Patents by Inventor Atsushi Nozoe
Atsushi Nozoe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6333871Abstract: Externally supplied program data is latched into data latch circuits DLL and DLR. A judgment is made as to whether or not the latched program data corresponds to any threshold value of multi-levels every time each of plural programing operations is carried out. The program control information corresponding to the judgment result is latched into a sense latch circuit SL. Based upon the latched program control information, the programing operation for setting threshold voltages having multi-levels to a memory cell is carried out in a stepwise manner. Even when the programing operation is ended, the externally supplied program data is left in the data latch circuit. Even when the programing operation of the memory cell is retried due to the overprograming condition, the program data is no longer required to be again received from the external device.Type: GrantFiled: March 30, 2000Date of Patent: December 25, 2001Assignee: Hitachi, Ltd.Inventors: Tetsuya Tsujikawa, Atsushi Nozoe, Michitaro Kanamitsu, Shoji Kubono, Eiji Yamamoto, Ken Matsubara
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Patent number: 6320793Abstract: A non-volatile memory device having a plurality of memory cells and a control circuit. The control circuit receives operation commands from outside the device and controls the operation of the device according to the commands. The commands include read commands and write commands. In the read command the control circuit reads data in the memory cells and outputs it. In a write command the control circuit controls the inputting of data to data latch circuits and then to memory cells. The control circuit provides status information indicating whether the writing of data is a success or a failure.Type: GrantFiled: March 30, 2001Date of Patent: November 20, 2001Assignee: Hitachi, Ltd.Inventors: Tetsuya Tsujikawa, Atsushi Nozoe, Michitaro Kanamitsu, Shoji Kubono, Eiji Yamamoto, Ken Matsubara
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Patent number: 6301150Abstract: Data are generated based on additional write data input to data latch circuits (DLR and DLL) and data read from memory cells (MC) to program non-volatile memory cells in a write state into the same write state and to program non-volatile memory cells in an erase state into a write state indicated by the additional write data. The generated data are latched in the data latch circuits to perform a logical synthesis process for additional writing. Even after the additional write operation, the logically synthesized data remain in the data latch circuits, and the latched data can be reused against abnormality in writing. This eliminates the need for receiving write data again from the outside when the additional write operation is to be retried.Type: GrantFiled: April 28, 2000Date of Patent: October 9, 2001Assignee: Hitachi, Ltd.Inventors: Michitaro Kanamitsu, Tetsuya Tsujikawa, Toshinori Harada, Hiroaki Kotani, Shoji Kubono, Atsushi Nozoe, Takayuki Yoshitake
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Patent number: 6285597Abstract: A control of a flash memory includes control for supplying a pulse-shaped voltage to each of non-volatile memory cells until a threshold voltage of the non-volatile memory cell having a first threshold voltage is changed to a second threshold voltage. The control involves a first write mode (coarse write) in which the amount of change in threshold voltage of each non-volatile memory cell, which is varied each time the pulse-shaped voltage is applied, is relatively rendered high, and a second write mode (high-accuracy write) in which the amount of change in threshold voltage thereof is relatively rendered low. As compared with the high-accuracy mode, the number of pulses required to change the threshold voltage of each memory cell is smaller than that in the coarse write mode. Therefore, the number of verify operations at the time that the coarse write mode is used, is small and hence the entire write operation can be speeded up.Type: GrantFiled: November 29, 2000Date of Patent: September 4, 2001Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corp.Inventors: Takayuki Kawahara, Hiroshi Sato, Atsushi Nozoe, Keiichi Yoshida, Satoshi Noda, Shoji Kubono, Hiroaki Kotani, Katsutaka Kimura
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Publication number: 20010010644Abstract: Externally supplied program data is latched into data latch circuits DLL and DLR. A judgment is made as to whether or not the latched program data corresponds to any threshold value of multi-levels every time each of plural programing operations is carried out. The program control information corresponding to the judgment result is latched into a sense latch circuit SL. Based upon the latched program control information, the programing operation for setting threshold voltages having multi-levels to a memory cell is carried out in a stepwise manner. Even when the programing operation is ended, the externally supplied program data is left in the data latch circuit. Even when the programing operation of the memory cell is retried due to the overprograming condition, the program data is no longer required to be again received from the external device.Type: ApplicationFiled: March 30, 2001Publication date: August 2, 2001Inventors: Tetsuya Tsujikawa, Atsushi Nozoe, Michitaro Kanamitsu, Shoji Kubono, Eiji Yamamoto, Ken Matsubara
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Publication number: 20010009520Abstract: Externally supplied program data is latched into data latch circuits DLL and DLR. A judgment is made as to whether or not the latched program data corresponds to any threshold value of multi-levels every time each of plural programing operations is carried out. The program control information corresponding to the judgment result is latched into a sense latch circuit SL. Based upon the latched program control information, the programing operation for setting threshold voltages having multi-levels to a memory cell is carried out in a stepwise manner. Even when the programing operation is ended, the externally supplied program data is left in the data latch circuit. Even when the programing operation of the memory cell is retried due to the over programming condition, the program data is no longer required to be again received from the external device.Type: ApplicationFiled: March 30, 2001Publication date: July 26, 2001Inventors: Tetsuya Tsujikawa, Atsushi Nozoe, Michitaro Kanamitsu, Shoji Kubono, Eiji Yamamoto, Ken Matsubara
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Patent number: 6243313Abstract: In order to eliminate erroneous reading of data by preventing noise which might otherwise be transmitted at the data read time through parasitic capacitance in the data lines to other data lines, switches (Qt1 and Qt1′) are interposed between a sense amplifier (SA) for amplifying the potential of a data line (DL) and the data line, and the sense amplifier is fed with an operating voltage after the potential of the data line is transmitted to the sense amplifier, and the switch is turned off.Type: GrantFiled: July 18, 2000Date of Patent: June 5, 2001Assignee: Hitachi, Ltd.Inventors: Yoshinori Sakamoto, Tatsuya Ishii, Atsushi Nozoe, Hitoshi Miwa, Kazuyoshi Oshima
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Patent number: 6233174Abstract: A nonvolatile semiconductor memory device having a plurality of memory cells. Each cell stores data and has a threshold voltage corresponding to the data. A controller controls a partial erase operation in response to a command. This operation includes selecting memory cells in two groups, storing the data in a data latch, writing erase data indicating an erase state, erasing data of selected cells and programming the data stored in the data latch to selected memory cells and programming the erased data to selected memory cells.Type: GrantFiled: March 30, 2000Date of Patent: May 15, 2001Assignee: Hitachi, Ltd.Inventors: Tetsuya Tsujikawa, Atsushi Nozoe, Michitaro Kanamitsu, Shoji Kubono, Eiji Yamamoto, Ken Matsubara
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Patent number: 6226212Abstract: In order to eliminate erroneous reading of data by preventing noise which might otherwise be transmitted at the data reading time through parasitic capacitance in the data lines to other data lines, switches (Qt1 and Qt1′) are interposed between a sense amplifier (SA) for amplifying the potential of a data line (DL) and the data line, and the sense amplifier is fed with an operating voltage after the potential of the data line is transmitted to the sense amplifier, and the switch is turned off.Type: GrantFiled: March 31, 1998Date of Patent: May 1, 2001Assignee: Hitachi, Ltd.Inventors: Yoshinori Sakamoto, Tatsuya Ishii, Atsushi Nozoe, Hitoshi Miwa, Kazuyoshi Oshima
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Publication number: 20010000023Abstract: A control of a flash memory includes control for supplying a pulse-shaped voltage to each of non-volatile memory cells until a threshold voltage of the non-volatile memory cell having a first threshold voltage is changed to a second threshold voltage. The control involves a first write mode (coarse write) in which the amount of change in threshold voltage of each non-volatile memory cell, which is varied each time the pulse-shaped voltage is applied, is relatively rendered high, and a second write mode (high-accuracy write) in which the amount of change in threshold voltage thereof is relatively rendered low. As compared with the high-accuracy mode, the number of pulses required to change the threshold voltage of each memory cell is smaller than that in the coarse write mode. Therefore, the number of verify operations at the time that the coarse write mode is used, is small and hence the entire write operation can be speeded up.Type: ApplicationFiled: November 29, 2000Publication date: March 15, 2001Inventors: Takayuki Kawahara, Hiroshi Sato, Atsushi Nozoe, Keiichi Yoshida, Satoshi Noda, Shoji Kubono, Hiroaki Kotani, Katsutaka Kimura
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Patent number: 6163485Abstract: A control of a flash memory includes control for supplying a pulse-shaped voltage to each of non-volatile memory cells until a threshold voltage of the non-volatile memory cell having a first threshold voltage is changed to a second threshold voltage. The control involves a first write mode (coarse write) in which the amount of change in threshold voltage of each non-volatile memory cell, which is varied each time the pulse-shaped voltage is applied, is relatively rendered high, and a second write mode (high-accuracy write) in which the amount of change in threshold voltage thereof is relatively rendered low. As compared with the high-accuracy mode, the number of pulses required to change the threshold voltage of each memory cell is smaller than that in the coarse write mode. Therefore, the number of verify operations at the time that the coarse write mode is used, is small and hence the entire write operation can be speeded up.Type: GrantFiled: March 9, 2000Date of Patent: December 19, 2000Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corp.Inventors: Takayuki Kawahara, Hiroshi Sato, Atsushi Nozoe, Keiichi Yoshida, Satoshi Noda, Shoji Kubono, Hiroaki Kotani, Katsutaka Kimura
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Patent number: 6134148Abstract: A control of a flash memory includes control for supplying a pulse-shaped voltage to each of non-volatile memory cells until a threshold voltage of the non-volatile memory cell having a first threshold voltage is changed to a second threshold voltage. The control involves a first write mode (coarse write) in which the amount of change in threshold voltage of each non-volatile memory cell, which is varied each time the pulse-shaped voltage is applied, is relatively rendered high, and a second write mode (high-accuracy write) in which the amount of change in threshold voltage thereof is relatively rendered low. As compared with the high-accuracy mode, the number of pulses required to change the threshold voltage of each memory cell is smaller than that in the coarse write mode. Therefore, the number of verify operations at the time that the coarse write mode is used, is small and hence the entire write operation can be speeded up.Type: GrantFiled: August 20, 1999Date of Patent: October 17, 2000Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corp.Inventors: Takayuki Kawahara, Hiroshi Sato, Atsushi Nozoe, Keiichi Yoshida, Satoshi Noda, Shoji Kubono, Hiroaki Kotani, Katsutaka Kimura
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Patent number: 6091640Abstract: A control of a flash memory includes control for supplying a pulse-shaped voltage to each of non-volatile memory cells until a threshold voltage of the non-volatile memory cell having a first threshold voltage is changed to a second threshold voltage. The control involves a first write mode (coarse write) in which the amount of change in threshold voltage of each non-volatile memory cell, which is varied each time the pulse-shaped voltage is applied, is relatively rendered high, and a second write mode (high-accuracy write) in which the amount of change in threshold voltage thereof is relatively rendered low. As compared with the high-accuracy mode, the number of pulses required to change the threshold voltage of each memory cell is smaller than that in the coarse write mode. Therefore, the number of verify operations at the time that the coarse write mode is used, is small and hence the entire write operation can be speeded up.Type: GrantFiled: September 30, 1997Date of Patent: July 18, 2000Assignees: Hitachi, Ltd., Hitachi ULSLI Engineering Corp.Inventors: Takayuki Kawahara, Hiroshi Sato, Atsushi Nozoe, Keiichi Yoshida, Satoshi Noda, Shoji Kubono, Hiroaki Kotani, Katsutaka Kimura
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Patent number: 6078519Abstract: Data are generated based on additional write data input to data latch circuits (DLR and DLL) and data read from memory cells (MC) to program non-volatile memory cells in a write state into the same write state and to program non-volatile memory cells in an erase state into a write state indicated by the additional write data. The generated data are latched in the data latch circuits to perform a logical synthesis process for additional writing. Even after the additional write operation, the logically synthesized data remain in the data latch circuits, and the latched data can be reused against abnormality in writing. This eliminates the need for receiving write data again from the outside when the additional write operation is to be retried.Type: GrantFiled: May 25, 1999Date of Patent: June 20, 2000Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Michitaro Kanamitsu, Tetsuya Tsujikawa, Toshinori Harada, Hiroaki Kotani, Shoji Kubono, Atsushi Nozoe, Takayuki Yoshitake
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Patent number: 6046936Abstract: Externally supplied program data is latched into data latch circuits DLL and DLR. A judgment is made as to whether or not the latched program data corresponds to any threshold value of multi-levels every time each of plural programing operations is carried out. The program control information corresponding to the judgment result is latched into a sense latch circuit SL. Based upon the latched program control information, the programing operation for setting threshold voltages having multi-levels to a memory cell is carried out in a stepwise manner. Even when the programing operation is ended, the externally supplied program data is left in the data latch circuit. Even when the programing operation of the memory cell is retried due to the overprograming condition, the program data is no longer required to be again received from the external device.Type: GrantFiled: February 16, 1999Date of Patent: April 4, 2000Assignee: Hitachi, Ltd.Inventors: Tetsuya Tsujikawa, Atsushi Nozoe, Michitaro Kanamitsu, Shoji Kubono, Eiji Yamamoto, Ken Matsubara
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Patent number: 5581508Abstract: In a semiconductor memory apparatus having a row decoder classified by main word lines and word lines, the number of spare lines for a defect is increased without increasing the number of spare main word lines. The area of a redundancy circuit is minimized to improve the yield of chip. Normal and spare memory blocks each including a plurality of memory cells are each divided so that replacement may be effected without increasing the number of spare main word lines even when defective addresses associated with a plurality of normal main word lines take place.Type: GrantFiled: December 9, 1994Date of Patent: December 3, 1996Assignee: Hitachi, Ltd.Inventors: Toshio Sasaki, Toshihiro Tanaka, Atsushi Nozoe, Hitoshi Kume
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Patent number: 5506804Abstract: A Bi.CMOS semiconductor memory device is provided which includes an arrangement to simultaneously select a plurality of memory cells, followed by using a 3 bit Z addressing arrangement to determine a read or write operation for the simultaneously selected memory cells. To speed up the word line selection, a static selection type operation is used with the word line selecting voltage being greater than signal amplitude of the data lines during the write operation. Also, to speed up the read operation, separate common I/O lines are provided for the read and write operations. Read signals are transmitted as current signals, and then converted to voltage signals for improving reading speed. Also, improved arrangements are provided for resistance structure, logic circuitry, input circuitry, fuse cutting circuitry, drive circuitry, power circuitry, electrostatic protection circuitry, layout structure and testing methods for the semiconductor device.Type: GrantFiled: November 30, 1993Date of Patent: April 9, 1996Assignees: Hitachi, Ltd., VLSI Engineering Corp.Inventors: Kazumasa Yanagisawa, Tatsuyuki Ohta, Tetsu Udagawa, Kyoko Ishii, Hitoshi Miwa, Atsushi Nozoe, Masayuki Nakamura, Tetsurou Matsumoto, Yoshitaka Kinoshita, Yoshiaki Ouchi, Hiromi Tsukada, Shoji Wada, Kazuo Mihashi, Yutaka Kobayashi, Goro Kitsukawa
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Patent number: 5276648Abstract: A Bi.CMOS semiconductor memory device is provided which includes an arrangement to simultaneously select a plurality of memory cells, followed by using a 3 bit Z addressing arrangement to determine a read or write operation for the simultaneously selected memory cells. To speed up the word line selection, a static selection type operation is used with the word line selecting voltage being greater than signal amplitude of the data lines during the write operation. Also, to speed up the read operation, separate common I/O lines are provided for the read and write operations. Read signals are transmitted as current signals, and then converted to voltage signals for improving reading speed. Also, improved arrangements are provided for resistance structure, logic circuitry, input circuitry, fuse cutting circuitry, drive circuitry, power circuitry, electrostatic protection circuitry, layout structure and testing methods for the semiconductor device.Type: GrantFiled: January 8, 1992Date of Patent: January 4, 1994Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.Inventors: Kazumasa Yanagisawa, Tatsuyuki Ohta, Tetsu Udagawa, Kyoko Ishii, Hitoshi Miwa, Atsushi Nozoe, Masayuki Nakamura, Tetsurou Matsumoto, Yoshitaka Kinoshita, Yoshiaki Ouchi, Hiromi Tsukada, Shoji Wada, Kazuo Mihashi, Yutaka Kobayashi, Goro Kitsukawa
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Patent number: 5150325Abstract: A Bi.CMOS semiconductor memory device is provided which includes an arrangement to simultaneously select a plurality of memory cells, followed by using a 3 bit Z addressing arrangement to determine a read or write operation for the simultaneously selected memory cells. To speed up the word line selection, a static selection type operation is used with the word line selecting voltage being greater than signal amplitude of the data lines during the write operation. Also, to speed up the read operation, separate common I/O lines are provided for the read and write operations. Read signals are transmitted as curent signals, and then converted to voltage signals for improving reading speed. Also, improved arrangements are provided for resistance structure, logic circuitry, input circuitry, fuse cutting circuitry, drive circuitry, power circuitry, electrostatic protection circuitry, layout structure and testing methods for the semiconductor device.Type: GrantFiled: March 20, 1990Date of Patent: September 22, 1992Assignees: Hitachi, Ltd., Hitachi VLSI Engineering CorpInventors: Kazumasa Yanagisawa, Tatsuyuki Ohta, Tetsu Udagawa, Kyoko Ishii, Hitoshi Miwa, Atsushi Nozoe, Masayuki Nakamura, Tetsurou Matsumoto, Yoshitaka Kinoshita, Yoshiaki Ouchi, Hiromi Tsukada, Shoji Wada, Kazuo Mihashi, Yutaka Kobayashi, Goro Kitsukawa