Abstract: A fragrance composition comprising a compound represented by Formula (1): wherein, in Formula (1), R represents a linear, branched, or cyclic alkyl group having 2 to 6 carbon atoms.

Abstract: A method for producing an ?-acyloxycarboxylic acid ester of Formula (1) is described. The method involves reacting an ?-hydroxycarboxylic acid ester compound with an acylating agent in the presence of a catalyst comprising an iron halide compound. R1 represents a hydrogen atom, a methyl group, an ethyl group, an n-propyl group, an isopropyl group, or a tert-butyl group, R2 and R3 each independently represent a methyl group or an ethyl group, and R4 represents a linear, branched, or cyclic alkyl group having from 1 to 6 carbon atoms.

Abstract: A hot water supply apparatus includes a heat exchanger that heats water for hot water supply, a pressure controller provided in a subsequent stage of the heat exchanger, and a trap that promotes deposition of scale. The pressure controller pressurizes the water for hot water supply. The trap is provided in a subsequent stage of the pressure controller.

Abstract: A compound, represented by Formula (1): where X represents an isopropyl group or a t-butyl group, and R represents a linear, branched, or cyclic alkyl group having 1 to 5 carbon atoms; provided that one where X is an isopropyl group, and R is a t-butyl group is excluded.

Abstract: A memory system according to an embodiment includes a nonvolatile memory and a memory controller. The nonvolatile memory includes a first storage region and a second storage region. The memory controller comprises a third storage region storing a master table and a fourth storage region storing a change history of the master table. The memory controller is configured to: order the nonvolatile memory to write the master table stored in the third storage region in the first storage region when receiving a power-off command from outside; order the nonvolatile memory to write the change history stored in the fourth storage region in the second storage region.

Abstract: A controller performs a first operation in which a heat source device directly or indirectly heats water in a first channel of a heat exchanger and a second operation in which the heat source device directly or indirectly cools the water in the first channel of the heat exchanger after the first operation ends.

Abstract: A semiconductor device has: a first chip having a substrate and a first wiring layer; and a second wiring layer formed on a second surface of the substrate. The second wiring layer has a first power supply line, and a second power supply line. The first chip has a first ground line, a third power supply line, a fourth power supply line, vias formed in the substrate and connecting the first power supply line and the third power supply line, a first area in which the first ground line and the fourth power supply line are arranged, and a first circuit connected between the first ground line and the third power supply line. A switch is connected between the first power supply line and the second power supply line. In a plan view, the third power supply line, the vias, and the first circuit are arranged in the first area.

Abstract: A semiconductor device includes a chip that includes a substrate and a first interconnection layer on a surface of the substrate; and a second interconnection layer on another surface opposite to the surface of the substrate. The second interconnection layer includes a first power line having a first power potential, a second power line having a second power potential, and a switch between the first power line and the second power line. The chip includes a first grounding line, a third power line having the second power potential, a first region having the first grounding line and the third power line, a second grounding line, a fourth power line having the first power potential, and a second region having the second grounding line and the fourth power line. In plan view, the switch is between the first region and the second region.

Abstract: A semiconductor device includes first and second power supply lines formed in a first wiring layer and extending in a first direction; third and fourth power supply lines formed in a second wiring layer, extending in a second direction, and connected to the first and second power supply lines, respectively; a fifth power supply line formed in the first wiring layer; and a first power switch circuit including a transistor provided between the first and fifth power supply lines. The transistor overlaps at least one of the third and fourth power supply lines. The first power switch circuit includes first and second wirings formed in the second wiring layer, extending in the second direction, not overlapping the third and fourth power supply lines, and connected to a source of the transistor and the fifth power supply line, and to a drain and the third power supply line, respectively.

Abstract: A semiconductor device includes a first chip including a substrate and a first interconnection layer formed on a first surface of the substrate; and a second interconnection layer formed on a second surface opposite to the first surface of the substrate. The second interconnection layer includes a first power line to which a first power potential is applied, a second power line to which a second power potential is applied, and a first switch connected between the first power line and the second power line. The first chip includes a first grounding line, a third power line to which the second power potential is applied, and a first region in which the first grounding line and the third power line are disposed. In plan view, the first switch overlaps the first region.

Abstract: A semiconductor device includes a first area including a logic circuit, a second area including a functional circuit, a first power line, a second power line that supplies a power to the logic circuit and the functional circuit, and a first power switch circuit connected to the first power line and the second power line, wherein the first power switch circuit includes a first transistor larger than a transistor provided in the logic circuit and being connected to the first power line and the second power line, an end cap provided in an area next to the functional circuit, and a second transistor provided between the end cap and an area including the first transistor, the second transistor being of a same size as the transistor provided in the logic circuit and being connected to the first power line and the second power line.

Abstract: A compound, represented by Formula (1): wherein, in Formula (1), R represents a linear, branched, or cyclic alkyl group having 1 to 4 carbon atoms.

Abstract: An air conditioning system includes a refrigerant cycle, a power feed unit, a controller, and a processor. The refrigerant cycle includes an outdoor unit and a plurality of indoor units. The outdoor unit includes a compressor. In a case where a power source for at least one indoor unit of the plurality of indoor units is interrupted, the power feed unit feeds power from an auxiliary power source to the at least one indoor unit. The controller controls at least the compressor. In the case where the power source for the at least one indoor unit of the plurality of indoor units is interrupted, the processor makes one of a determination to stop the compressor and a determination to cause the compressor to continue operating. The processor transmits to the controller an instruction corresponding to the determination that has been made.

Abstract: Provided is an air conditioning system capable of detecting in advance a device that consumes more power than the power that can be fed by a power feed unit. An air conditioning system includes a refrigerant cycle, a power feed unit, and a controller. The refrigerant cycle includes an outdoor unit and a plurality of indoor units. In a case where a power source for at least one indoor unit of the plurality of indoor units has been interrupted, the power feed unit feeds power from an auxiliary power source to the indoor unit for which the power source has been interrupted. When a predetermined device has been connected to at least part of the plurality of indoor units and the power feed unit, the controller performs deactivation of at least one of functions of the device.

Abstract: A fragrance composition comprising a compound represented by Formula (1) as an active ingredient: wherein, in Formula (1), R1 represents a linear, branched, or cyclic alkyl group having 1 to 6 carbon atoms.

Abstract: A power switch cell using vertical nanowire (VNW) FETs includes a switch element configured to be capable of switching between electrical connection and disconnection between a global power interconnect and a local power interconnect. The switch element is constituted by at least one VNW FET. The top electrode of the VNW FET constituting the switch element is connected with the global power interconnect.

Abstract: A memory system according to an embodiment includes a nonvolatile memory and a memory controller. The nonvolatile memory includes a first storage region and a second storage region. The memory controller comprises a third storage region storing a master table and a fourth storage region storing a change history of the master table. The memory controller is configured to: order the nonvolatile memory to write the master table stored in the third storage region in the first storage region when receiving a power-off command from outside; order the nonvolatile memory to write the change history stored in the fourth storage region in the second storage region.

Abstract: A semiconductor device includes a first power supply line, a second power supply line, a first ground line, a switch circuit connected to the first and the second power supply line, and a switch control circuit connected to the first ground line and the first power supply line. The switch circuit includes a first and a second transistor of a first conductive type. A first gate electrode of the first transistor is connected to a second gate electrode of the second transistor. The switch control circuit includes a third transistor of a second conductive type, and a fourth transistor of a third conductive type. A third gate electrode of the third transistor is connected to a fourth gate electrode of the fourth transistor. A semiconductor device includes a signal line that electrically connects a connection point between the third and fourth transistor to the first and second gate electrode.

Abstract: A semiconductor device includes a substrate; first and second fins protruding from the substrate; a first transistor including the first fin; a second transistor above the first transistor; and a first power supply line electrically connected to the first fin through the second fin. The first transistor includes first and second impurity areas in the first fin, and a first gate insulating film on the first fin between the first and second impurity areas. The second transistor includes a first semiconductor area above the first fin, a third impurity area in the first semiconductor area above the first impurity area, a fourth impurity area in the first semiconductor area above the second impurity area, and a second gate insulating film on the first semiconductor area between the third and fourth impurity areas. The first and second transistors have a common gate on the first and second gate insulating films.

Abstract: A semiconductor device includes a semiconductor substrate, a first standard cell including a first active region and a second active region, and a power switching circuit including a first switching transistor electrically connected between a first interconnect and a second interconnect over the semiconductor substrate, and including a first buffer connected to a gate of the first switching transistor, the first buffer including a third active region and a fourth active region, and wherein the first buffer adjoins, in a plan view, the first standard cell in a first direction, wherein an arrangement of the first active region matches an arrangement of the third active region in a second direction different from the first direction, and wherein an arrangement of the second active region matches an arrangement of the fourth active region in the second direction.