Abstract: A semiconductor memory device according to an embodiment described below comprises: first lines arranged in a first direction perpendicular to a main surface of a substrate and extending in a second direction crossing the first direction; second lines arranged in the second direction, extending in the first direction, and intersecting the first lines; memory cells disposed at intersections of the first lines and the second lines; and an interlayer insulating film provided between the second lines. The interlayer insulating film has an air gap extending continuously in the first direction so as to intersect at least some of the first lines aligned along the first direction. The interlayer insulating film also includes an insulating film positioned above the air gap and having a curved surface that protrudes toward a direction of the substrate.

Abstract: In a bus system including a bus master, a first bus, and a second bus to connect them together, this router is arranged on the second bus to relay packets. The bus master outputs packets including information about at least one of (N+1) predetermined types of quality requirements. The second bus transmits packets designating at most N types of quality requirements. An exemplary router controls sending of the packets, with respect to at most N types of buffers that classify and store the packets by reference to the quality requirement type information and the packets stored in the buffers, so that the packets are sent in the descending order of their level of the quality requirement. The router controls sending schedule of the traffic flows by sensing a difference between the (N+1) different types of quality requirements.

Abstract: This semiconductor memory device comprises a memory cell array that includes: a plurality of first lines; a plurality of second lines intersecting the plurality of first lines; a plurality of memory cells each disposed at an intersection of the plurality of first lines and the plurality of second lines and including a variable resistance element; and a select transistor respectively connected to an end of the plurality of first lines. The select transistor includes a gate electrode, a gate insulating film, and a conductive layer. Moreover, one end of that conductive layer is connected to the end of the first line, and a non-linear resistance layer configured from a non-linear material is connected between the first line and the conductive layer.

Abstract: An ink jet recording method includes discharging a ultraviolet curable ink of which viscosity is 7 mPa·s or more at 20° C. from a head toward a recording medium, and curing the ultraviolet curable ink adhered to the recording medium, wherein, in the discharging, the temperature of the ultraviolet curable ink discharged is 20 to 30° C., and the viscosity of the ultraviolet curable ink at the temperature is 13 mPa·s or less.

Abstract: A motor includes: an end bell mounted on an opening of a cylindrical rotor housing for housing a rotor and is provided with a power-feeding path to the rotor; and a choke coil connected in the middle of the power-feeding path. The choke coil overlaps at least a part of the rotor housing as viewed from outside the rotor housing in a radial direction and as viewed in a direction perpendicular to an axial direction, and is arranged such that a longitudinal direction thereof extends along a direction parallel to a rotating shaft of the motor.

Abstract: A three-dimensional image processor includes an aspect conversion discriminator, an aspect conversion parameter generator, a 2D/3D conversion parameter generator, a frame memory unit and a read address controller. The aspect conversion discriminator generates a signal indicating whether or not a read position of a video signal is to be modified. The aspect conversion parameter generator generates a parameter indicating an aspect ratio of an image based on the video signal. The 2D/3D conversion parameter generator generates shift amounts for generating a left-eye signal and a right-eye signal based on the video signal. The frame memory unit temporarily stores the video signal. The read address controller controls the read position of the video signal based on the parameter and the shift amounts when the signal received from the aspect conversion discriminator indicates that the read position is to be modified.

Abstract: A semiconductor memory device comprises: first lines disposed in a first direction perpendicular to a substrate and extending in a second direction parallel to the substrate; second lines disposed in the second direction and configured to extend in the first direction, the second lines intersecting the first lines; and memory cells disposed at intersections of the first lines and the second lines and each including a variable resistance element. Furthermore, a third line extends in a third direction orthogonal to the first and second directions. A select transistor is connected between the second and third lines. A control circuit controls a voltage applied to the first and third lines, and the select transistor. The control circuit renders conductive at least one of the select transistors and thereby detect a current flowing in the third line, and determines a deterioration state of the select transistor according to a detection result.

Abstract: A liquid ejecting apparatus includes a liquid ejecting head that ejects a plurality of kinds of photocurable type liquids, an irradiation unit that irradiates light that cures the liquids, a liquid receiving portion that is capable of receiving the liquids that are ejected from the liquid ejecting head, and a control unit that controls the ejection of the liquids from the liquid ejecting head. Among the plurality of kinds of liquids that are ejected, the control unit ejects a liquid that is cured with most ease when the light is irradiated before at least one different liquid other than the liquid in a case in which the plurality of kinds of liquids are ejected into the liquid receiving portion from the liquid ejecting head.

Abstract: A router includes an input section configured to receive data, a buffer section including a plurality of data storage sections and configured to store the data received by the input section, and an output section configured to output the data stored on the buffer section. The router also includes an allocation processing section configured to determine whether or not to store the data on a pre-secured specific data storage section among the plurality of data storage sections, or whether or not to store the data on a pre-secured specific data storage section among a plurality of data storage sections in a buffer section of another router which is an output destination, the determination being made based on information representing burstiness of the data received by the input section.

Abstract: A nonvolatile semiconductor memory device according to an embodiment includes a control circuit configured to cause data to be stored in a memory cell by setting the memory cell to be included in one of resistance value distributions. The control circuit is configured to set a first resistance value distribution and a second resistance value distribution, the second resistance value distribution having a resistance value larger than that of the first resistance value distribution, and to set a second width to be larger than a first width, the second width being a width between a second upper limit value of the second resistance value distribution and a second lower limit value of the second resistance value distribution, and the first width being a width between a first upper limit value of the first resistance value distribution and a first lower limit value of the first resistance value distribution.

Abstract: According to an embodiment, a non-volatile memory device includes a first wiring extending in a first direction, a second wiring extending in a second direction orthogonal to the first direction. The device includes third wirings, and a first and a second memory. The third wirings extend in a third direction crossing the first direction and orthogonal to the second direction, and aligned in the second direction on both sides of the second wiring. The first memory is provided between one of third wiring pair and the second wiring, the pair of third wirings facing each other across the second wiring. The second memory is provided between another one of the third wiring pair and the second wiring. The second wiring has a block portion between a first portion in contact with the first memory and a second portion in contact with the second memory.

Abstract: In an NoC bus system, data is transmitted between first and second nodes through a router. The data includes performance-ensuring data which guarantees throughput and/or a permitted time delay. The first node generates packets, each including the data to be transmitted and classification information that indicates the class of that data to be determined according to its required performance, and controls transmission of the packets. The router includes a buffer section configured to store the received packets separately after having classified the packets according to their required performance by reference to the classification information, and a relay controller configured to control transmission of the packets stored in the buffer section at a transmission rate which is equal to or higher than the sum of transmission rates to be guaranteed for every first node associated with the classification information by reference to each piece of the classification information.

Abstract: An exemplary router is provided for an integrated circuit that has distributed buses and is arranged on a transmission route that leads from a transmission node to a reception node on the distributed buses to relay data. The distributed buses include first and second routes, each leading from the router to the reception node. The router includes a notifying section which sends a data transfer permission request to a second router on the first route and a third router on the second route and which determines whether or not the request is approved before a predetermined standby period passes to see if there is any abnormality in the first and second routes.

Abstract: A controller as an embodiment of the present disclosure controls a timing of transmitting an access request that has been received from an initiator (or its transmission interval). The controller includes: transmitting and receiving circuitry configured to receive an access request related to burst accesses from a first initiator that is connected via a first bus to, and adjacent to, the transmitting and receiving circuitry and configured to transmit the access request to a second bus implemented as a network; and a transmission interval controller configured to control the timing of transmitting the access request that has been received from the first initiator according to density of the burst accesses during a period in which the burst accesses continue and an access load on the second bus.

Abstract: A liquid ejecting apparatus includes an ejecting head that is enabled to eject a liquid; a liquid supply portion for supplying the liquid from a liquid supply source to the ejecting head; a holding frame that holds the ejecting head, the liquid supply source and the liquid supply portion; and a movement mechanism that moves the holding frame. The liquid supply portion has a flow channel forming portion that forms a liquid flow channel connecting the liquid supply source and the ejecting head and a flow channel holding portion that holds the flow channel forming portion in a swayable manner.

Abstract: A bellows pump with a case member that forms an axial space therein, closed-bottomed cylindrical bellows that are arranged in the space in an axially extendable/contractable manner and axially separate the space into a pump chamber and an operation chamber, suction valves that are provided on a suction side of the pump chamber and guide a fluid to be transferred to the pump chamber, and discharge valves that are provided on a discharge side of the pump chamber and discharge the fluid to be transferred from the pump chamber, and which extends/contracts the bellows by introducing a working fluid into the operation chamber to discharge the working fluid from the operation chamber, wherein each of the bellows is configured by alternately forming mountain portions and valley portions along the axial direction and having, on a predetermined position in the axial direction, annular ring portion integrally formed therewith.