Patents by Inventor Atsushi Yoshida

Atsushi Yoshida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160008333
    Abstract: The present invention relates to a prophylactic or therapeutic agent for a posterior ocular disease containing the compound represented by a formula (1), its enantiomer or diastereomer, or their pharmaceutically acceptable salt thereof as an active ingredient.
    Type: Application
    Filed: February 27, 2014
    Publication date: January 14, 2016
    Applicant: SANTEN PHARMACEUTICAL CO., LTD.
    Inventors: Atsushi YOSHIDA, Sae AKAO, Shinji YONEDA, Komei OKABE, Tomomi KOHARA
  • Patent number: 9224469
    Abstract: A semiconductor memory device according to an embodiment includes a memory cell array and a control circuit. The memory cell array includes first lines and second lines intersecting each other, a third line commonly connecting to the first lines, memory cells disposed at intersections of the first lines and the second lines, respectively. The control circuit is configured to execute a state determining operation detecting a voltage of the third line, and adjust a voltage applied to the first lines and the second lines during a resetting operation or a setting operation based on a result of the state determining operation. The resetting operation raises a resistance value of the variable resistance element. The setting operation lowers the resistance value of the variable resistance element.
    Type: Grant
    Filed: June 16, 2014
    Date of Patent: December 29, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yoichi Minemura, Takayuki Tsukamoto, Hiroshi Kanno, Takamasa Okawa, Atsushi Yoshida, Hideyuki Tabata
  • Publication number: 20150367635
    Abstract: An ink jet recorder includes a support unit configured to support a recording medium, and a mobile unit including a plurality of containers containing inks of identical composition and a head configured to eject the ink supplied from any one of the plurality of containers. The ink jet recorder is configured to record an image on the recording medium in such a manner that the head performs main scanning by ejecting the ink while changing positions in a first direction, and the mobile unit performs sub-scanning by moving in a second direction intersecting with the first direction.
    Type: Application
    Filed: September 1, 2015
    Publication date: December 24, 2015
    Inventors: Keita ICHIHARA, Atsushi YOSHIDA, Masaki UCHIYAMA, Hiroyuki ITO, Mitsuaki YOSHIZAWA
  • Patent number: 9214228
    Abstract: A semiconductor memory device has a memory cell array including memory cells, the memory cell being disposed at an intersection of first lines and second lines, the second lines being disposed intersecting the first lines, and the memory cell including a variable resistance element; and a control circuit. The control circuit is configured to execute a forming operation sequentially on a plurality of the memory cells. The control circuit applies a forming voltage to a selected memory cell of the memory cells, and controls the forming voltage such that the forming voltage is lower as the forming operation progresses.
    Type: Grant
    Filed: December 13, 2013
    Date of Patent: December 15, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takamasa Okawa, Takayuki Tsukamoto, Yoichi Minemura, Hiroshi Kanno, Atsushi Yoshida
  • Patent number: 9189013
    Abstract: This controller is used in a system in which initiators and targets are connected via distributed buses to control transmission timing of an access request received from the initiators. The controller stores intermittent information including information about an intermittent period in which interference between packets can be restricted and bus operating frequency information indicating a bus operating frequency at which real-time performance is guaranteed for each initiator and which has been generated based on system configuration information and flow configuration information indicating, on a flow basis, a specification required for each initiator to access the target. The controller includes a clock generator; communications circuitry; and transmission interval setting circuitry which sets a time to send transmission permission responsive to a transmission request based on the intermittent period, a time when the transmission request is detected, and a previous transmission time.
    Type: Grant
    Filed: July 26, 2013
    Date of Patent: November 17, 2015
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Tomoki Ishii, Takao Yamaguchi, Atsushi Yoshida
  • Patent number: 9164944
    Abstract: Highly efficient and low latency network transmission in consideration of a difference in the traffic characteristic and a memory access load which changes moment by moment is realized. A relay device transmits data on a networked communication bus between a bus master and a memory. The relay device includes a delay time processor for obtaining information on processing delay time in other relay devices located on a plurality of transmission routes on which the data is transmitted; and a low latency route selector for selecting a memory and one of transmission routes to the memory, among the plurality of transmission routes, based on obtained information on the processing delay time regarding the plurality of transmission routes.
    Type: Grant
    Filed: October 28, 2011
    Date of Patent: October 20, 2015
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Takao Yamaguchi, Tomoki Ishii, Atsushi Yoshida
  • Patent number: 9156266
    Abstract: An ink jet recorder includes a support unit configured to support a recording medium, and a mobile unit including a plurality of containers containing inks of identical composition and a head configured to eject the ink supplied from any one of the plurality of containers. The ink jet recorder is configured to record an image on the recording medium in such a manner that the head performs main scanning by ejecting the ink while changing positions in a first direction, and the mobile unit performs sub-scanning by moving in a second direction intersecting with the first direction.
    Type: Grant
    Filed: March 18, 2014
    Date of Patent: October 13, 2015
    Assignee: Seiko Epson Corporation
    Inventors: Keita Ichihara, Atsushi Yoshida, Masaki Uchiyama, Hiroyuki Ito, Mitsuaki Yoshizawa
  • Patent number: 9144979
    Abstract: A liquid absorbing material, being provided in a liquid ejecting apparatus having a liquid ejecting head for ejecting liquid from nozzle openings formed on a nozzle forming surface, and being able to come into abutment with the liquid ejecting head so as to cover the nozzle openings and being stored in a cap having a discharge channel for discharging the liquid in the interior thereof, includes a body portion to be arranged in the cap when being stored in the cap, and a projecting portion arranged in the discharge channel.
    Type: Grant
    Filed: July 23, 2008
    Date of Patent: September 29, 2015
    Assignee: Seiko Epson Corporation
    Inventors: Atsushi Yoshida, Shinichi Kamoshida
  • Publication number: 20150267814
    Abstract: A spherical annular seal member 38 is used in an exhaust pipe joint and includes a spherical annular base member 36 defined by a cylindrical inner surface 32, a partially convex spherical surface 33, large- and small-diameter side annular end faces 34 and 35 of the partially convex spherical surface 33, and an outer layer 37 formed integrally on the partially convex spherical surface 33 of the spherical annular base member 36. The spherical annular base member 36 includes a reinforcing member made from a metal wire net 5 and a heat-resistant material containing expanded graphite filling meshes of the metal wire net 5 of this reinforcing member and compressed in such a manner as to be formed integrally with this reinforcing member in mixed form. In the outer layer 37, the reinforcing member, the heat-resistant material, and the solid lubricant are integrated in mixed form.
    Type: Application
    Filed: August 22, 2013
    Publication date: September 24, 2015
    Applicant: OILES CORPORATION
    Inventors: Atsushi Yoshida, Eiji Satou, Shin-ichi Shionoya, Ryota Koibuchi
  • Patent number: 9142290
    Abstract: According to one embodiment, a nonvolatile memory device includes: a memory cell array including first wirings, second wirings, and a memory cell connected between the first wirings and the second wirings; and a control circuit unit configured to select a selected memory cell from the memory cells, perform a first operation of changing a resistance state of the selected memory cell between a first resistance state and a second resistance state, and determine whether the first operation has been properly performed or not and perform retry operation such as applying a retry pulse when the first operation has not been properly performed. The control circuit unit regards the selected memory cell as excessive retry operation and inhibits the selected memory cell in accordance with the number of times of the excessive retry operation when the number of times of the retry operation is over k times.
    Type: Grant
    Filed: November 13, 2013
    Date of Patent: September 22, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Kanno, Yoichi Minemura, Takayuki Tsukamoto, Takamasa Okawa, Atsushi Yoshida
  • Publication number: 20150242261
    Abstract: A communication device includes: a receiving terminal; a storage device which stores a rule in which a condition regarding a bus system operation environment and an error tolerance scheme are associated with each other, and information regarding a path length; an error processor which determines the error tolerance scheme by utilizing the condition regarding the bus system operation environment and the rule so as to generate error tolerance information corresponding to the received data according to the determined error tolerance scheme; and a sending terminal for sending at least one packet including the error tolerance information and the data to the bus. The operation environment-related condition is a condition for granting an error tolerance for a transmission path of which a bus path length to another communication device, which is a destination of the data, is greater than a predetermined value.
    Type: Application
    Filed: May 11, 2015
    Publication date: August 27, 2015
    Inventors: Takao YAMAGUCHI, Atsushi YOSHIDA, Tomoki ISHII, Satoru TOKUTSU
  • Publication number: 20150228337
    Abstract: A semiconductor memory device comprises: first lines disposed in a first direction perpendicular to a substrate and extending in a second direction parallel to the substrate; second lines disposed in the second direction and configured to extend in the first direction, the second lines intersecting the first lines; and memory cells disposed at intersections of the first lines and the second lines and each including a variable resistance element. Furthermore, a third line extends in a third direction orthogonal to the first and second directions. A select transistor is connected between the second and third lines. A control circuit controls a voltage applied to the first and third lines, and the select transistor. The control circuit renders conductive at least one of the select transistors and thereby detect a current flowing in the third line, and determines a deterioration state of the select transistor according to a detection result.
    Type: Application
    Filed: June 17, 2014
    Publication date: August 13, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takamasa OKAWA, Takayuki Tsukamoto, Yoichi Minemura, Hiroshi Kanno, Atsushi Yoshida, Hideyuki Tabata
  • Publication number: 20150221368
    Abstract: A semiconductor memory device according to an embodiment includes a memory cell array and a control circuit. The memory cell array includes: a plurality of first conductive layers that are stacked; a memory layer provided on a side surface of the plurality of the first conductive layers; and a second conductive layer that contacts the side surface of the plurality of the first conductive layers via the memory layer. A thickness of the first conductive layer disposed at the first position is larger than a thickness of the first conductive layer disposed at the second position. The control circuit is configured to apply a first voltage to a selected first conductive layer. The control circuit changes a value of the first voltage based on a position of the selected first conductive layer.
    Type: Application
    Filed: June 16, 2014
    Publication date: August 6, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi KANNO, Takayuki TSUKAMOTO, Takamasa OKAWA, Atsushi YOSHIDA
  • Patent number: 9099075
    Abstract: A standing wave attenuation device is installed in a cabin of a vehicle so as to reduce a standing wave caused by external noise such as road noise. The standing wave attenuation device provides a closed loop including a feedback comb filter with a feedback loop, a microphone, a speaker, and a delay element. The delay element adjusts the phase of the output signal of the feedback comb filter such that the time needed for one-time circulation of a signal through the feedback loop matches a half period of the standing wave. An original sound including the standing wave is picked up by the microphone and subjected to processing so that the speaker produces a sound wave with the inverse phase against the phase of a sound wave constituting the standing wave, so that the standing wave is canceled out by the sound wave emitted from the speaker.
    Type: Grant
    Filed: October 17, 2011
    Date of Patent: August 4, 2015
    Assignee: Yamaha Corporation
    Inventors: Satoshi Sekine, Rento Tanase, Keiichi Fukatsu, Shinichi Kato, Atsushi Yoshida
  • Patent number: 9097754
    Abstract: The present invention provides a method for manufacturing a magnetoresistive element having a high selection ratio of an insulating layer to a free layer. The method for manufacturing a magnetoresistive element includes the steps of preparing (left drawing, middle drawing) a substrate on which a free layer, a fixed layer disposed under a first magnetic layer, and a barrier layer that is an insulating layer disposed between the free layer and the fixed layer are formed and processing (right drawing) the free layer by plasma etching, in which an insulating layer configuring the barrier layer contains a Ta element or a Ti element.
    Type: Grant
    Filed: January 24, 2013
    Date of Patent: August 4, 2015
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Makoto Satake, Jun Hayakawa, Tsutomu Tetsuka, Takeshi Shimada, Naohiro Yamamoto, Atsushi Yoshida
  • Patent number: 9094231
    Abstract: The router is used to relay a packet to be transmitted from one node to another in an integrated circuit that has distributed buses according to a packet exchange method. The router includes: a plurality of buffers, each of which configured to store packets with information indicating their transmission node; a classifying section configured to classify the buffers that store the packets into a number of groups according to the transmission nodes of the packets; a selecting section configured to select at least one of the buffers of each group; and an output port configured to sequentially output the packets that are stored in the selected buffer.
    Type: Grant
    Filed: May 14, 2013
    Date of Patent: July 28, 2015
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Atsushi Yoshida, Tomoki Ishii, Takao Yamaguchi
  • Patent number: 9076369
    Abstract: An image modulation apparatus includes a device information obtaining unit to obtain device property information of a plurality of display devices respectively disposed at a plurality of image distribution destination apparatuses; a simulated image generator to generate a simulated image to be displayed on each of the display devices disposed at each of the image distribution destination apparatuses based on a distribution target image, to be transmitted to each of the image distribution destination apparatuses, and the device property information of each of the display devices obtained by the device information obtaining unit; and an image modulation unit to modulate the distribution target image based on a modulation instruction prepared for the plurality of the simulated images simulated by the simulated image generator.
    Type: Grant
    Filed: January 31, 2013
    Date of Patent: July 7, 2015
    Assignee: RICOH COMPANY, LTD.
    Inventor: Atsushi Yoshida
  • Patent number: 9075747
    Abstract: A bus controller is arranged on a plurality of network communication buses that connect together a plurality of bus masters, each sending out a packet, and at least one node, to which the packet is sent from each said bus master, in order to control the transmission route of a packet that is flowing through the plurality of communication buses. The bus controller includes: a route diagram manager configured to manage a plurality of transmission routes and their respective transmission statuses; a parameter generator configured to generate either a parameter that conforms to a predetermined probability distribution or a parameter that follows a predefined rule; a processor configured to select one of the plurality of transmission routes based on the respective transmission statuses of the transmission routes and the parameter; and a relay configured to perform relay processing on the packet that is flowing through the communication bus.
    Type: Grant
    Filed: November 19, 2012
    Date of Patent: July 7, 2015
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Tomoki Ishii, Takao Yamaguchi, Atsushi Yoshida
  • Patent number: D745723
    Type: Grant
    Filed: September 24, 2014
    Date of Patent: December 15, 2015
    Assignee: Mazda Motor Corporation
    Inventors: Atsushi Yoshida, Tamami Sato, Kota Akagawa, Keisuke Nakai
  • Patent number: D745724
    Type: Grant
    Filed: September 24, 2014
    Date of Patent: December 15, 2015
    Assignee: Mazda Motor Corporation
    Inventors: Atsushi Yoshida, Tamami Sato, Kota Akagawa, Kazuhiro Ito