Abstract: A bus system (100) for a semiconductor circuit transmits data on a networked bus between a first node and at least one second node via a relay device (250) arranged on the bus. The bus system (100) includes a first bus of a low delay and a second bus of a high delay. The first node generates a plurality of packets by attaching, to the data stored in a buffer (202), information specifying a priority of transmission. The relay device (250) converts a priority based on a priority conversion rule, which is determined based on a transmission delay of the high-delay bus, allocates a buffer of a destination relay device to which each packet is to be sent, based on the converted priority, and sends packets in a descending order. The relay device (250) stores packets in a buffer (252) based on the priority.

Abstract: A semiconductor memory device according to an embodiment described below comprises: first lines arranged in a first direction perpendicular to a main surface of a substrate and extending in a second direction crossing the first direction; second lines arranged in the second direction, extending in the first direction, and intersecting the first lines; memory cells disposed at intersections of the first lines and the second lines; and an interlayer insulating film provided between the second lines. The interlayer insulating film has an air gap extending continuously in the first direction so as to intersect at least some of the first lines aligned along the first direction. The interlayer insulating film also includes an insulating film positioned above the air gap and having a curved surface that protrudes toward a direction of the substrate.

Abstract: A bus control device (401a) includes a storage (408) that stores a transmission order of data pieces transmitted from a first node (402) to each second node (403); a sorter (413) that receives data pieces transferred from each second node toward the first node and refers to a predefined sorting rule to determine a sorting destination of each data piece; a buffer (409) that stores the sorted data pieces while classifying the sorted data pieces by the second node as a transmission source; and a connection controller (410) that refers to change permission/rejection information indicating whether or not an order is permitted to be changed while the data piece is transferred from each second node to the first node, and transmits data pieces, the order of which is not changed, from the buffer to the first node in the same order as the transmission order stored on the storage.

Abstract: The polishing apparatus has a polishing unit capable of polishing a peripheral portion of the substrate to form a right-angled cross section. The polishing apparatus includes: a substrate holder that holds and rotates the substrate; guide rollers that support a polishing tape; and a polishing head having a pressing member that presses an edge of the polishing tape against the peripheral portion of the substrate from above. The guide rollers are arranged such that the polishing tape extends parallel to a tangential direction of the substrate and a polishing surface of the polishing tape is parallel to a surface of the substrate. The substrate holder includes: a holding stage that holds the substrate; and a supporting stage that supports a lower surface of the peripheral portion of the substrate in its entirety. The supporting stage rotates in unison with the holding stage.

Abstract: A nonvolatile semiconductor memory device according to an embodiment includes a memory cell block that includes a memory cell array, the memory cell array including: a plurality of first lines; a plurality of second lines intersecting the plurality of first lines; and a memory cell that is provided at each of intersections of the plurality of first lines and the plurality of second lines and includes a variable resistance element, the memory cell array further including a protective resistance film that is provided respectively at each of the intersections of the plurality of first lines and the plurality of second lines and that is connected in series with the memory cell and ohmically contacts the memory cell, and the protective resistance film being configured from a material having a resistivity of 1˜100 ?·cm.

Abstract: A liquid ejecting apparatus includes a liquid ejecting head that ejects a plurality of kinds of photocurable type liquids, an irradiation unit that irradiates light that cures the liquids, a liquid receiving portion that is capable of receiving the liquids that are ejected from the liquid ejecting head, and a control unit that controls the ejection of the liquids from the liquid ejecting head. Among the plurality of kinds of liquids that are ejected, the control unit ejects a liquid that is cured with most ease when the light is irradiated before at least one different liquid other than the liquid in a case in which the plurality of kinds of liquids are ejected into the liquid receiving portion from the liquid ejecting head.

Abstract: Provided is a liquid supply device that includes a liquid storage portion that stores liquid containing sedimenting components which are sedimented in solvent, a liquid supply path that extends from the liquid storage portion to a liquid ejecting portion and through which the liquid to be supplied to the liquid ejecting portion can flow, a liquid flowing portion that is operated to cause the liquid to flow through at least part of the liquid supply path, a temperature detection portion that can detect the temperature of at least part of the liquid in the liquid supply path, and an operation control portion that controls an operation of the liquid flowing portion in correspondence with a detected temperature of the liquid, which is detected by the temperature detection portion, such that a flow condition of the liquid in the liquid supply path changes.

Abstract: Routers in a data transfer system relay data between the first node and each of the second nodes. A router includes a load value processing section and an aggregation decision section. The load value processing section obtains information about a load value of another router connected to a communications bus. The load value is a time delay caused by that another router and/or the throughput of that router. The aggregation decision section chooses one of the second nodes at which the data is to be received, and determines a transmission path between the second node chosen and the first node in accordance with information about the load value obtained from each router and information determined during a design process about the number of stages of routers from the first node through each second node and/or the length of data to be transferred.

Abstract: A semiconductor memory device according to an embodiment includes a memory cell array and a control circuit. The memory cell array includes first lines and second lines intersecting each other, a third line commonly connecting to the first lines, memory cells disposed at intersections of the first lines and the second lines, respectively. The control circuit is configured to execute a state determining operation detecting a voltage of the third line, and adjust a voltage applied to the first lines and the second lines during a resetting operation or a setting operation based on a result of the state determining operation. The resetting operation raises a resistance value of the variable resistance element. The setting operation lowers the resistance value of the variable resistance element.

Abstract: A plasma etching method performs plasma etching on a sample, which has laminated films containing a variable layer of a magnetic film, a barrier layer of an insulating material, and a fixed layer of a magnetic film, using a hard mask, which includes at least one of a Ta film and a TiN film. The plasma etching method includes a first step of etching the laminated films using N2 gas; and a second step of etching the laminated films after the first step using mixed gas of N2 gas and gas containing carbon elements.

Abstract: This semiconductor memory device comprises a memory cell array that includes: a plurality of first lines; a plurality of second lines intersecting the plurality of first lines; a plurality of memory cells each disposed at an intersection of the plurality of first lines and the plurality of second lines and including a variable resistance element; and a select transistor respectively connected to an end of the plurality of first lines. The select transistor includes a gate electrode, a gate insulating film, and a conductive layer. Moreover, one end of that conductive layer is connected to the end of the first line, and a non-linear resistance layer configured from a non-linear material is connected between the first line and the conductive layer.

Abstract: A nonvolatile semiconductor memory device according to an embodiment includes a control circuit configured to cause data to be stored in a memory cell by setting the memory cell to be included in one of resistance value distributions. The control circuit is configured to set a first resistance value distribution and a second resistance value distribution, the second resistance value distribution having a resistance value larger than that of the first resistance value distribution, and to set a second width to be larger than a first width, the second width being a width between a second upper limit value of the second resistance value distribution and a second lower limit value of the second resistance value distribution, and the first width being a width between a first upper limit value of the first resistance value distribution and a first lower limit value of the first resistance value distribution.

Abstract: The polishing apparatus has a polishing unit capable of polishing a peripheral portion of the substrate to form a right-angled cross section. The polishing apparatus includes: a substrate holder that holds and rotates the substrate; guide rollers that support a polishing tape; and a polishing head having a pressing member that presses an edge of the polishing tape against the peripheral portion of the substrate from above. The guide rollers are arranged such that the polishing tape extends parallel to a tangential direction of the substrate and a polishing surface of the polishing tape is parallel to a surface of the substrate. The substrate holder includes: a holding stage that holds the substrate; and a supporting stage that supports a lower surface of the peripheral portion of the substrate in its entirety. The supporting stage rotates in unison with the holding stage.

Abstract: A semiconductor test device and method for sequentially carrying out tests including an AC test, DC test, and thermal resistance test on a power semiconductor device are provided. The semiconductor test device includes a holding unit that positions the power semiconductor device. Test units each generate a test signal for the power semiconductor device and determine a test result generated in response to the test signal. A connection unit switches between the test units and selectively connects the test units electrically to electrodes of the power semiconductor device. The connection unit is controlled such that the test units are sequentially connected to the power semiconductor device to perform a plurality of the tests. The connection unit may include parallel plate electrodes in proximity to each other across an insulating sheet. The parallel plate electrodes may connect the power semiconductor device to positive and negative power sources of the test unit.

Abstract: An exemplary interface apparatus according to the present disclosure connects together an initiator and a packet exchange type bus network formed on the integrated circuit. In the bus network, if the initiator has submitted request data with a deadline time specified, the initiator receives, by the deadline time, response data to be issued by a node in response to the request data. The interface apparatus includes: a correcting circuit which corrects the deadline time of the request data according to the timing when the request data has been submitted, thereby generating corrected deadline time information; a header generator which generates a packet header that stores the corrected deadline time information; and a packetizing processor which generates a request packet based on the request data and the packet header.

Abstract: A solid-state imaging unit includes: a solid-state imaging device mounted on a substrate; a bonding wire which electrically connects a pad formed on the solid-state imaging device and a lead formed on the substrate; a frame member having a frame shape which surrounds side portions of the solid-state imaging device; and an optical member having optical transparency and mounted on the frame member so as to face an imaging surface of the solid-state imaging device, wherein the frame member has a leg portion which protrudes from an optical member side toward the imaging surface of the solid-state imaging device, and the frame member and the solid-state imaging device are integrally fixed to each other in a state where the leg portion comes into contact with an intermediate area which is located between an imaging area and a pad forming area on the imaging surface.

Abstract: According to an embodiment, a non-volatile memory device includes a first wiring extending in a first direction, a second wiring extending in a second direction orthogonal to the first direction. The device includes third wirings, and a first and a second memory. The third wirings extend in a third direction crossing the first direction and orthogonal to the second direction, and aligned in the second direction on both sides of the second wiring. The first memory is provided between one of third wiring pair and the second wiring, the pair of third wirings facing each other across the second wiring. The second memory is provided between another one of the third wiring pair and the second wiring. The second wiring has a block portion between a first portion in contact with the first memory and a second portion in contact with the second memory.

Abstract: In the bus system, bus interface apparatuses and routers are connected together through packet exchange buses which have been established on the integrated circuit. The bus interface apparatuses are respectively connected to transmission nodes which transmit data of mutually different numbers of bits in one cycle of operation of the bus system. Each of the bus interface apparatuses generates and transmits a packet based on data received from the transmission node connected and header information including size information indicating the number of bits with respect to the transmission node connected. The router analyzes the packet, gets the size information from the header information, determines how to allocate a space in the buffer for storage by reference to the size information gotten, and stores the received packet in the buffer.

Abstract: An image processing apparatus includes a frame memory, a motion vector detector, a screen edge detector and an interpolation frame generator. The frame memory frame-delays an input signal and outputs the input signal as a delayed input signal. The motion vector detector detects a motion vector between frames based on the input signal and the delayed input signal. The screen edge detector detects a pixel corresponding to a screen edge in the input signal. The interpolation frame generator generates an interpolation frame from the input signal and delayed input signal based on the motion vector and the pixel corresponding to the screen edge. The interpolation frame generator generates the interpolation frame using the pixel corresponding to the screen edge or the pixel inside relative to the pixel corresponding to the screen edge when the motion vector points a pixel outside relative to the pixel corresponding to the screen edge.

Abstract: An exemplary interface apparatus includes: a header generator which receives, in a first order, a plurality of request headers extracted from a plurality of request packets, generates response headers associated with the request headers, and then stores the response headers so that the response headers are read in the first order; and a header order controller which controls the header generator so that if the plurality of request data have been transmitted to the memory in a second order, the respective response headers are read in the second order.