Patents by Inventor Atsushi Yoshimura

Atsushi Yoshimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220298736
    Abstract: A work machine includes: a drive rotation speed detector configured to detect a signal indicating a rotation of a drive source; a work rotation speed detector configured to detect a signal indicating rotation of a work rotation shaft; and a control device configured to, on the basis of comparison between signals acquired from the drive rotation speed detector and the work rotation speed detector, stop the drive source in a case where there is a rotation speed difference between a driven shaft in a rotating state due to power transmission from the drive source and the work rotation shaft. The work rotation speed detector includes: a detection target member configured to rotate together with the work rotation shaft; and a sensor mounting member configured to hold a detection sensor configured to detect rotation of the detection target member.
    Type: Application
    Filed: March 15, 2022
    Publication date: September 22, 2022
    Inventors: Yoshitaka OTA, Hajime YOSHIMURA, Yuta KIMURA, Atsushi MOROI
  • Patent number: 11415589
    Abstract: Provided is an automatic analyzer provided with a liquid level sensing function in which liquid levels in sample containers having various heights can be precisely detected using ultrasonic waves. This device is provided with: a conveyance rack for conveying a sample container which contains a sample and is loaded thereon; a fixed ultrasonic distance sensor for measuring the liquid level position in the sample container loaded on the conveyance rack; sound wave guides for suppressing diffusion of sound waves transmitted from the ultrasonic distance sensor, the sound wave guides being disposed between the sample container and the ultrasonic distance sensor; and a sound wave guide control unit for adjusting the length or switching the length of the sound wave guides in accordance with the distance between the ultrasonic distance sensor and the sample container.
    Type: Grant
    Filed: December 26, 2018
    Date of Patent: August 16, 2022
    Assignee: Hitachi High-Tech Corporation
    Inventors: Yosuke Horie, Yasuhiro Yoshimura, Atsushi Kazama, Masato Ishizawa, Satoru Yamamoto
  • Patent number: 11373416
    Abstract: An image processing device includes: a detection unit which detects a target object based on edge information acquired from image data; and a judging unit which judges whether a certain region in the image data is an improper region that is not suitable for detection of the target object based on an edge pattern of edge information in the certain region and a feature pattern indicating a feature of the target object, and the detection unit detects the target object excluding a region that has been judged to be the improper region by the judging unit.
    Type: Grant
    Filed: September 18, 2019
    Date of Patent: June 28, 2022
    Assignee: DENSO TEN Limited
    Inventors: Yasutaka Okada, Hiroaki Sano, Tetsuo Yamamoto, Atsushi Yoshihara, Jun Kanetake, Ryo Yoshimura, Tomoki Shidori
  • Publication number: 20150214193
    Abstract: A stacked electronic component comprises a first electronic component adhered on a substrate via a first adhesive layer, and a second electronic component adhered by using a second adhesive layer thereon. The second adhesive layer has a two-layer structure formed by a same material and having different modulus of elasticity. The second adhesive layer of the two-layer structure has a first layer disposed at the first electronic component side and a second layer disposed at the second electronic component side. The first layer softens or melts at an adhesive temperature. The second layer maintains a layered shape at the adhesive temperature. According to the stacked electronic component, occurrences of an insulation failure and a short circuiting are prevented, and in addition, a peeling failure between the electronic components, an increase of a manufacturing cost, and so on, can be suppressed.
    Type: Application
    Filed: April 2, 2015
    Publication date: July 30, 2015
    Inventors: Atsushi Yoshimura, Naoyuki Komuta, Hideo Numata
  • Patent number: 9024424
    Abstract: A stacked electronic component comprises a first electronic component adhered on a substrate via a first adhesive layer, and a second electronic component adhered by using a second adhesive layer thereon. The second adhesive layer has a two-layer structure formed by a same material and having different modulus of elasticity. The second adhesive layer of the two-layer structure has a first layer disposed at the first electronic component side and a second layer disposed at the second electronic component side. The first layer softens or melts at an adhesive temperature. The second layer maintains a layered shape at the adhesive temperature. According to the stacked electronic component, occurrences of an insulation failure and a short circuiting are prevented, and in addition, a peeling failure between the electronic components, an increase of a manufacturing cost, and so on, can be suppressed.
    Type: Grant
    Filed: August 16, 2012
    Date of Patent: May 5, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Atsushi Yoshimura, Naoyuki Komuta, Hideo Numata
  • Patent number: 9006029
    Abstract: According to one embodiment, a method is disclosed for manufacturing a semiconductor device including a semiconductor chip having electrode pads formed on a first major surface and a bonding layer provided on a second major surface, and a substrate having the semiconductor chip mounted on the substrate. The manufacturing method can include applying a fillet-forming material to a portion contacting an outer edge of the second major surface of the semiconductor chip on a front face of the substrate. The method can include bonding the second major surface of the semiconductor chip to the substrate via the bonding layer.
    Type: Grant
    Filed: March 21, 2011
    Date of Patent: April 14, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yukio Katamura, Yasuo Tane, Atsushi Yoshimura, Fumihiro Iwami
  • Patent number: 8796076
    Abstract: After formation of an opening by exposing and development of the photosensitive surface protection film and adhesive layer which is formed on the circuit side of the semiconductor wafer, the semiconductor chips having a photosensitive surface protection film and adhesive layer thereon is fabricated by cutting individual chips from the semiconductor wafer. After the second semiconductor chip is placed over the first semiconductor chip up by the suction collet, the second semiconductor chip is bonded with the first semiconductor chip by the first surface protection film and adhesive layer. The suction side of the suction collet has lower adhesion to the second semiconductor chip than that between the now bonded semiconductor chips.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: August 5, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Atsushi Yoshimura, Shoko Omizo
  • Patent number: 8783207
    Abstract: An electric wire for connecting a rotating base plate 18 and a main substrate 10 is composed of an FPC 13. The FPC is connected to the main substrate 10 in a manner that a width direction of the FPC 13 is perpendicular to the main substrate 10. A protecting member 14 is provided on the main substrate 10 for surrounding a moving range of the FPC 13 on the main substrate 10 associated with a rotation of a meter pointer 12.
    Type: Grant
    Filed: March 17, 2011
    Date of Patent: July 22, 2014
    Assignee: Yazaki Corporation
    Inventors: Haruyoshi Ono, Atsushi Yoshimura
  • Patent number: 8717263
    Abstract: The present invention is to provide an LCD unit, an LCD apparatus, and a method of setting a drive voltage of the LCD unit with a simple operation. The LCD unit includes a label pasted on a place of the LCD unit, wherein the label includes an information code, which is information-coded from a data of a drive voltage for achieving the best contrast in optical characteristics of the LCD unit. The best drive voltage to drive the LCD unit with the best contrast is thereby easily set.
    Type: Grant
    Filed: April 6, 2007
    Date of Patent: May 6, 2014
    Assignee: Yazaki Corporation
    Inventor: Atsushi Yoshimura
  • Patent number: 8691628
    Abstract: According to one embodiment, a method of manufacturing a semiconductor device, a bonding layer is formed on a first surface of a chip region of a semiconductor wafer. Semiconductor chips are singulated along a dicing region. The semiconductor chips are stacked stepwise via the bonding layer. In formation of the bonding layer of the semiconductor chip, in at least a part of a first region of the first surface not in contact with the other semiconductor chip in a stacked state, a projected section where the bonding layer is formed thicker than the bonding layer in a second region that is in contact with the other semiconductor chip is provided.
    Type: Grant
    Filed: September 6, 2011
    Date of Patent: April 8, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasuo Tane, Yukio Katamura, Atsushi Yoshimura, Fumihiro Iwami
  • Patent number: 8659137
    Abstract: In an embodiment, a first semiconductor wafer having plural first chip areas sectioned by first dicing grooves, and first photosensitive surface protection and adhesive layers provided at each of circuit surfaces of the plural first chip areas is prepared. A second semiconductor wafer having plural second chip areas sectioned by second dicing grooves, and second photosensitive surface protection and adhesive layers provided at each of circuit surfaces of the plural second chip areas is stacked with the first semiconductor wafer via the second photosensitive surface protection and adhesive layers to form plural chip stacked bodies of the first chip areas and the second chip areas.
    Type: Grant
    Filed: August 20, 2013
    Date of Patent: February 25, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shoko Omizo, Atsushi Yoshimura, Fumihiro Iwami
  • Patent number: 8633602
    Abstract: According to one embodiment, a manufacturing method of a semiconductor device is disclosed. The method includes: stacking and adhering a second semiconductor chip on a first semiconductor chip via an adhesive layer; adjusting at least one of an elasticity modulus of the adhesive layer, a sink amount of the adhesive layer, a thickness of a protective film at a surface of the first chip, and an elasticity modulus of the protective film such that “y” in a following formula is 70 or less; and sealing the chips by a molding resin with filler particles. y=74.7?82.7a1+273.2a2?9882a3+65.8a4 a1: a logarithm of the modulus of elasticity [MPa] of the adhesive layer a2: the sink amount [mm] of the adhesive layer a3: the thickness [mm] of the protective film a4: a logarithm of the modulus of elasticity [MPa] of the protective film.
    Type: Grant
    Filed: March 15, 2012
    Date of Patent: January 21, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Nobuhito Suzuya, Atsushi Yoshimura, Hideko Mukaida
  • Patent number: 8629041
    Abstract: According to one embodiment, a method is disclosed for manufacturing a semiconductor device. The method can include die bonding to bond a semiconductor element to a first position of a base member via a bonding layer provided on one surface of the semiconductor element. The method can include wire bonding to connect a terminal formed on the semiconductor element to a terminal formed on the base member by a bonding wire. In addition, the method can include sealing to seal the semiconductor element and the bonding wire. Viscosity of the bonding layer in the bonding is controlled not to exceed the viscosity of the bonding layer in the sealing.
    Type: Grant
    Filed: April 21, 2011
    Date of Patent: January 14, 2014
    Assignees: Kabushiki Kaisha Toshiba, KYOCERA Chemical Corporation
    Inventors: Yasuo Tane, Yukio Katamura, Atsushi Yoshimura, Fumihiro Iwami, Kazuyoshi Sakurai
  • Publication number: 20130334709
    Abstract: In an embodiment, a first semiconductor wafer having plural first chip areas sectioned by first dicing grooves, and first photosensitive surface protection and adhesive layers provided at each of circuit surfaces of the plural first chip areas is prepared. A second semiconductor wafer having plural second chip areas sectioned by second dicing grooves, and second photosensitive surface protection and adhesive layers provided at each of circuit surfaces of the plural second chip areas is stacked with the first semiconductor wafer via the second photosensitive surface protection and adhesive layers to form plural chip stacked bodies of the first chip areas and the second chip areas.
    Type: Application
    Filed: August 20, 2013
    Publication date: December 19, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Shoko OMIZO, Atsushi YOSHIMURA, Fumihiro IWAMI
  • Patent number: 8557635
    Abstract: In an embodiment, a first semiconductor wafer having plural first chip areas sectioned by first dicing grooves, and first photosensitive surface protection and adhesive layers provided at each of circuit surfaces of the plural first chip areas is prepared. A second semiconductor wafer having plural second chip areas sectioned by second dicing grooves, and second photosensitive surface protection and adhesive layers provided at each of circuit surfaces of the plural second chip areas is stacked with the first semiconductor wafer via the second photosensitive surface protection and adhesive layers to form plural chip stacked bodies of the first chip areas and the second chip areas.
    Type: Grant
    Filed: February 23, 2012
    Date of Patent: October 15, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shoko Omizo, Atsushi Yoshimura, Fumihiro Iwami
  • Patent number: 8513088
    Abstract: In one embodiment, an adhesive layer is formed by applying a liquid adhesive to a semiconductor wafer whose wafer shape is maintained by a surface protective film attached to a first surface. A supporting sheet having a tacky layer is attached to a second surface of the semiconductor wafer. After the surface protective film is peeled, the supporting sheet is expanded to cleave the adhesive layer including the adhesive filled into the dicing grooves. The first surface of the semiconductor wafer is cleaned while an expansion state of the supporting sheet is maintained. Tack strength of portions corresponding to the dicing grooves of the tacky layer is selectively reduced before cleaning.
    Type: Grant
    Filed: September 15, 2011
    Date of Patent: August 20, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Atsushi Yoshimura, Fumihiro Iwami
  • Patent number: 8506102
    Abstract: The present invention is to provide a lightweight indicator, which suppresses a backlash between a light guide portion and a light source, and a display apparatus including the indicator. The pointer includes a base portion disposed rearward of a display device and fixed to a rotation axle of a motor disposed rearward of the base portion, and extending radially from the rotation axle; a board fixed on a front face of the base portion; a light source mounted on a rear face of the board for radially outwardly emitting a light; and a light guide portion.
    Type: Grant
    Filed: March 28, 2011
    Date of Patent: August 13, 2013
    Assignee: Yazaki Corporation
    Inventors: Haruyoshi Ono, Atsushi Yoshimura
  • Publication number: 20130062782
    Abstract: After formation of an opening by exposing and development of the photosensitive surface protection film and adhesive layer which is formed on the circuit side of the semiconductor wafer, the semiconductor chips having a photosensitive surface protection film and adhesive layer thereon is fabricated by cutting individual chips from the semiconductor wafer. After the second semiconductor chip is placed over the first semiconductor chip up by the suction collet, the second semiconductor chip is bonded with the first semiconductor chip by the first surface protection film and adhesive layer. The suction side of the suction collet has lower adhesion to the second semiconductor chip than that between the now bonded semiconductor chips.
    Type: Application
    Filed: August 30, 2012
    Publication date: March 14, 2013
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Atsushi Yoshimura, Shoko Omizo
  • Patent number: 8381706
    Abstract: A part of a ceiling wall (14) of a head cover (10) that opposes an intake collection chamber (51) is constituted by a concave ceiling wall (20) that defines a concave surface facing the intake collection chamber (51), and the concave ceiling wall (20) is formed with a recessed groove (21) that further recedes toward an inner side of the head cover.
    Type: Grant
    Filed: April 30, 2008
    Date of Patent: February 26, 2013
    Assignees: Honda Motor Co., Ltd., Mahle Filter Systems Japan Corporation
    Inventors: Yoshihiro Akiyama, Atsushi Yoshimura, Isao Emi
  • Publication number: 20120326339
    Abstract: According to one embodiment, a manufacturing method of a semiconductor device is disclosed. The method includes: stacking and adhering a second semiconductor chip on a first semiconductor chip via an adhesive layer; adjusting at least one of an elasticity modulus of the adhesive layer, a sink amount of the adhesive layer, a thickness of a protective film at a surface of the first chip, and an elasticity modulus of the protective film such that “y” in a following formula is 70 or less; and sealing the chips by a molding resin with filler particles. y=74.7?82.7a1+273.2a2?9882a3+65.
    Type: Application
    Filed: March 15, 2012
    Publication date: December 27, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Nobuhito SUZUYA, Atsushi Yoshimura, Hideko Mukaida