Patents by Inventor Atsushi Yoshimura
Atsushi Yoshimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20120326339Abstract: According to one embodiment, a manufacturing method of a semiconductor device is disclosed. The method includes: stacking and adhering a second semiconductor chip on a first semiconductor chip via an adhesive layer; adjusting at least one of an elasticity modulus of the adhesive layer, a sink amount of the adhesive layer, a thickness of a protective film at a surface of the first chip, and an elasticity modulus of the protective film such that “y” in a following formula is 70 or less; and sealing the chips by a molding resin with filler particles. y=74.7?82.7a1+273.2a2?9882a3+65.Type: ApplicationFiled: March 15, 2012Publication date: December 27, 2012Applicant: Kabushiki Kaisha ToshibaInventors: Nobuhito SUZUYA, Atsushi Yoshimura, Hideko Mukaida
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Publication number: 20120318431Abstract: In one embodiment, a method for manufacturing a semiconductor device is disclosed. The method can include, upon attaching a bonding material containing a resin and a solvent to a second surface opposed to a first surface including a circuit pattern of a wafer, heating the bonding material to evaporate the solvent and decreasing vapor pressure of the solvent in an atmosphere faced with the bonding material and heating the attached bonding material to form a bonding layer.Type: ApplicationFiled: August 30, 2012Publication date: December 20, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yukio Katamura, Yasuo Tane, Atsushi Yoshimura, Fumihiro Iwami
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Publication number: 20120306103Abstract: A stacked electronic component comprises a first electronic component adhered on a substrate via a first adhesive layer, and a second electronic component adhered by using a second adhesive layer thereon. The second adhesive layer has a two-layer structure formed by a same material and having different modulus of elasticity. The second adhesive layer of the two-layer structure has a first layer disposed at the first electronic component side and a second layer disposed at the second electronic component side. The first layer softens or melts at an adhesive temperature. The second layer maintains a layered shape at the adhesive temperature. According to the stacked electronic component, occurrences of an insulation failure and a short circuiting are prevented, and in addition, a peeling failure between the electronic components, an increase of a manufacturing cost, and so on, can be suppressed.Type: ApplicationFiled: August 16, 2012Publication date: December 6, 2012Applicant: Kabushiki Kaisha ToshibaInventors: Atsushi Yoshimura, Naoyuki Komuta, Hideo Numata
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Patent number: 8302889Abstract: A fuel injection valve has a valve body for opening and closing a valve seat, and receives an operation signal from a control unit to operate the valve body so that fuel is injected from a plurality of injection holes formed in an injection hole plate welded through a welded portion to a downstream side of the valve seat while passing through a gap between the valve body and the valve seat. The injection hole plate is formed at its central portion with a convex portion which is substantially axisymmetric with respect to a valve seat axis and which has a circular-arc shaped cross section, and the welded portion is also substantially axisymmetric with respect to the valve seat axis.Type: GrantFiled: July 6, 2011Date of Patent: November 6, 2012Assignee: Mitsubishi Electric CorporationInventors: Naoya Hashii, Keishi Nakano, Tsuyoshi Munezane, Atsushi Yoshimura, Manabu Miyaki
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Patent number: 8276537Abstract: In one embodiment, a method for manufacturing a semiconductor device is disclosed. The method can include, upon attaching a bonding material containing a resin and a solvent to a second surface opposed to a first surface including a circuit pattern of a wafer, heating the bonding material to evaporate the solvent and decreasing vapor pressure of the solvent in an atmosphere faced with the bonding material and heating the attached bonding material to form a bonding layer.Type: GrantFiled: January 18, 2011Date of Patent: October 2, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Yukio Katamura, Yasuo Tane, Atsushi Yoshimura, Fumihiro Iwami
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Patent number: 8268673Abstract: A stacked electronic component comprises a first electronic component adhered on a substrate via a first adhesive layer, and a second electronic component adhered by using a second adhesive layer thereon. The second adhesive layer has a two-layer structure formed by a same material and having different modulus of elasticity. The second adhesive layer of the two-layer structure has a first layer disposed at the first electronic component side and a second layer disposed at the second electronic component side. The first layer softens or melts at an adhesive temperature. The second layer maintains a layered shape at the adhesive temperature. According to the stacked electronic component, occurrences of an insulation failure and a short circuiting are prevented, and in addition, a peeling failure between the electronic components, an increase of a manufacturing cost, and so on, can be suppressed.Type: GrantFiled: July 20, 2011Date of Patent: September 18, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Atsushi Yoshimura, Naoyuki Komuta, Hideo Numata
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Publication number: 20120223441Abstract: In an embodiment, a first semiconductor wafer having plural first chip areas sectioned by first dicing grooves, and first photosensitive surface protection and adhesive layers provided at each of circuit surfaces of the plural first chip areas is prepared. A second semiconductor wafer having plural second chip areas sectioned by second dicing grooves, and second photosensitive surface protection and adhesive layers provided at each of circuit surfaces of the plural second chip areas is stacked with the first semiconductor wafer via the second photosensitive surface protection and adhesive layers to form plural chip stacked bodies of the first chip areas and the second chip areas.Type: ApplicationFiled: February 23, 2012Publication date: September 6, 2012Applicant: Kabushiki Kaisha ToshibaInventors: Shoko OMIZO, Atsushi Yoshimura, Fumihiro Iwami
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Patent number: 8240281Abstract: A height of an upper end of an oil outflow prevention wall 25 with respect to the fastening plane 15 is greater in a lower side of the inclination of the fastening plane 15 than in a higher side of the inclination of the fastening plane 15.Type: GrantFiled: April 30, 2008Date of Patent: August 14, 2012Assignee: Honda Motor Co., LtdInventors: Yoshihiro Akiyama, Atsushi Yoshimura
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Publication number: 20120199993Abstract: In one embodiment, an adhesive layer is formed by applying a liquid adhesive to a semiconductor wafer whose wafer shape is maintained by a surface protective film attached to a first surface. A supporting sheet having a tacky layer is attached to a second surface of the semiconductor wafer. After the surface protective film is peeled, the supporting sheet is expanded to cleave the adhesive layer including the adhesive filled into the dicing grooves. The first surface of the semiconductor wafer is cleaned while an expansion state of the supporting sheet is maintained. Tack strength of portions corresponding to the dicing grooves of the tacky layer is selectively reduced before cleaning.Type: ApplicationFiled: September 15, 2011Publication date: August 9, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Atsushi YOSHIMURA, Fumihiro IWAMI
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Patent number: 8227296Abstract: A stacked semiconductor device includes a first semiconductor element bonded on a circuit base. The first semiconductor element is electrically connected to a connection part of the circuit base via a first bonding wire. A second semiconductor element is bonded on the first semiconductor element via a second adhesive layer with a thickness of 50 ?m or more. The second adhesive layer is formed of an insulating resin layer whose glass transition temperature is 135° C. or higher and whose coefficient of linear expansion at a temperature equal to or lower than the glass transition temperature is 100 ppm or less.Type: GrantFiled: June 29, 2011Date of Patent: July 24, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Atsushi Yoshimura, Hideko Mukaida
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Publication number: 20120149151Abstract: According to one embodiment, a method of manufacturing a semiconductor device, a bonding layer is formed on a first surface of a chip region of a semiconductor wafer. Semiconductor chips are singulated along a dicing region. The semiconductor chips are stacked stepwise via the bonding layer. In formation of the bonding layer of the semiconductor chip, in at least a part of a first region of the first surface not in contact with the other semiconductor chip in a stacked state, a projected section where the bonding layer is formed thicker than the bonding layer in a second region that is in contact with the other semiconductor chip is provided.Type: ApplicationFiled: September 6, 2011Publication date: June 14, 2012Applicant: Kabushiki Kaisha ToshibaInventors: Yasuo TANE, Yukio KATAMURA, Atsushi YOSHIMURA, Fumihiro IWAMI
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Publication number: 20120052627Abstract: According to one embodiment, a method is disclosed for manufacturing a semiconductor device including a semiconductor chip having electrode pads formed on a first major surface and a bonding layer provided on a second major surface, and a substrate having the semiconductor chip mounted on the substrate. The manufacturing method can include applying a fillet-forming material to a portion contacting an outer edge of the second major surface of the semiconductor chip on a front face of the substrate. The method can include bonding the second major surface of the semiconductor chip to the substrate via the bonding layer.Type: ApplicationFiled: March 21, 2011Publication date: March 1, 2012Applicant: Kabushiki Kaisha ToshibaInventors: Yukio KATAMURA, Yasuo Tane, Atsushi Yoshimura, Fumihiro Iwami
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Publication number: 20110281396Abstract: A stacked electronic component comprises a first electronic component adhered on a substrate via a first adhesive layer, and a second electronic component adhered by using a second adhesive layer thereon. The second adhesive layer has a two-layer structure formed by a same material and having different modulus of elasticity. The second adhesive layer of the two-layer structure has a first layer disposed at the first electronic component side and a second layer disposed at the second electronic component side. The first layer softens or melts at an adhesive temperature. The second layer maintains a layered shape at the adhesive temperature. According to the stacked electronic component, occurrences of an insulation failure and a short circuiting are prevented, and in addition, a peeling failure between the electronic components, an increase of a manufacturing cost, and so on, can be suppressed.Type: ApplicationFiled: July 20, 2011Publication date: November 17, 2011Applicant: Kabushiki Kaisha ToshibaInventors: Atsushi Yoshimura, Naoyuki Komuta, Hideo Numata
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Publication number: 20110267796Abstract: According to one embodiment, a semiconductor device includes a matrix and a semiconductor element bonded to the matrix via a bonding layer. The bonding layer includes a first layer and a second layer having a viscosity lower than a viscosity of the first layer at a bonding temperature. The first layer has a portion in which an end of the first layer is set further back to an inside than an end of the semiconductor element. At least a part of the portion set back to the inside is filled with a part of the second layer extruded from a periphery of the first layer to an outside.Type: ApplicationFiled: March 18, 2011Publication date: November 3, 2011Inventors: Atsushi YOSHIMURA, Yasuo Tane
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Publication number: 20110263097Abstract: According to one embodiment, a method for manufacturing semiconductor device can include forming a groove with a depth shallower than a thickness of a wafer. The method can include attaching a surface protection tape via a first bonding layer provided in the surface protection tape. The method can include grinding a surface of the wafer to divide the wafer into a plurality of semiconductor elements. The method can include forming an element bonding layer by attaching a bonding agent and turning the attached bonding agent into a B-stage state. The method can include attaching a dicing tape via a second bonding layer provided in the dicing tape. The method can include irradiating the first bonding layer with a first active energy ray. The method can include removing the surface protection tape. The method can include irradiating the second bonding layer with a second active energy ray.Type: ApplicationFiled: March 22, 2011Publication date: October 27, 2011Inventors: Atsushi YOSHIMURA, Yasuo TANE, Yukio KATAMURA, Fumihiro IWAMI
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Publication number: 20110263131Abstract: In one embodiment, a method for manufacturing a semiconductor device is disclosed. The method can include, upon attaching a bonding material containing a resin and a solvent to a second surface opposed to a first surface including a circuit pattern of a wafer, heating the bonding material to evaporate the solvent and decreasing vapor pressure of the solvent in an atmosphere faced with the bonding material and heating the attached bonding material to form a bonding layer.Type: ApplicationFiled: January 18, 2011Publication date: October 27, 2011Applicant: Kabushiki Kaisha ToshibaInventors: Yukio KATAMURA, Yasuo Tane, Atsushi Yoshimura, Fumihiro Iwami
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Publication number: 20110260084Abstract: A fuel injection valve has a valve body for opening and closing a valve seat, and receives an operation signal from a control unit to operate the valve body so that fuel is injected from a plurality of injection holes formed in an injection hole plate welded through a welded portion to a downstream side of the valve seat while passing through a gap between the valve body and the valve seat. The injection hole plate is formed at its central portion with a convex portion which is substantially axisymmetric with respect to a valve seat axis and which has a circular-arc shaped cross section, and the welded portion is also substantially axisymmetric with respect to the valve seat axis.Type: ApplicationFiled: July 6, 2011Publication date: October 27, 2011Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Naoya HASHII, Keishi NAKANO, Tsuyoshi MUNEZANE, Atsushi YOSHIMURA, Manabu MIYAKI
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Publication number: 20110263076Abstract: A stacked semiconductor device includes a first semiconductor element bonded on a circuit base. The first semiconductor element is electrically connected to a connection part of the circuit base via a first bonding wire. A second semiconductor element is bonded on the first semiconductor element via a second adhesive layer with a thickness of 50 ?m or more. The second adhesive layer is formed of an insulating resin layer whose glass transition temperature is 135° C. or higher and whose coefficient of linear expansion at a temperature equal to or lower than the glass transition temperature is 100 ppm or less.Type: ApplicationFiled: June 29, 2011Publication date: October 27, 2011Applicant: Kabushiki Kaisha ToshibaInventors: Atsushi Yoshimura, Hideko Mukaida
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Publication number: 20110263078Abstract: According to one embodiment, a method is disclosed for manufacturing a semiconductor device. The method can include die bonding to bond a semiconductor element to a first position of a base member via a bonding layer provided on one surface of the semiconductor element. The method can include wire bonding to connect a terminal formed on the semiconductor element to a terminal formed on the base member by a bonding wire. In addition, the method can include sealing to seal the semiconductor element and the bonding wire. Viscosity of the bonding layer in the bonding is controlled not to exceed the viscosity of the bonding layer in the sealing.Type: ApplicationFiled: April 21, 2011Publication date: October 27, 2011Applicants: KYOCERA CHEMICAL CORPORATION, Kabushiki Kaisha ToshibaInventors: Yasuo TANE, Yukio Katamura, Atsushi Yoshimura, Fumihiro Iwami, Kazuyoshi Sakurai
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Patent number: 8039364Abstract: An adhesive layer of which thickness is over 25 ?m and a dicing tape are laminated on a rear surface of a semiconductor wafer. The semiconductor wafer is cut together with a part of the adhesive layer by using a first blade of which cutting depth reaches the adhesive layer. The adhesive layer is cut together with a part of the dicing tape by using a second blade of which cutting depth reaches the dicing tape and of which width is narrower than the first blade. A semiconductor element sectioned by cutting the semiconductor wafer with the adhesive layer is picked up from the dicing tape, and is adhered on another semiconductor element or a circuit board.Type: GrantFiled: April 23, 2010Date of Patent: October 18, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Atsushi Yoshimura, Tadanobu Okubo, Shigetaka Onishi