Patents by Inventor Atsushi Yoshimura

Atsushi Yoshimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110242790
    Abstract: The present invention is to provide a lightweight indicator, which suppresses a backlash between a light guide portion and a light source, and a display apparatus including the indicator. The pointer includes a base portion disposed rearward of a display device and fixed to a rotation axle of a motor disposed rearward of the base portion, and extending radially from the rotation axle; a board fixed on a front face of the base portion; a light source mounted on a rear face of the board for radially outwardly emitting a light; and a light guide portion.
    Type: Application
    Filed: March 28, 2011
    Publication date: October 6, 2011
    Applicant: Yazaki Corporation
    Inventors: Haruyoshi Ono, Atsushi Yoshimura
  • Publication number: 20110232563
    Abstract: An electric wire for connecting a rotating base plate 18 and a main substrate 10 is composed of an FPC 13. The FPC is connected to the main substrate 10 in a manner that a width direction of the FPC 13 is perpendicular to the main substrate 10. A protecting member 14 is provided on the main substrate 10 for surrounding a moving range of the FPC 13 on the main substrate 10 associated with a rotation of a meter pointer 12.
    Type: Application
    Filed: March 17, 2011
    Publication date: September 29, 2011
    Applicant: Yazaki Corporation
    Inventors: Haruyoshi Ono, Atsushi Yoshimura
  • Patent number: 8008763
    Abstract: A stacked electronic component comprises a first electronic component adhered on a substrate via a first adhesive layer, and a second electronic component adhered by using a second adhesive layer thereon. The second adhesive layer has a two-layer structure formed by a same material and having different modulus of elasticity. The second adhesive layer of the two-layer structure has a first layer disposed at the first electronic component side and a second layer disposed at the second electronic component side. The first layer softens or melts at an adhesive temperature. The second layer maintains a layered shape at the adhesive temperature. According to the stacked electronic component, occurrences of an insulation failure and a short circuiting are prevented, and in addition, a peeling failure between the electronic components, an increase of a manufacturing cost, and so on, can be suppressed.
    Type: Grant
    Filed: January 25, 2008
    Date of Patent: August 30, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Atsushi Yoshimura, Naoyuki Komuta, Hideo Numata
  • Patent number: 8002207
    Abstract: This invention serves to suppress the deterioration of oil tightness of a valve after welding without any change in the direction of fuel injection even with deformation of a convex portion after welding of an injection opening plate to a valve seat, as well as without any variation in the direction of fuel injection due to welding variation.
    Type: Grant
    Filed: March 27, 2007
    Date of Patent: August 23, 2011
    Assignee: Mitsubishi Electric Corporation
    Inventors: Naoya Hashii, Keishi Nakano, Tsuyoshi Munezane, Atsushi Yoshimura, Manabu Miyaki
  • Patent number: 7994620
    Abstract: A stacked semiconductor device includes a first semiconductor element bonded on a circuit base. The first semiconductor element is electrically connected to a connection part of the circuit base via a first bonding wire. A second semiconductor element is bonded on the first semiconductor element via a second adhesive layer with a thickness of 50 ?m or more. The second adhesive layer is formed of an insulating resin layer whose glass transition temperature is 135° C. or higher and whose coefficient of linear expansion at a temperature equal to or lower than the glass transition temperature is 100 ppm or less.
    Type: Grant
    Filed: March 15, 2007
    Date of Patent: August 9, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Atsushi Yoshimura, Hideko Mukaida
  • Patent number: 7955896
    Abstract: A first semiconductor element is mounted on a wiring board. A second semiconductor element having a portion projecting to an outer side of an outer periphery of the first semiconductor element is disposed on the first semiconductor element via an adhesive. The adhesive has a viscosity (?0.5 rpm) at a low-rotation speed in a range from 10 Pa·s to 150 Pa·s and a thixotropic ratio of 2 or higher expressed by a ratio (?0.5 rpm/?5 rpm) of the viscosity (?0.5 rpm) at the low-rotation speed to a viscosity (?5 rpm) at a high-rotation speed. The second semiconductor element is bonded onto the first semiconductor element while the adhesive is filled in a hollow portion between the projecting portion of the second semiconductor element and the wiring board.
    Type: Grant
    Filed: July 24, 2009
    Date of Patent: June 7, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Atsushi Yoshimura, Shoko Omizo
  • Publication number: 20110079629
    Abstract: A method of manufacturing a stacked-type semiconductor device, comprises: arranging a plurality of stacked chips obtained by stacking semiconductor chips on a plurality of stages on a support substrate; connecting a semiconductor chip of each stage in each stacked chip and the support substrate by wire while performing heating in units of stacked chips; performing plastic molding of each stacked chip; and separating the stacked chips from each other. An apparatus for manufacturing a stacked-type semiconductor device, comprising divided heater blocks formed under a support substrate on which a plurality of stacked chips obtained by stacking a plurality of semiconductor chips are arranged, the divided heater blocks being formed with respect to the stacked chips, and a heating device to selectively transmit heat to a stacked chip subjected to a wire bonding.
    Type: Application
    Filed: December 8, 2010
    Publication date: April 7, 2011
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Atsushi Yoshimura
  • Publication number: 20110061626
    Abstract: A height of an upper end of an oil outflow prevention wall 25 with respect to the fastening plane 15 is greater in a lower side of the inclination of the fastening plane 15 than in a higher side of the inclination of the fastening plane 15.
    Type: Application
    Filed: August 19, 2009
    Publication date: March 17, 2011
    Applicant: HONDA MOTOR CO., LTD
    Inventors: Yoshihiro AKIYAMA, Atsushi YOSHIMURA
  • Patent number: 7900533
    Abstract: A controller of an automatic transmission can be set to be in a first control mode and a second control mode for controlling a transmission gear ratio of the automatic transmission. The controller in the second control mode automatically changes the transmission gear ratio. The controller obtains an index value and upper limit speed of rotation speed of a transmission output shaft. The controller in the first control mode allows the transmission gear ratio to be changed when an operation member is operated to increase the transmission gear ratio and the index value is equal to or lower than the upper limit speed. The controller has a setting section that sets the upper limit speed. The setting section sets the upper limit speed based on vehicle acceleration when the controller is in the first control mode and the operation member is operated to increase the transmission gear ratio.
    Type: Grant
    Filed: October 17, 2008
    Date of Patent: March 8, 2011
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Kazuyuki Shiiba, Seiji Kuwahara, Nobufusa Kobayashi, Ichiro Kitaori, Toshihiro Fukumasu, Atsushi Yoshimura
  • Patent number: 7880308
    Abstract: There is disclosed a semiconductor device comprising at least two substrates, at least one wiring being provided in each of the substrates, the substrates being stacked such that major surfaces on one side of each thereof oppose each other and the wirings being connected between the major surfaces, and a plurality of connecting portions being provided adjacent to each other while connected to each wiring on the major surfaces opposing each other, at least one of the connecting portions provided on the same major surface being formed smaller than the adjacent other connecting portion, the connecting portions being provided at positions opposing each other one to one on the major surface, the connecting portions being connected so that the wirings are connected between the major surfaces, one connecting portion of a pair of the connecting portions connected one to one being formed smaller than the other connecting portion.
    Type: Grant
    Filed: November 21, 2006
    Date of Patent: February 1, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Atsushi Yoshimura, Yoshiaki Sugizaki
  • Patent number: 7871856
    Abstract: A method of manufacturing a stacked-type semiconductor device, comprises: arranging a plurality of stacked chips obtained by stacking semiconductor chips on a plurality of stages on a support substrate; connecting a semiconductor chip of each stage in each stacked chip and the support substrate by wire while performing heating in units of stacked chips; performing plastic molding of each stacked chip; and separating the stacked chips from each other; an apparatus for manufacturing a stacked-type semiconductor device, comprising divided heater blocks formed under a support substrate on which a plurality of stacked chips obtained by stacking a plurality of semiconductor chips are arranged, the divided heater blocks being formed with respect to the stacked chips, and a heating device to selectively transmit heat to a stacked chip subjected to a wire bonding.
    Type: Grant
    Filed: August 10, 2005
    Date of Patent: January 18, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Atsushi Yoshimura
  • Patent number: 7849897
    Abstract: An apparatus for manufacturing a semiconductor device, includes: a collet; an alignment stage; and a sheet feeding mechanism. The collet is configured to suck a surface of a semiconductor chip. The surface is on opposite side of a bonding surface to be bonded to a bonding target. The bonding surface is provided with a film-like adhesive layer. The collet includes a heater for heating the adhesive layer. The alignment stage is configured to support the semiconductor chip and to correct position of the semiconductor chip. The sheet feeding mechanism is configured to feed a release sheet onto the alignment stage.
    Type: Grant
    Filed: August 24, 2007
    Date of Patent: December 14, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shoko Omizo, Atsushi Yoshimura, Mitsuhiro Nakao, Junya Sagara, Masayuki Dohi, Tatsuhiko Shirakawa
  • Publication number: 20100224705
    Abstract: This invention serves to suppress the deterioration of oil tightness of a valve after welding without any change in the direction of fuel injection even with deformation of a convex portion after welding of an injection opening plate to a valve seat, as well as without any variation in the direction of fuel injection due to welding variation.
    Type: Application
    Filed: March 27, 2007
    Publication date: September 9, 2010
    Applicant: Mitsubishi Electric Corporation
    Inventors: Naoya Hashii, Keishi Nakano, Tsuyoshi Munezane, Atsushi Yoshimura, Manabu Miyaki
  • Patent number: 7785926
    Abstract: A first semiconductor element is bonded on a substrate. A complex film formed of integrated dicing film and adhesive film is affixed on a rear surface of a semiconductor wafer which is to be second semiconductor elements, the dicing film having a thickness within a range of not less than 50 ?m nor more than 140 ?m and a room temperature elastic modulus within a range of not less than 30 MPa nor more than 120 MPa, and the adhesive film having a thickness of 30 ?m or more and a room temperature elastic modulus before curing within a range of not less than 500 MPa nor more than 1200 MPa. The semiconductor wafer together with the adhesive film is divided into the second semiconductor elements. The second semiconductor element is picked up from the dicing film to be bonded on the first semiconductor element.
    Type: Grant
    Filed: September 17, 2009
    Date of Patent: August 31, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Atsushi Yoshimura, Tadanobu Ookubo
  • Publication number: 20100207252
    Abstract: An adhesive layer of which thickness is over 25 ?m and a dicing tape are laminated on a rear surface of a semiconductor wafer. The semiconductor wafer is cut together with a part of the adhesive layer by using a first blade of which cutting depth reaches the adhesive layer. The adhesive layer is cut together with a part of the dicing tape by using a second blade of which cutting depth reaches the dicing tape and of which width is narrower than the first blade. A semiconductor element sectioned by cutting the semiconductor wafer with the adhesive layer is picked up from the dicing tape, and is adhered on another semiconductor element or a circuit board.
    Type: Application
    Filed: April 23, 2010
    Publication date: August 19, 2010
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Atsushi Yoshimura, Tadanobu Okubo, Shigetaka Onishi
  • Publication number: 20100147273
    Abstract: A part of a ceiling wall (14) of a head cover (10) that opposes an intake collection chamber (51) is constituted by a concave ceiling wall (20) that defines a concave surface facing the intake collection chamber (51), and the concave ceiling wall (20) is formed with a recessed groove (21) that further recedes toward an inner side of the head cover.
    Type: Application
    Filed: April 30, 2008
    Publication date: June 17, 2010
    Inventors: Yoshihiro Akiyama, Atsushi Yoshimura, Isao Emi
  • Patent number: 7736999
    Abstract: An adhesive layer of which thickness is over 25 ?m and a dicing tape are laminated on a rear surface of a semiconductor wafer. The semiconductor wafer is cut together with a part of the adhesive layer by using a first blade of which cutting depth reaches the adhesive layer. The adhesive layer is cut together with a part of the dicing tape by using a second blade of which cutting depth reaches the dicing tape and of which width is narrower than the first blade. A semiconductor element sectioned by cutting the semiconductor wafer with the adhesive layer is picked up from the dicing tape, and is adhered on another semiconductor element or a circuit board.
    Type: Grant
    Filed: March 9, 2007
    Date of Patent: June 15, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Atsushi Yoshimura, Tadanobu Okubo, Shigetaka Onishi
  • Publication number: 20100062566
    Abstract: A first semiconductor element is bonded on a substrate. A complex film formed of integrated dicing film and adhesive film is affixed on a rear surface of a semiconductor wafer which is to be second semiconductor elements, the dicing film having a thickness within a range of not less than 50 ?m nor more than 140 ?m and a room temperature elastic modulus within a range of not less than 30 MPa nor more than 120 MPa, and the adhesive film having a thickness of 30 ?m or more and a room temperature elastic modulus before curing within a range of not less than 500 MPa nor more than 1200 MPa. The semiconductor wafer together with the adhesive film is divided into the second semiconductor elements. The second semiconductor element is picked up from the dicing film to be bonded on the first semiconductor element.
    Type: Application
    Filed: September 17, 2009
    Publication date: March 11, 2010
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Atsushi Yoshimura, Tadanobu Ookubo
  • Publication number: 20100035381
    Abstract: A first semiconductor element is mounted on a wiring board. A second semiconductor element having a portion projecting to an outer side of an outer periphery of the first semiconductor element is disposed on the first semiconductor element via an adhesive. The adhesive has a viscosity (?0.5 rpm) at a low-rotation speed in a range from 10 Pa·s to 150 Pa·s and a thixotropic ratio of 2 or higher expressed by a ratio (?0.5 rpm/?5 rpm) of the viscosity (?0.5 rpm) at the low-rotation speed to a viscosity (?5 rpm) at a high-rotation speed. The second semiconductor element is bonded onto the first semiconductor element while the adhesive is filled in a hollow portion between the projecting portion of the second semiconductor element and the wiring board.
    Type: Application
    Filed: July 24, 2009
    Publication date: February 11, 2010
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Atsushi Yoshimura, Shoko Omizo
  • Publication number: 20100004094
    Abstract: A controller (30) of an automatic transmission (13) can be set to be in a first control mode and a second control mode for controlling a transmission gear ratio (SR) of the automatic transmission (13). The controller (30) in the second control mode automatically changes the transmission gear ratio (SR). The controller (30) obtains an index value and upper limit speed (Lim) of rotation speed (Nout) of a transmission output shaft. The controller (30) in the first control mode allows the transmission gear ratio (SR) to be changed when an operation member (22) is operated to increase the transmission gear ratio (SR) and the index value is equal to or lower than the upper limit speed (Lim). The controller (30) has a setting section (S13) that sets the upper limit speed (Lim). The setting section (S13) sets the upper limit speed (Lim) based on vehicle acceleration (AR) when the controller (30) is in the first control mode and the operation member (22) is operated to increase the transmission gear ratio (SR).
    Type: Application
    Filed: October 17, 2008
    Publication date: January 7, 2010
    Applicant: Toyota Jidosha Kabushiki Kaisha
    Inventors: Kazuyuki Shiiba, Seiji Kuwahara, Nobufusa Kobayashi, Ichiro Kitaori, Toshihiro Fukumasu, Atsushi Yoshimura