Patents by Inventor Avanindra Madisetti
Avanindra Madisetti has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11933919Abstract: Systems and methods for synthesis of a modulated RF signal using a variety of modulation schemes are described. An embodiment includes a direct frequency synthesizer with frequency modulated continuous wave (FMCW) modulation that includes: a high speed BAW resonator that generates a frequency signal; a BAW oscillator that receives the frequency signal and generates an output BAW clock signal (BAW CLK); a frequency and phase estimation circuit that receives a reference clock signal from a reference clock (REF CLK) and the BAW CLK and generates a frequency error and a phase error; a frequency chirp generator that receives chirp parameters, a chirp sync signal and generates a nominal frequency control word (FCW); and a high speed digital to analog converter (HS DAC) that receives the BAW CLK and the codeword and outputs an analog signal.Type: GrantFiled: February 24, 2022Date of Patent: March 19, 2024Assignee: Mixed-Signal Devices Inc.Inventors: Tommy Yu, Avanindra Madisetti
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Publication number: 20240063803Abstract: Systems and methods for processing and storing digital information are described. One embodiment includes a method for linearizing digital-to-analog conversion including: receiving an input digital signal; segmenting the input digital signal into several segments, each segment being thermometer-coded; generating a redundant representation of each of the several segments, defining several redundant segments; performing a redundancy mapping for the several segments, defining redundantly mapped segments; assigning a probabilistic assignment for redundantly mapped segments; converting each redundantly mapped segment into an analog signal by a sub-digital-to-analog converter (DAC); and combining the analog signals to define an output analog signal.Type: ApplicationFiled: August 24, 2023Publication date: February 22, 2024Applicant: Mixed-Signal Devices Inc.Inventors: Tommy Yu, Avanindra Madisetti
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Patent number: 11777511Abstract: Systems and methods for processing and storing digital information are described. One embodiment includes a method for linearizing digital-to-analog conversion including: receiving an input digital signal; segmenting the input digital signal into several segments, each segment being thermometer-coded; generating a redundant representation of each of the several segments, defining several redundant segments; performing a redundancy mapping for the several segments, defining redundantly mapped segments; assigning a probabilistic assignment for redundantly mapped segments; converting each redundantly mapped segment into an analog signal by a sub-digital-to-analog converter (DAC); and combining the analog signals to define an output analog signal.Type: GrantFiled: September 14, 2021Date of Patent: October 3, 2023Assignee: Mixed-Signal Devices Inc.Inventors: Tommy Yu, Avanindra Madisetti
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Publication number: 20230266448Abstract: Systems and methods for synthesis of a modulated RF signal using a variety of modulation schemes are described. An embodiment includes a direct frequency synthesizer with frequency modulated continuous wave (FMCW) modulation that includes: a high speed BAW resonator that generates a frequency signal; a BAW oscillator that receives the frequency signal and generates an output BAW clock signal (BAW CLK); a frequency and phase estimation circuit that receives a reference clock signal from a reference clock (REF CLK) and the BAW CLK and generates a frequency error and a phase error; a frequency chirp generator that receives chirp parameters, a chirp sync signal and generates a nominal frequency control word (FCW); and a high speed digital to analog converter (HS DAC) that receives the BAW CLK and the codeword and outputs an analog signal.Type: ApplicationFiled: February 24, 2022Publication date: August 24, 2023Applicant: Mixed-Signal Devices Inc.Inventors: Tommy Yu, Avanindra Madisetti
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Publication number: 20220252694Abstract: Systems and methods for digitally synthesizing chirp signal in a low intermediate frequency (IF) band and using frequency multipliers to generate a higher frequency signal for radar applications are described. An embodiment includes a chirp signal generator that includes: a direct digital frequency synthesizer (DDFS) that is configured to receive an input sync signal and a frequency reference signal and generate several chirp signals at a first frequency that is in a low intermediate frequency (IF) band, several frequency multipliers that are configured to increase the chirp signals to higher frequencies and several bandpass filter circuits that are configured to remove nonlinearities from the chirp signals to generate a clean output signal.Type: ApplicationFiled: February 4, 2022Publication date: August 11, 2022Applicant: Mixed-Signal Devices Inc.Inventors: Tommy Yu, Avanindra Madisetti
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Patent number: 11405045Abstract: The present embodiments introduce an approach for designing perfectly linear DACs using non-ideal components. The approach may eliminate the non-linearity of the DAC and remove the conventional trade-offs between performance and complexity.Type: GrantFiled: September 10, 2021Date of Patent: August 2, 2022Assignee: Mixed-Signal Devices Inc.Inventors: Tommy Yu, Avanindra Madisetti
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Publication number: 20220085823Abstract: The present embodiments introduce an approach for designing perfectly linear DACs using non-ideal components. The approach may eliminate the non-linearity of the DAC and remove the conventional trade-offs between performance and complexity.Type: ApplicationFiled: September 10, 2021Publication date: March 17, 2022Applicant: Mixed-Signal Devices Inc.Inventors: Tommy Yu, Avanindra Madisetti
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Patent number: 11258448Abstract: Systems and methods for digital synthesis of an output signal using a frequency generated from a resonator and computing amplitude values that take into account temperature variations and resonant frequency variations resulting from manufacturing variability are described. A direct frequency synthesizer architecture is leveraged on a high Q resonator, such as a film bulk acoustic resonator (FBAR), a spectral multiband resonator (SMR), and a contour mode resonator (CMR) and is used to generate pristine signals.Type: GrantFiled: October 19, 2020Date of Patent: February 22, 2022Assignee: Mixed-Signal Devices Inc.Inventors: Tommy Yu, Avanindra Madisetti
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Publication number: 20220006465Abstract: Systems and methods for processing and storing digital information are described. One embodiment includes a method for linearizing digital-to-analog conversion including: receiving an input digital signal; segmenting the input digital signal into several segments, each segment being thermometer-coded; generating a redundant representation of each of the several segments, defining several redundant segments; performing a redundancy mapping for the several segments, defining redundantly mapped segments; assigning a probabilistic assignment for redundantly mapped segments; converting each redundantly mapped segment into an analog signal by a sub-digital-to-analog converter (DAC); and combining the analog signals to define an output analog signal.Type: ApplicationFiled: September 14, 2021Publication date: January 6, 2022Applicant: Mixed-Signal Devices Inc.Inventors: Tommy Yu, Avanindra Madisetti
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Publication number: 20210175889Abstract: Systems and methods for digital synthesis of an output signal using a frequency generated from a resonator and computing amplitude values that take into account temperature variations and resonant frequency variations resulting from manufacturing variability are described. A direct frequency synthesizer architecture is leveraged on a high Q resonator, such as a film bulk acoustic resonator (FBAR), a spectral multiband resonator (SMR), and a contour mode resonator (CMR) and is used to generate pristine signals.Type: ApplicationFiled: October 19, 2020Publication date: June 10, 2021Applicant: Mixed-Signal Devices Inc.Inventors: Tommy Yu, Avanindra Madisetti
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Patent number: 10840939Abstract: A parallel delta sigma modulator architecture is disclosed. The parallel delta sigma modulator architecture includes a signal demultiplexer configured to receive an input signal and to demultiplex the input signal to output a plurality of streams, a plurality of delta sigma modulators executing in parallel, each delta sigma modulator configured to receive a stream from the plurality of streams and to generate a delta sigma modulated output, and a signal multiplexer configured to receive a plurality of delta sigma modulated outputs from the plurality of delta sigma modulators and to multiplex together the plurality of delta sigma modulated outputs into a pulse train.Type: GrantFiled: July 29, 2019Date of Patent: November 17, 2020Assignee: Mixed-Signal Devices Inc.Inventors: Tommy Yu, Avanindra Madisetti
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Patent number: 10812087Abstract: Systems and methods for digital synthesis of an output signal using a frequency generated from a resonator and computing amplitude values that take into account temperature variations and resonant frequency variations resulting from manufacturing variability are described. A direct frequency synthesizer architecture is leveraged on a high Q resonator, such as a film bulk acoustic resonator (FBAR), a spectral multiband resonator (SMR), and a contour mode resonator (CMR) and is used to generate pristine signals.Type: GrantFiled: December 4, 2019Date of Patent: October 20, 2020Assignee: Mixed-Signal Devices Inc.Inventors: Tommy Yu, Avanindra Madisetti
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Publication number: 20200106448Abstract: Systems and methods for digital synthesis of an output signal using a frequency generated from a resonator and computing amplitude values that take into account temperature variations and resonant frequency variations resulting from manufacturing variability are described. A direct frequency synthesizer architecture is leveraged on a high Q resonator, such as a film bulk acoustic resonator (FBAR), a spectral multiband resonator (SMR), and a contour mode resonator (CMR) and is used to generate pristine signals.Type: ApplicationFiled: December 4, 2019Publication date: April 2, 2020Applicant: MY Tech, LLCInventors: Tommy Yu, Avanindra Madisetti
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Patent number: 10530372Abstract: Systems and methods for digital synthesis of an output signal using a frequency generated from a resonator and computing amplitude values that take into account temperature variations and resonant frequency variations resulting from manufacturing variability are described. A direct frequency synthesizer architecture is leveraged on a high Q resonator, such as a film bulk acoustic resonator (FBAR), a spectral multiband resonator (SMR), and a contour mode resonator (CMR) and is used to generate pristine signals.Type: GrantFiled: March 27, 2017Date of Patent: January 7, 2020Assignee: MY Tech, LLCInventors: Tommy Yu, Avanindra Madisetti
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Publication number: 20190356329Abstract: A parallel delta sigma modulator architecture is disclosed. The parallel delta sigma modulator architecture includes a signal demultiplexer configured to receive an input signal and to demultiplex the input signal to output a plurality of streams, a plurality of delta sigma modulators executing in parallel, each delta sigma modulator configured to receive a stream from the plurality of streams and to generate a delta sigma modulated output, and a signal multiplexer configured to receive a plurality of delta sigma modulated outputs from the plurality of delta sigma modulators and to multiplex together the plurality of delta sigma modulated outputs into a pulse train.Type: ApplicationFiled: July 29, 2019Publication date: November 21, 2019Applicant: MY Tech, LLCInventors: Tommy Yu, Avanindra Madisetti
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Patent number: 10367522Abstract: A parallel delta sigma modulator architecture is disclosed. The parallel delta sigma modulator architecture includes a signal demultiplexer configured to receive an input signal and to demultiplex the input signal to output a plurality of streams, a plurality of delta sigma modulators executing in parallel, each delta sigma modulator configured to receive a stream from the plurality of streams and to generate a delta sigma modulated output, and a signal multiplexer configured to receive a plurality of delta sigma modulated outputs from the plurality of delta sigma modulators and to multiplex together the plurality of delta sigma modulated outputs into a pulse train.Type: GrantFiled: November 21, 2017Date of Patent: July 30, 2019Assignee: MY Tech, LLCInventors: Tommy Yu, Avanindra Madisetti
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Patent number: 10020818Abstract: An error feedback system for a delta sigma modulator is disclosed. The error feedback system has an error transfer function where at least k?1 coefficients are set to zero. This allows the error feedback system to be divided into k feedback paths that are performed in parallel at a clock speed that is 1/k of the system clock of the delta sigma modulator (i.e. the rate at which the output of the delta sigma modulator changes).Type: GrantFiled: March 27, 2017Date of Patent: July 10, 2018Assignee: MY Tech, LLCInventors: Tommy Yu, Avanindra Madisetti
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Publication number: 20180145700Abstract: A parallel delta sigma modulator architecture is disclosed. The parallel delta sigma modulator architecture includes a signal demultiplexer configured to receive an input signal and to demultiplex the input signal to output a plurality of streams, a plurality of delta sigma modulators executing in parallel, each delta sigma modulator configured to receive a stream from the plurality of streams and to generate a delta sigma modulated output, and a signal multiplexer configured to receive a plurality of delta sigma modulated outputs from the plurality of delta sigma modulators and to multiplex together the plurality of delta sigma modulated outputs into a pulse train.Type: ApplicationFiled: November 21, 2017Publication date: May 24, 2018Applicant: MY Tech, LLCInventors: Tommy Yu, Avanindra Madisetti
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Patent number: 8934527Abstract: A method for providing a next-cycle input sample from a decision feedback equalizer to a symbol decoder using look-ahead computations such that timing contention between the decision feedback equalizer and the symbol decoder is reduced. During a symbol period, a set of possible values is computed in the decision feedback equalizer and a set of path memory symbols is computed in the symbol decoder, the set of path memory symbols being based on a current input sample. During the same symbol period, one of the possible values is selected as the next-cycle input sample based on at least one of the next-cycle path memory symbols produced from the symbol decoder.Type: GrantFiled: June 15, 2010Date of Patent: January 13, 2015Assignee: Broadcom CorporationInventors: Arthur Abnous, Avanindra Madisetti, Christian A. J. Lutkemeyer
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Patent number: 8824538Abstract: Methods and systems adaptively equalizing an analog information signal, the method including sampling the analog information signal to provide analog samples including post-transition samples and steady-state samples, and equalizing the analog samples to produce equalized analog samples. The equalizing includes determining a difference between an average post-transition amplitude associated with at least one of the post-transition samples and an average steady-state amplitude associated with at least one of the steady-state samples, and adjusting an equalization coefficient to adjust the difference between the average post-transition amplitude and the average steady-state amplitude.Type: GrantFiled: May 16, 2013Date of Patent: September 2, 2014Assignee: Broadcom CorporationInventors: Aaron Buchwald, Xicheng Jiang, Hui Wang, Howard A. Baumer, Avanindra Madisetti