Patents by Inventor Avanindra Madisetti
Avanindra Madisetti has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7058150Abstract: A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates. Each receiver includes a timing recovery system for tracking a phase and a frequency of the serial data signal associated with the receiver. The timing recovery system includes a phase interpolator responsive to phase control signals and a set of reference signals having different predetermined phases. The phase interpolator derives a sampling signal, having an interpolated phase, to sample the serial data signal. The timing recovery system in each receiver independently phase-aligns and frequency synchronizes the sampling signal to the serial data signal associated with the receiver. A receiver can include multiple paths for sampling a received, serial data signal in accordance with multiple time-staggered sampling signals, each having an interpolated phase.Type: GrantFiled: April 30, 2001Date of Patent: June 6, 2006Assignee: Broadcom CorporationInventors: Aaron W. Buchwald, Michael Le, Jurgen Van Engelen, Xicheng Jiang, Hui Wang, Howard A. Baumer, Avanindra Madisetti
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Patent number: 7016449Abstract: A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates. Each receiver includes a timing recovery system for tracking a phase and a frequency of the serial data signal associated with the receiver. The timing recovery system includes a phase interpolator responsive to phase control signals and a set of reference signals having different predetermined phases. The phase interpolator derives a sampling signal, having an interpolated phase, to sample the serial data signal. The timing recovery system in each receiver independently phase-aligns and frequency synchronizes the sampling signal to the serial data signal associated with the receiver. A receiver can include multiple paths for sampling a received, serial data signal in accordance with multiple time-staggered sampling signals, each having an interpolated phase.Type: GrantFiled: April 30, 2001Date of Patent: March 21, 2006Assignee: Broadcom CorporationInventors: Aaron W. Buchwald, Myles Wakayama, Michael Le, Jurgen Van Engelen, Xicheng Jiang, Hui Wang, Howard A. Baumer, Avanindra Madisetti
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Patent number: 7012983Abstract: A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates. Each receiver includes a timing recovery system for tracking a phase and a frequency of the serial data signal associated with the receiver. The timing recovery system includes a phase interpolator responsive to phase control signals and a set of reference signals having different predetermined phases. The phase interpolator derives a sampling signal, having an interpolated phase, to sample the serial data signal. The timing recovery system in each receiver independently phase-aligns and frequency synchronizes the sampling signal to the serial data signal associated with the receiver. A receiver can include multiple paths for sampling a received, serial data signal in accordance with multiple time-staggered sampling signals, each having an interpolated phase.Type: GrantFiled: April 30, 2001Date of Patent: March 14, 2006Assignee: Broadcom CorporationInventors: Aaron W. Buchwald, Myles Wakayama, Michael Le, Jurgen Van Engelen, Xicheng Jiang, Hui Wang, Howard A. Baumer, Avanindra Madisetti
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Patent number: 6995594Abstract: A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates. Each receiver includes a timing recovery system for tracking a phase and a frequency of the serial data signal associated with the receiver. The timing recovery system includes a phase interpolator responsive to phase control signals and a set of reference signals having different predetermined phases. The phase interpolator derives a sampling signal, having an interpolated phase, to sample the serial data signal. The timing recovery system in each receiver independently phase-aligns and frequency synchronizes the sampling signal to the serial data signal associated with the receiver. A receiver can include multiple paths for sampling a received, serial data signal in accordance with multiple time-staggered sampling signals, each having an interpolated phase.Type: GrantFiled: May 28, 2004Date of Patent: February 7, 2006Assignee: Broadcom CorporationInventors: Aaron W. Buchwald, Myles Wakayama, Michael Le, Jurgen Van Engelen, Xicheng Jiang, Hui Wang, Howard A. Baumer, Avanindra Madisetti
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Publication number: 20040212416Abstract: A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates. Each receiver includes a timing recovery system for tracking a phase and a frequency of the serial data signal associated with the receiver. The timing recovery system includes a phase interpolator responsive to phase control signals and a set of reference signals having different predetermined phases. The phase interpolator derives a sampling signal, having an interpolated phase, to sample the serial data signal. The timing recovery system in each receiver independently phase-aligns and frequency synchronizes the sampling signal to the serial data signal associated with the receiver. A receiver can include multiple paths for sampling a received, serial data signal in accordance with multiple time-staggered sampling signals, each having an interpolated phase.Type: ApplicationFiled: May 28, 2004Publication date: October 28, 2004Applicant: Broadcom CorporationInventors: Aaron W. Buchwald, Myles Wakayama, Michael Le, Josephus Van Engelen, Xicheng Jiang, Hui Wang, Howard A. Baumer, Avanindra Madisetti
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Patent number: 6791388Abstract: A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates. Each receiver includes a timing recovery system for tracking a phase and a frequency of the serial data signal associated with the receiver. The timing recovery system includes a phase interpolator responsive to phase control signals and a set of reference signals having different predetermined phases. The phase interpolator derives a sampling signal, having an interpolated phase, to sample the serial data signal. The timing recovery system in each receiver independently phase-aligns and frequency synchronizes the sampling signal to the serial data signal associated with the receiver. A receiver can include multiple paths for sampling a received, serial data signal in accordance with multiple time-staggered sampling signals, each having an interpolated phase.Type: GrantFiled: January 17, 2003Date of Patent: September 14, 2004Assignee: Broadcom CorporationInventors: Aaron W. Buchwald, Myles Wakayama, Michael Le, Jurgen Van Engelen, Xicheng Jiang, Hui Wang, Howard A. Baumer, Avanindra Madisetti
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Publication number: 20030141914Abstract: A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates. Each receiver includes a timing recovery system for tracking a phase and a frequency of the serial data signal associated with the receiver. The timing recovery system includes a phase interpolator responsive to phase control signals and a set of reference signals having different predetermined phases. The phase interpolator derives a sampling signal, having an interpolated phase, to sample the serial data signal. The timing recovery system in each receiver independently phase-aligns and frequency synchronizes the sampling signal to the serial data signal associated with the receiver. A receiver can include multiple paths for sampling a received, serial data signal in accordance with multiple time-staggered sampling signals, each having an interpolated phase.Type: ApplicationFiled: January 17, 2003Publication date: July 31, 2003Inventors: Aaron W. Buchwald, Myles Wakayama, Michael Le, Josephus Van Engelen, Xicheng Jiang, Hui Wang, Howard A. Baumer, Avanindra Madisetti
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Publication number: 20030123572Abstract: An aspect of the invention provides for recovering communicated information in a communication system. Recovering communicated information in a communication system may include generating a first digital signal from a received analog signal bearing communicated information, the first digital signal having a pre-cursor response and a post-cursor response. A second digital signal may be generated that limits a duration of at least a portion of the post-cursor response and a third digital signal may be generated that inhibits at least a portion of the pre-cursor response. A fourth digital signal that inhibits at least a portion of the post-cursor response and a fifth digital signal that limits a duration of at least a portion of the fourth signal may be generated in order to recover the communicated information. A sixth digital signal based on at least the third digital signal and the fifth digital signal may be generated.Type: ApplicationFiled: September 30, 2002Publication date: July 3, 2003Inventors: Henry Samueli, Fang Lu, Avanindra Madisetti
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Patent number: 6509773Abstract: A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates. Each receiver includes a timing recovery system for tracking a phase and a frequency of the serial data signal associated with the receiver. The timing recovery system includes a phase interpolator responsive to phase control signals and a set of reference signals having different predetermined phases. The phase interpolator derives a sampling signal, having an interpolated phase, to sample the serial data signal. The timing recovery system in each receiver independently phase-aligns and frequency synchronizes the sampling signal to the serial data signal associated with the receiver. A receiver can include multiple paths for sampling a received, serial data signal in accordance with multiple time-staggered sampling signals, each having an interpolated phase.Type: GrantFiled: April 30, 2001Date of Patent: January 21, 2003Assignee: Broadcom CorporationInventors: Aaron W. Buchwald, Myles Wakayama, Michael Le, Jurgen Van Engelen, Xicheng Jiang, Hui Wang, Howard A. Baumer, Avanindra Madisetti
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Patent number: 6459730Abstract: Digital signals provided by a repeater connected to a plurality of clients by unshielded twisted wire pairs, are converted to analog signals which become degraded during transmission through the wires. Clients convert the degraded analog signals to digital signals. Digital signal phases are coarsely adjusted to have assumed zero crossing times coincide in-time with a clock signal zero crossing. Signal polarity, and the polarity of any change, is determined at the assumed zero crossing times of the digital signals. Pre-cursor and post-cursor responses, resulting from signal degradation, are respectively inhibited by a feed forward and a decision feedback equalizer. The time duration of post-cursor response is further inhibited by a high pass filter and a tail canceller. Phase adjustments are made, after response inhibition, by determining the polarity, and the polarity of any change, at the assumed zero crossing times.Type: GrantFiled: January 13, 2000Date of Patent: October 1, 2002Assignee: Broadcom CorporationInventors: Henry Samueli, Fang Lu, Avanindra Madisetti
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Publication number: 20020122480Abstract: A method for providing a next-cycle input sample from a decision feedback equalizer to a symbol decoder using look-ahead computations such that timing contention between the decision feedback equalizer and the symbol decoder is reduced. During a symbol period, a set of possible values is computed in the decision feedback equalizer and a set of path memory symbols is computed in the symbol decoder, the set of path memory symbols being based on a current input sample. During the same symbol period, one of the possible values is selected as the next-cycle input sample based on at least one of the next-cycle path memory symbols produced from the symbol decoder.Type: ApplicationFiled: March 12, 2001Publication date: September 5, 2002Inventors: Arthur Abnous, Avanindra Madisetti, Christian A.J. Lutkemeyer
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Publication number: 20020044618Abstract: A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates. Each receiver includes a timing recovery system for tracking a phase and a frequency of the serial data signal associated with the receiver. The timing recovery system includes a phase interpolator responsive to phase control signals and a set of reference signals having different predetermined phases. The phase interpolator derives a sampling signal, having an interpolated phase, to sample the serial data signal. The timing recovery system in each receiver independently phase-aligns and frequency synchronizes the sampling signal to the serial data signal associated with the receiver. A receiver can include multiple paths for sampling a received, serial data signal in accordance with multiple time-staggered sampling signals, each having an interpolated phase.Type: ApplicationFiled: April 30, 2001Publication date: April 18, 2002Inventors: Aaron W. Buchwald, Michael Le, Josephus Van Engelen, Xicheng Jiang, Hui Wang, Howard A. Baumer, Avanindra Madisetti
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Publication number: 20020044617Abstract: A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates. Each receiver includes a timing recovery system for tracking a phase and a frequency of the serial data signal associated with the receiver. The timing recovery system includes a phase interpolator responsive to phase control signals and a set of reference signals having different predetermined phases. The phase interpolator derives a sampling signal, having an interpolated phase, to sample the serial data signal. The timing recovery system in each receiver independently phase-aligns and frequency synchronizes the sampling signal to the serial data signal associated with the receiver. A receiver can include multiple paths for sampling a received, serial data signal in accordance with multiple time-staggered sampling signals, each having an interpolated phase.Type: ApplicationFiled: April 30, 2001Publication date: April 18, 2002Inventors: Aaron W. Buchwald, Myles Wakayama, Michael Le, Josephus Van Engelen, Xicheng Jiang, Hui Wang, Howard A. Baumer, Avanindra Madisetti
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Publication number: 20020039395Abstract: A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates. Each receiver includes a timing recovery system for tracking a phase and a frequency of the serial data signal associated with the receiver. The timing recovery system includes a phase interpolator responsive to phase control signals and a set of reference signals having different predetermined phases. The phase interpolator derives a sampling signal, having an interpolated phase, to sample the serial data signal. The timing recovery system in each receiver independently phase-aligns and frequency synchronizes the sampling signal to the serial data signal associated with the receiver. A receiver can include multiple paths for sampling a received, serial data signal in accordance with multiple time-staggered sampling signals, each having an interpolated phase.Type: ApplicationFiled: April 30, 2001Publication date: April 4, 2002Inventors: Aaron W. Buchwald, Myles Wakayama, Michael Le, Josephus van Engelen, Xicheng Jiang, Hui Wang, Howard A. Baumer, Avanindra Madisetti
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Publication number: 20020039394Abstract: A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates. Each receiver includes a timing recovery system for tracking a phase and a frequency of the serial data signal associated with the receiver. The timing recovery system includes a phase interpolator responsive to phase control signals and a set of reference signals having different predetermined phases. The phase interpolator derives a sampling signal, having an interpolated phase, to sample the serial data signal. The timing recovery system in each receiver independently phase-aligns and frequency synchronizes the sampling signal to the serial data signal associated with the receiver. A receiver can include multiple paths for sampling a received, serial data signal in accordance with multiple time-staggered sampling signals, each having an interpolated phase.Type: ApplicationFiled: April 30, 2001Publication date: April 4, 2002Inventors: Aaron W. Buchwald, Myles Wakayama, Michael Le, Josephus Van Engelen, Xicheng Jiang, Hui Wang, Howard A. Baumer, Avanindra Madisetti
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Publication number: 20020034222Abstract: Methods and systems for minimizing distortions in an analog data signal include equalizing the analog data signal at a receive end. In an embodiment, the invention adapts equalization parameters to a signal path associated with the analog data signal. Adaptive control logic is implemented with analog and/or digital components. In an embodiment, the invention equalizes a discreet-time analog representation of an analog data signal. In an embodiment, the invention digitally controls equalization parameters. In an embodiment, a resultant equalized analog data signal is digitized. In an example implementation, an analog data signal is sampled, a quality of the samples is measured, and one or more equalization parameters are adjusted with digital controls as needed to minimize distortion of the samples. The equalized samples are then digitized. The present invention is suitable for lower rate analog data signals and multi-gigabit data rate analog signals.Type: ApplicationFiled: April 30, 2001Publication date: March 21, 2002Inventors: Aaron Buchwald, Xicheng Jiang, Hui Wang, Howard A. Baumer, Avanindra Madisetti
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Patent number: 6178198Abstract: Digital signals provided by a repeater connected to a plurality of clients by unshielded twisted wire pairs, are converted to analog signals which become degraded during transmission through the wires. Clients convert the degraded analog signals to digital signals. Digital signal phases are coarsely adjusted to have assumed zero crossing times coincide in-time with a clock signal zero crossing. Signal polarity, and the polarity of any change, is determined at the assumed zero crossing times of the digital signals. Pre-cursor and post-cursor responses, resulting from signal degradation, are respectively inhibited by a feed forward and a decision feedback equalizer. The time duration of post-cursor response is further inhibited by a high pass filter and a tail canceller. Phase adjustments are made, after response inhibition, by determining the polarity, and the polarity of any change, at the assumed zero crossing times.Type: GrantFiled: November 14, 1997Date of Patent: January 23, 2001Assignee: Broadcom CorproationInventors: Henry Samueli, Fang Lu, Avanindra Madisetti
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Patent number: 5737253Abstract: The present invention comprises a direct digital frequency synthesizer. A phase accumulator provides a normalized angle .theta. to a sine/cosine generator that outputs the value of the sine/cosine function at the provided angle. The she/cosine generator in a preferred embodiment comprises a plurality of multiplierless butterfly and carry-save stages in cascade that perform angle rotations on a phasor on the unit circle whose x and y coordinates correspond to cosine and sine values. To calculate the sine and cosine values at a particular angle .theta.=b.sub.1 .theta..sub.1 +b.sub.2 .theta..sub.2 +. . . +b.sub.N .theta..sub.N where b.sub.k .epsilon. {0, 1} are the binary bits and the .theta..sub.k =2.sup.-k are the associated positional weights, each of the butterfly and carry-save stages rotate the phasor by an amount .theta..sub.k =2.sup.-k. The direction of the rotation, clockwise or counter-clockwise, depends upon the value of the binary bits b.sub.k.Type: GrantFiled: August 30, 1995Date of Patent: April 7, 1998Assignee: Pentomics, Inc.Inventors: Avanindra Madisetti, Alan Y. Kwentus