Abstract: A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates. Each receiver includes a timing recovery system for tracking a phase and a frequency of the serial data signal associated with the receiver. The timing recovery system includes a phase interpolator responsive to phase control signals and a set of reference signals having different predetermined phases. The phase interpolator derives a sampling signal, having an interpolated phase, to sample the serial data signal. The timing recovery system in each receiver independently phase-aligns and frequency synchronizes the sampling signal to the serial data signal associated with the receiver. A receiver can include multiple paths for sampling a received, serial data signal in accordance with multiple time-staggered sampling signals, each having an interpolated phase.

Abstract: Methods and systems adaptively equalizing an analog information signal, the method including sampling the analog information signal to provide analog samples including post-transition samples and steady-state samples, and equalizing the analog samples to produce equalized analog samples. The equalizing includes determining a difference between an average post-transition amplitude associated with at least one of the post-transition samples and an average steady-state amplitude associated with at least one of the steady-state samples, and adjusting an equalization coefficient to adjust the difference between the average post-transition amplitude and the average steady-state amplitude.

Abstract: Methods and systems for adaptively equalizing an analog information signal for a signal path, including sampling the analog information signal, thereby generating analog samples, and performing an equalizing process on the analog samples, wherein the equalizing includes processing an average of post-transition sample amplitudes and an average of steady state sample amplitudes of the analog samples to produce equalized analog samples.

Abstract: A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates. Each receiver includes a timing recovery system for tracking a phase and a frequency of the serial data signal associated with the receiver. The timing recovery system includes a phase interpolator responsive to phase control signals and a set of reference signals having different predetermined phases. The phase interpolator derives a sampling signal, having an interpolated phase, to sample the serial data signal. The timing recovery system in each receiver independently phase-aligns and frequency synchronizes the sampling signal to the serial data signal associated with the receiver. A receiver can include multiple paths for sampling a received, serial data signal in accordance with multiple time-staggered sampling signals, each having an interpolated phase.

Abstract: Methods and systems for adaptively equalizing an analog information signal for a signal path, including sampling the analog information signal, thereby generating analog samples, and performing an equalizing process on the analog samples, wherein the equalizing includes processing an average of post-transition sample amplitudes and an average of steady state sample amplitudes of the analog samples to produce equalized analog samples.

Abstract: Systems for recovering communicated information in a communication system are disclosed and may include at least one digitizer for digitizing an analog received signal comprising the communicated information, thereby creating a digital received signal. The system may include at least one filter for bandwidth-limiting at least a portion of the digital received signal. At least one feed forward equalizer may be used for equalizing at least a portion of the bandwidth-limited signal to create an equalized signal. At least one converter for creating a data signal according to at least the equalized signal. At least one soft decision circuit for creating a soft decision signal according to the data signal. The soft decision circuit may cancel at least a portion of the equalized signal.

Abstract: Methods and systems for minimizing distortions in an analog data signal include equalizing the analog data signal at a receive end. In an embodiment, the invention adapts equalization parameters to a signal path associated with the analog data signal. Adaptive control logic is implemented with analog and/or digital components. In an embodiment, the invention equalizes a discrete-time analog representation of an analog data signal. In an embodiment, the invention digitally controls equalization parameters. In an embodiment, a resultant equalized analog data signal is digitized. In an example implementation, an analog data signal is sampled, a quality of the samples is measured, and one or more equalization parameters are adjusted with digital controls as needed to minimize distortion of the samples. The equalized samples are then digitized. The present invention is suitable for lower rate analog data signals and multi-gigabit data rate analog signals.

Abstract: A method for providing a next-cycle input sample from a decision feedback equalizer to a symbol decoder using look-ahead computations such that timing contention between the decision feedback equalizer and the symbol decoder is reduced. During a symbol period, a set of possible values is computed in the decision feedback equalizer and a set of path memory symbols is computed in the symbol decoder, the set of path memory symbols being based on a current input sample. During the same symbol period, one of the possible values is selected as the next-cycle input sample based on at least one of the next-cycle path memory symbols produced from the symbol decoder.

Abstract: Skew between a first clock signal received by a first analog-to-digital converter (ADC) and a second clock signal received by a second ADC is adjusted to minimize error. Each ADC has an ADC element that produces a respective first or second digital output signal in response to an analog input signal and a respective first or second clock signal. A correction signal is produced in response to the first and second digital output signals. The skew between the first and second clock signals is then adjusted in response to the correction signal.

Abstract: An apparatus for converting an analog signal to a digital signal comprising a first analog to digital converter for generating a first digital value from an analog value. A second analog to digital converter for generating a second digital value from the analog value. Logic for determining a correction factor for the second digital value based on a difference between the first digital value and the second digital value, wherein the logic updates the correction factor.

Abstract: A method for providing a next-cycle input sample from a decision feedback equalizer to a symbol decoder using look-ahead computations such that timing contention between the decision feedback equalizer and the symbol decoder is reduced. During a symbol period, a set of possible values is computed in the decision feedback equalizer and a set of path memory symbols is computed in the symbol decoder, the set of path memory symbols being based on a current input sample. During the same symbol period, one of the possible values is selected as the next-cycle input sample based on at least one of the next-cycle path memory symbols produced from the symbol decoder.

Abstract: Skew between a first clock signal received by a first analog-to-digital converter (ADC) and a second clock signal received by a second ADC is adjusted to minimize error. Each ADC has an ADC element that produces a respective first or second digital output signal in response to an analog input signal and a respective first or second clock signal. A correction signal is produced in response to the first and second digital output signals. The skew between the first and second clock signals is then adjusted in response to the correction signal.

Abstract: An apparatus for converting an analog signal to a digital signal comprising a first analog to digital converter for generating a first digital value from an analog value. A second analog to digital converter for generating a second digital value from the analog value. Logic for determining a correction factor for the second digital value based on a difference between the first digital value and the second digital value, wherein the logic updates the correction factor.

Abstract: Systems for recovering communicated information in a communication system are disclosed and may include at least one digitizer for digitizing an analog received signal comprising the communicated information, thereby creating a digital received signal. The system may include at least one filter for bandwidth-limiting at least a portion of the digital received signal. At least one feed forward equalizer may be used for equalizing at least a portion of the bandwidth-limited signal to create an equalized signal. At least one converter for creating a data signal according to at least the equalized signal. At least one soft decision circuit for creating a soft decision signal according to the data signal. The soft decision circuit may cancel at least a portion of the equalized signal.

Abstract: Methods and systems for minimizing distortions in an analog data signal include equalizing the analog data signal at a receive end. In an embodiment, the invention adapts equalization parameters to a signal path associated with the analog data signal. Adaptive control logic is implemented with analog and/or digital components. In an embodiment, the invention equalizes a discreet-time analog representation of an analog data signal. In an embodiment, the invention digitally controls equalization parameters. In an embodiment, a resultant equalized analog data signal is digitized. In an example implementation, an analog data signal is sampled, a quality of the samples is measured, and one or more equalization parameters are adjusted with digital controls as needed to minimize distortion of the samples. The equalized samples are then digitized. The present invention is suitable for lower rate analog data signals and multi-gigabit data rate analog signals.

Abstract: An aspect of the invention provides for recovering communicated information in a communication system. Recovering communicated information in a communication system may include generating a first digital signal from a received analog signal bearing communicated information, the first digital signal having a pre-cursor response and a post-cursor response. A second digital signal may be generated that limits a duration of at least a portion of the post-cursor response and a third digital signal may be generated that inhibits at least a portion of the pre-cursor response. A fourth digital signal that inhibits at least a portion of the post-cursor response and a fifth digital signal that limits a duration of at least a portion of the fourth signal may be generated in order to recover the communicated information. A sixth digital signal based on at least the third digital signal and the fifth digital signal may be generated.

Abstract: Methods and systems for minimizing distortions in an analog data signal include equalizing the analog data signal at a receive end. In an embodiment, the invention adapts equalization parameters to a signal path associated with the analog data signal. Adaptive control logic is implemented with analog and/or digital components. In an embodiment, the invention equalizes a discreet-time analog representation of an analog data signal. In an embodiment, the invention digitally controls equalization parameters. In an embodiment, a resultant equalized analog data signal is digitized. In an example implementation, an analog data signal is sampled, a quality of the samples is measured, and one or more equalization parameters are adjusted with digital controls as needed to minimize distortion of the samples. The equalized samples are then digitized. The present invention is suitable for lower rate analog data signals and multi-gigabit data rate analog signals.

Abstract: A method for providing a next-cycle input sample from a decision feedback equalizer to a symbol decoder using look-ahead computations such that timing contention between the decision feedback equalizer and the symbol decoder is reduced. During a symbol period, a set of possible values is computed in the decision feedback equalizer and a set of path memory symbols is computed in the symbol decoder, the set of path memory symbols being based on a current input sample. During the same symbol period, one of the possible values is selected as the next-cycle input sample based on at least one of the next-cycle path memory symbols produced from the symbol decoder.

Abstract: A method for providing a next-cycle input sample from a decision feedback equalizer to a symbol decoder using look-ahead computations such that timing contention between the decision feedback equalizer and the symbol decoder is reduced. During a symbol period, a set of possible values is computed in the decision feedback equalizer and a set of path memory symbols is computed in the symbol decoder, the set of path memory symbols being based on a current input sample. During the same symbol period, one of the possible values is selected as the next-cycle input sample based on at least one of the next-cycle path memory symbols produced from the symbol decoder.

Abstract: A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates. Each receiver includes a timing recovery system for tracking a phase and a frequency of the serial data signal associated with the receiver. The timing recovery system includes a phase interpolator responsive to phase control signals and a set of reference signals having different predetermined phases. The phase interpolator derives a sampling signal, having an interpolated phase, to sample the serial data signal. The timing recovery system in each receiver independently phase-aligns and frequency synchronizes the sampling signal to the serial data signal associated with the receiver. A receiver can include multiple paths for sampling a received, serial data signal in accordance with multiple time-staggered sampling signals, each having an interpolated phase.