Patents by Inventor Avinash Seetharamaiah
Avinash Seetharamaiah has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12380625Abstract: The present disclosure relates to graphics processing. An apparatus of the present disclosure may determine visibility streams corresponding to a target and a set of bins into which the target is divided. The apparatus may select one of a first rendering mode or a second rendering mode for the target based on the first visibility stream and based on the set of second visibility streams. When the first rendering mode is select, the apparatus may configure each of the set of bins into a first subset associated with a first type of rendering pass or a second subset associated with a second type of rendering pass. The apparatus may then render the target based on the selected one of the first rendering mode or the second rendering mode and, if applicable, based on the first rendering pass type or the second rendering pass type.Type: GrantFiled: November 18, 2020Date of Patent: August 5, 2025Assignee: QUALCOMM IncorporatedInventors: Srihari Babu Alla, Jonnala Gadda Nagendra Kumar, Avinash Seetharamaiah, Andrew Evan Gruber, Thomas Edwin Frisinger, Richard Hammerstone, Bo Du, Yongjun Xu
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Patent number: 12353603Abstract: Systems, methods, and computer-readable media are provided for signing and executing graphics processing unit (GPU) commands. In some examples, a method can include receiving, by a GPU, one or more commands including one or more verification signatures generated using a processor, each verification signature of the one or more verification signatures including a first value generated based on the one or more commands; generating, by the GPU, one or more additional verification signatures associated with the one or more commands, wherein each verification signature of the one or more additional verification signatures includes a second value generated by the GPU based on the one or more commands; and determining, by the GPU, a validity of the one or more commands based on a comparison of the one or more verification signatures and the one or more additional verification signatures.Type: GrantFiled: October 14, 2020Date of Patent: July 8, 2025Assignee: QUALCOMM IncorporatedInventors: Avinash Seetharamaiah, Murat Balci, Jonnala Gadda Nagendra Kumar, Nigel Poole, Abhiraj Deshpande
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Publication number: 20250173946Abstract: Aspects presented herein relate to methods and devices for graphics processing including an apparatus, e.g., a GPU. The apparatus may obtain an indication of a plurality of render targets (RTs) associated with a rendering process, where each of the plurality of RTs is associated with a subset of a graphics surface for the rendering process. The apparatus may also select at least one RT in the plurality of RTs based on the subset of the graphics surface associated with the at least one RT. Further, the apparatus may store the selected at least one RT in a buffer or a cache, or refraining from storing the selected at least one RT in the buffer or the cache.Type: ApplicationFiled: November 27, 2023Publication date: May 29, 2025Inventors: Md Wahidul ISLAM, Jonnala Gadda NAGENDRA KUMAR, Andrew Evan GRUBER, Avinash SEETHARAMAIAH, Tao WANG, Brendon Lewis JOHNSON, Thomas Edwin FRISINGER, Zhenbiao MA, Raghavendra NAGARAJ
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Patent number: 12229864Abstract: This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for runtime optimization of the shader execution flow. A graphics processor may obtain instruction execution data associated with a graphics workload, the instruction execution data including graphics data for a set of shader operations. The graphics processor may configure, at a first iteration, at least one predication value based on the instruction execution data including the graphics data for the set of shader operations. The graphics processor may adjust, at a second iteration, an execution flow of the graphics workload based on the configured at least one predication value, the execution flow of the graphics workload including the set of shader operations. The graphics processor may execute or refrain from executing, at the second iteration, each of the set of shader operations based on the adjusted execution flow of the graphics workload.Type: GrantFiled: August 5, 2022Date of Patent: February 18, 2025Assignee: QUALCOMM IncorporatedInventors: Yun Du, Eric Demers, Andrew Evan Gruber, Chun Yu, Baoguang Yang, Chihong Zhang, Yuehai Du, Avinash Seetharamaiah, Jonnala Gadda Nagendra Kumar, Gang Zhong, Zilin Ying, Fei Wei
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Publication number: 20250022204Abstract: This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for adaptive BVH rebuilds with biased cost functions for dynamic geometry. A graphics processor may obtain an indication of first BVH structure(s) including first nodes, where the first BVH structure(s) are representative of first geometry data for first primitives in first frame(s), where each of the first nodes is associated with first primitive(s), may detect a number of rays that intersect each of the first BVH structure(s) from direction(s) associated with the first frame(s), may update a cost function based on the number of rays and each of the direction(s), and may configure, based on the updated cost function, second BVH structure(s) including second nodes, where the second BVH structure(s) are representative of second geometry data for second primitives in second frame(s), where each of the second nodes is associated with second primitive(s).Type: ApplicationFiled: July 12, 2023Publication date: January 16, 2025Inventors: Adimulam RAMESH BABU, Srihari Babu ALLA, Alfredo Olegario SAUCEDO, Avinash SEETHARAMAIAH, Jonnala Gadda NAGENDRA KUMAR
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Patent number: 12067666Abstract: Aspects presented herein relate to methods and devices for graphics processing including an apparatus, e.g., a GPU. The apparatus may receive a set of draw call instructions corresponding to a graphics workload, where the set of draw call instructions is associated with at least one run-time parameter. The apparatus may also obtain a first shader program associated with storing data in a system memory and at least one second shader program associated with storing data in a constant memory. Further, the apparatus may execute the first shader program or the at least one second shader program based on whether the at least one run-time parameter is less than or equal to a size of the constant memory. The apparatus may also update or maintain a configuration of a shader processor or a streaming processor based on executing the first shader program or the at least one second shader program.Type: GrantFiled: May 18, 2022Date of Patent: August 20, 2024Assignee: QUALCOMM IncorporatedInventors: Yun Du, Eric Demers, Andrew Evan Gruber, Chun Yu, Chihong Zhang, Baoguang Yang, Yuehai Du, Gang Zhong, Avinash Seetharamaiah, Jonnala Gadda Nagendra Kumar
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Patent number: 11978151Abstract: Aspects presented herein relate to methods and devices for graphics processing including an apparatus, e.g., a GPU. The apparatus may obtain an indication of a BVH structure including a plurality of nodes, wherein the BVH structure is associated with geometry data for a plurality of primitives in a scene, wherein each of the plurality of nodes is associated with one or more primitives, where a first level BVH includes a set of first nodes and a second level BVH includes a set of second nodes. The apparatus may also allocate information for a plurality of second nodes in the set of second nodes to at least one first node in the set of first nodes. Further, the apparatus may store the allocated information for the plurality of second nodes in the set of second nodes in the at least one first node in the set of first nodes.Type: GrantFiled: August 31, 2022Date of Patent: May 7, 2024Assignee: QUALCOMM IncorporatedInventors: Adimulam Ramesh Babu, Srihari Babu Alla, Avinash Seetharamaiah, Jonnala Gadda Nagendra Kumar
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Publication number: 20240070964Abstract: Aspects presented herein relate to methods and devices for graphics processing including an apparatus, e.g., a GPU. The apparatus may obtain an indication of a BVH structure including a plurality of nodes, wherein the BVH structure is associated with geometry data for a plurality of primitives in a scene, wherein each of the plurality of nodes is associated with one or more primitives, where a first level BVH includes a set of first nodes and a second level BVH includes a set of second nodes. The apparatus may also allocate information for a plurality of second nodes in the set of second nodes to at least one first node in the set of first nodes. Further, the apparatus may store the allocated information for the plurality of second nodes in the set of second nodes in the at least one first node in the set of first nodes.Type: ApplicationFiled: August 31, 2022Publication date: February 29, 2024Inventors: Adimulam RAMESH BABU, Srihari Babu ALLA, Avinash SEETHARAMAIAH, Jonnala Gadda NAGENDRA KUMAR
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Publication number: 20240046543Abstract: This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for runtime optimization of the shader execution flow. A graphics processor may obtain instruction execution data associated with a graphics workload, the instruction execution data including graphics data for a set of shader operations. The graphics processor may configure, at a first iteration, at least one predication value based on the instruction execution data including the graphics data for the set of shader operations. The graphics processor may adjust, at a second iteration, an execution flow of the graphics workload based on the configured at least one predication value, the execution flow of the graphics workload including the set of shader operations. The graphics processor may execute or refrain from executing, at the second iteration, each of the set of shader operations based on the adjusted execution flow of the graphics workload.Type: ApplicationFiled: August 5, 2022Publication date: February 8, 2024Inventors: Yun DU, Eric DEMERS, Andrew Evan GRUBER, Chun YU, Baoguang YANG, Chihong ZHANG, Yuehai DU, Avinash SEETHARAMAIAH, Jonnala Gadda NAGENDRA KUMAR, Gang ZHONG, Zilin YING, Fei WEI
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Patent number: 11893677Abstract: Systems and techniques are provided for widening a hierarchical structure for ray tracing. For instance, a process can include obtaining a plurality of primitives of a scene object included in a first hierarchical acceleration data structure and determining one or more candidate hierarchical acceleration data structures each including the plurality of primitives. A cost metric can be determined for the one or more candidate hierarchical acceleration data structures and, based on the cost metric, a compressibility prediction associated with a candidate hierarchical acceleration data structure of the one or more candidate hierarchical acceleration data structures can be determined. An output hierarchical acceleration data structure can be generated based on the compressibility prediction.Type: GrantFiled: July 29, 2022Date of Patent: February 6, 2024Assignee: QUALCOMM IncorporatedInventors: Adimulam Ramesh Babu, Srihari Babu Alla, Avinash Seetharamaiah, Jonnala Gadda Nagendra Kumar, David Kirk McAllister
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Publication number: 20240037840Abstract: Systems and techniques are provided for widening a hierarchical structure for ray tracing. For instance, a process can include obtaining a plurality of primitives of a scene object included in a first hierarchical acceleration data structure and determining one or more candidate hierarchical acceleration data structures each including the plurality of primitives. A cost metric can be determined for the one or more candidate hierarchical acceleration data structures and, based on the cost metric, a compressibility prediction associated with a candidate hierarchical acceleration data structure of the one or more candidate hierarchical acceleration data structures can be determined. An output hierarchical acceleration data structure can be generated based on the compressibility prediction.Type: ApplicationFiled: July 29, 2022Publication date: February 1, 2024Inventors: Adimulam RAMESH BABU, Srihari Babu ALLA, Avinash SEETHARAMAIAH, Jonnala Gadda NAGENDRA KUMAR, David Kirk MCALLISTER
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Publication number: 20230377240Abstract: Aspects presented herein relate to methods and devices for graphics processing including an apparatus, e.g., a GPU. The apparatus may receive a set of draw call instructions corresponding to a graphics workload, where the set of draw call instructions is associated with at least one run-time parameter. The apparatus may also obtain a first shader program associated with storing data in a system memory and at least one second shader program associated with storing data in a constant memory. Further, the apparatus may execute the first shader program or the at least one second shader program based on whether the at least one run-time parameter is less than or equal to a size of the constant memory. The apparatus may also update or maintain a configuration of a shader processor or a streaming processor based on executing the first shader program or the at least one second shader program.Type: ApplicationFiled: May 18, 2022Publication date: November 23, 2023Inventors: Yun DU, Eric DEMERS, Andrew Evan GRUBER, Chun YU, Chihong ZHANG, Baoguang YANG, Yuehai DU, Gang ZHONG, Avinash SEETHARAMAIAH, Jonnala Gadda NAGENDRA KUMAR
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Publication number: 20230343016Abstract: The present disclosure relates to graphics processing. An apparatus of the present disclosure may determine visibility streams corresponding to a target and a set of bins into which the target is divided. The apparatus may select one of a first rendering mode or a second rendering mode for the target based on the first visibility stream and based on the set of second visibility streams. When the first rendering mode is select, the apparatus may configure each of the set of bins into a first subset associated with a first type of rendering pass or a second subset associated with a second type of rendering pass. The apparatus may then render the target based on the selected one of the first rendering mode or the second rendering mode and, if applicable, based on the first rendering pass type or the second rendering pass type.Type: ApplicationFiled: November 18, 2020Publication date: October 26, 2023Inventors: Srihari Babu ALLA, Jonnala Gadda NAGENDRA KUMAR, Avinash SEETHARAMAIAH, Andrew Evan GRUBER, Thomas Edwin FRISINGER, Richard HAMMERSTONE, Bo DU, Yongjun XU
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Patent number: 11727631Abstract: Aspects presented herein relate to methods and devices for graphics processing including an apparatus, e.g., a GPU. The apparatus may perform a color analysis on at least one first frame of a plurality of frames, the color analysis being performed based on at least one image in the at least one first frame. The apparatus may also generate a frequency map for at least one second frame of the plurality of frames based on the performed color analysis. Further, the apparatus may render the at least one second frame based on the frequency map for the at least one second frame, the at least one second frame being rendered after the at least one first frame.Type: GrantFiled: September 22, 2021Date of Patent: August 15, 2023Assignee: QUALCOMM IncorporatedInventors: Matthew Netsch, Srihari Babu Alla, Avinash Seetharamaiah, Jonnala Gadda Nagendra Kumar
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Publication number: 20230086288Abstract: Aspects presented herein relate to methods and devices for graphics processing including an apparatus, e.g., a GPU. The apparatus may perform a color analysis on at least one first frame of a plurality of frames, the color analysis being performed based on at least one image in the at least one first frame. The apparatus may also generate a frequency map for at least one second frame of the plurality of frames based on the performed color analysis. Further, the apparatus may render the at least one second frame based on the frequency map for the at least one second frame, the at least one second frame being rendered after the at least one first frame.Type: ApplicationFiled: September 22, 2021Publication date: March 23, 2023Inventors: Matthew NETSCH, Srihari Babu ALLA, Avinash SEETHARAMAIAH, Jonnala Gadda NAGENDRA KUMAR
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Patent number: 11373268Abstract: The present disclosure relates to methods and apparatus for hybrid rendering of video/graphics content by a graphics processing unit. The apparatus can configure the graphics processing unit of a display apparatus to perform multiple rendering passes for a frame of a scene to be displayed on a display device. Moreover, the apparatus can control the graphics processing unit to perform a first rendering pass of the multiple rendering passes to generate a first render target that is stored in either an on-chip graphics memory of the GPU or a system of the display apparatus. The apparatus can also control the graphics processing unit to perform a second rendering pass to generate a second render target that is alternatively stored in the system memory of the display apparatus or on-chip graphics memory of the GPU.Type: GrantFiled: September 30, 2020Date of Patent: June 28, 2022Assignee: QUALCOMM IncorporatedInventors: Srihari Babu Alla, Jonnala Gadda Nagendra Kumar, Avinash Seetharamaiah, Andrew Evan Gruber, Richard Hammerstone, Thomas Edwin Frisinger, Daniel Archard
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Patent number: 11321804Abstract: Methods, systems, and devices for graphics processer unit (GPU) operations are described. A device may monitor one or more states of a GPU during a duration. Based on monitoring the one or more GPU states, the device may determine an execution of a GPU command that is common to at least two GPU operations for clearing the GPU buffer. The device may determine whether the GPU clear command has previously been executed during a duration or a GPU cycle in which the device monitored the GPU states. The device may process the GPU clear command based on the determination of whether the GPU clear command has previously been executed. For example, the device may drop the GPU clear command based on the determination or modify a portion of the GPU clear command and execute at least the modified portion of the GPU clear command.Type: GrantFiled: October 15, 2020Date of Patent: May 3, 2022Assignee: QUALCOMM IncorporatedInventors: Thomas Edwin Frisinger, Richard Hammerstone, Jonnala Gadda Nagendra Kumar, Avinash Seetharamaiah, Shangmei Yu, Srihari Babu Alla
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Publication number: 20220122214Abstract: Methods, systems, and devices for graphics processer unit (GPU) operations are described. A device may monitor one or more states of a GPU during a duration. Based on monitoring the one or more GPU states, the device may determine an execution of a GPU command that is common to at least two GPU operations for clearing the GPU buffer. The device may determine whether the GPU clear command has previously been executed during a duration or a GPU cycle in which the device monitored the GPU states. The device may process the GPU clear command based on the determination of whether the GPU clear command has previously been executed. For example, the device may drop the GPU clear command based on the determination or modify a portion of the GPU clear command and execute at least the modified portion of the GPU clear command.Type: ApplicationFiled: October 15, 2020Publication date: April 21, 2022Inventors: Thomas Edwin Frisinger, Richard Hammerstone, Jonnala Gadda Nagendra Kumar, Avinash Seetharamaiah, Shangmei Yu, Srihari Babu Alla
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Publication number: 20220114284Abstract: Systems, methods, and computer-readable media are provided for signing and executing graphics processing unit (GPU) commands. In some examples, a method can include receiving, by a GPU, one or more commands including one or more verification signatures generated using a processor, each verification signature of the one or more verification signatures including a first value generated based on the one or more commands; generating, by the GPU, one or more additional verification signatures associated with the one or more commands, wherein each verification signature of the one or more additional verification signatures includes a second value generated by the GPU based on the one or more commands; and determining, by the GPU, a validity of the one or more commands based on a comparison of the one or more verification signatures and the one or more additional verification signatures.Type: ApplicationFiled: October 14, 2020Publication date: April 14, 2022Inventors: Avinash SEETHARAMAIAH, Murat BALCI, Jonnala Gadda NAGENDRA KUMAR, Nigel POOLE, Abhiraj DESHPANDE
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Publication number: 20220101479Abstract: The present disclosure relates to methods and apparatus for hybrid rendering of video/graphics content by a graphics processing unit. The apparatus can configure the graphics processing unit of a display apparatus to perform multiple rendering passes for a frame of a scene to be displayed on a display device. Moreover, the apparatus can control the graphics processing unit to perform a first rendering pass of the multiple rendering passes to generate a first render target that is stored in either an on-chip graphics memory of the GPU or a system of the display apparatus. The apparatus can also control the graphics processing unit to perform a second rendering pass to generate a second render target that is alternatively stored in the system memory of the display apparatus or on-chip graphics memory of the GPU.Type: ApplicationFiled: September 30, 2020Publication date: March 31, 2022Inventors: Srihari Babu ALLA, Jonnala Gadda NAGENDRA KUMAR, Avinash SEETHARAMAIAH, Andrew Evan GRUBER, Richard HAMMERSTONE, Thomas Edwin FRISINGER, Daniel ARCHARD