Patents by Inventor Avner Dor
Avner Dor has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240137048Abstract: A soft-decision decoding computes a first syndrome polynomial in accordance with a received word, computes a second syndrome polynomial by multiplying the first syndrome polynomial by a locator polynomial based on locations of erasures within the received word, finds a basis and private solution to an affine space of polynomials that solve key equations based on the second syndrome polynomial, determines a weak set of a locations of symbols in the received word with confidence below a certain confidence level, computes a matrix from the basis, the private solution and the weak set, determines sub-matrices in the matrix whose rank is equal to a rank of the matrix, determines error locator polynomial (ELP) candidates from the sub-matrices, the basis, and the private solution, and corrects the received word using a selected one of the ELP candidates.Type: ApplicationFiled: October 11, 2022Publication date: April 25, 2024Inventors: Avner DOR, Yaron SHANY, Ariel DOUBCHAK, Amit BERMAN
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Patent number: 11942965Abstract: A soft-decision decoding computes a first syndrome polynomial in accordance with a received word, computes a second syndrome polynomial by multiplying the first syndrome polynomial by a locator polynomial based on locations of erasures within the received word, finds a basis and private solution to an affine space of polynomials that solve key equations based on the second syndrome polynomial, determines a weak set of a locations of symbols in the received word with confidence below a certain confidence level, computes a matrix from the basis, the private solution and the weak set, determines sub-matrices in the matrix whose rank is equal to a rank of the matrix, determines error locator polynomial (ELP) candidates from the sub-matrices, the basis, and the private solution, and corrects the received word using a selected one of the ELP candidates.Type: GrantFiled: October 11, 2022Date of Patent: March 26, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Avner Dor, Yaron Shany, Ariel Doubchak, Amit Berman
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Patent number: 11855658Abstract: A processing circuit is configured to: construct a first locator polynomial for a Reed-Solomon codeword to identify locations of erasures in the Reed-Solomon codeword; determine a first syndrome of the Reed-Solomon codeword; calculate a first error evaluator polynomial from the first syndrome and the first locator polynomial; and perform error detection based on the first error evaluator polynomial to determine presence of errors in the Reed-Solomon codeword. When presence of errors in the Reed-Solomon codeword is not detected in the error detection, the processing circuit bypasses updating the first locator polynomial and proceeds to completing decoding of the Reed-Solomon codeword, but when presence of errors in the Reed-Solomon codeword is detected in the error detection, the system first updates the first locator polynomial to a second locator polynomial in a process with reduced complexity compared to the common one, before completing decoding of the Reed-Solomon codeword.Type: GrantFiled: August 5, 2022Date of Patent: December 26, 2023Inventors: Amit Berman, Avner Dor, Yaron Shany, Ilya Shapir, Ariel Doubchak
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Publication number: 20230370090Abstract: A method of correcting data stored in a memory device includes: applying an iterative decoder to the data; determining a total number of rows in first data the decoder attempted to correct; estimating first visible error rows among the total number that continue to have an error after the attempt; estimating residual error rows among the total number that no longer have an error after the attempt; determining second visible error rows in second data of the decoder that continue to have an error by permuting indices of the residual error rows according to a permutation; and correcting the first data using the first visible error rows.Type: ApplicationFiled: July 25, 2023Publication date: November 16, 2023Inventors: Ariel DOUBCHAK, Avner DOR, Yaron SHANY, Tal PHILOSOF, Yoav SHERESHEVSKI, Amit BERMAN
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Publication number: 20230308115Abstract: A method of correcting data stored in a memory device includes: applying an iterative decoder to the data; determining a total number of rows in first data the decoder attempted to correct; estimating first visible error rows among the total number that continue to have an error after the attempt; estimating residual error rows among the total number that no longer have an error after the attempt; determining second visible error rows in second data of the decoder that continue to have an error by permuting indices of the residual error rows according to a permutation; and correcting the first data using the first visible error rows.Type: ApplicationFiled: March 28, 2022Publication date: September 28, 2023Inventors: Ariel DOUBCHAK, Avner Dor, Yaron Shany, Tal Philosof, Yoav Shereshevski, Amit Berman
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Patent number: 11750221Abstract: A method of correcting data stored in a memory device includes: applying an iterative decoder to the data; determining a total number of rows in first data the decoder attempted to correct; estimating first visible error rows among the total number that continue to have an error after the attempt; estimating residual error rows among the total number that no longer have an error after the attempt; determining second visible error rows in second data of the decoder that continue to have an error by permuting indices of the residual error rows according to a permutation; and correcting the first data using the first visible error rows.Type: GrantFiled: March 28, 2022Date of Patent: September 5, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ariel Doubchak, Avner Dor, Yaron Shany, Tal Philosof, Yoav Shereshevski, Amit Berman
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Publication number: 20230223958Abstract: A method for Bose-Chaudhuri-Hocquenghem (BCH) soft error decoding includes receiving a codeword x, wherein the received codeword x has ?=t+r errors for some r?1; computing a minimal monotone basis {?i(x)}1?i?r+1?F[x] of an affine space V={?(x)?F[x]:?(x)·S(x)=??(x) (mod x2t), ?(0)=1, deg(?(x)?t+r}, wherein ?(x) is an error locator polynomial and S(x) is a syndrome; computing a matrix A?(?j(?i))i?[w],j?[r+1], wherein W={?1, . . . , ?w} is a set of weak bits in x; constructing a submatrix of r+1 rows from sub matrices of r+1 rows of the subsets of A such that the last column is a linear combination of the other columns; forming a candidate error locating polynomial using coefficients of the minimal monotone basis that result from the constructed submatrix; performing a fast Chien search to verify the candidate error locating polynomial; and flipping channel hard decision at error locations found in the candidate error locating polynomial.Type: ApplicationFiled: January 7, 2022Publication date: July 13, 2023Inventors: Avner Dor, Yaron Shany, Ariel Doubchak, Amit Berman
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Patent number: 11689221Abstract: A method for Bose-Chaudhuri-Hocquenghem (BCH) soft error decoding includes receiving a codeword x, wherein the received codeword x has ?=t+r errors for some r?1; computing a minimal monotone basis {?i(x)}1?i?r+1?F[x] of an affine space V={?(x)?F[x]: ?(x)·S(x)=??(x) (mod x2t), ?(0)=1, deg(?(x)?t+r}, wherein ?(x) is an error locator polynomial and S(x) is a syndrome; computing a matrix A?(?j?i))i?[W],j?[r+1], wherein W={?i, . . . , ?W} is a set of weak bits in x; constructing a submatrix of r+1 rows from sub matrices of r+1 rows of the subsets of A such that the last column is a linear combination of the other columns; forming a candidate error locating polynomial using coefficients of the minimal monotone basis that result from the constructed submatrix; performing a fast Chien search to verify the candidate error locating polynomial; and flipping channel hard decision at error locations found in the candidate error locating polynomial.Type: GrantFiled: January 7, 2022Date of Patent: June 27, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Avner Dor, Yaron Shany, Ariel Doubchak, Amit Berman
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Patent number: 11438013Abstract: A method of performing division operations in an error correction code includes the steps of receiving an output ??F†{0} wherein F=GF(2r) is a Galois field of 2r elements, ?=?0?i?r?1?i×?i wherein ? is a fixed primitive element of F, and ?i?GF(2), wherein K=GF(2s) is a subfield of F, and {1, ?} is a basis of F in a linear subspace of K; choosing a primitive element ??K, wherein ?=?1+?×?2, ?1=?0?i?s?1 ?i×?i?K, ?2=?0?i?s?1 ?i+s×?i?K, and ?=[?0, . . . , ?r?1]T?GF(2)r; accessing a first table with ?1 to obtain ?3=?1?1, computing ?2×?3 in field K, accessing a second table with ?2=?3 to obtain (1+?×?2×?3)?1=?4+?×?5, wherein ??1=(?1×(1+?×?2×?3))?1=?3×(?4+?×?5)=?3×?4+?×?3×?5; and computing products ?3×?4 and ?3×?5 to obtain ??1=?0?i?s?1?i×?i+?·?i?i?s?1?i+s=?i where ?i?GF(2).Type: GrantFiled: July 15, 2020Date of Patent: September 6, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Avner Dor, Amit Berman, Ariel Doubchak, Elik Almog Sheffi, Yaron Shany
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Publication number: 20220021401Abstract: A method of performing division operations in an error correction code includes the steps of receiving an output ??F†{0} wherein F=GF(2r) is a Galois field of 2r elements, ?=?0?i?r?1?i×?i wherein ? is a fixed primitive element of F, and ?i?GF(2), wherein K=GF(2s) is a subfield of F, and {1, ?} is a basis of F in a linear subspace of K; choosing a primitive element ??K, wherein ?=?1+?×?2, ?1=?0?i?s?1?i×?i?K, ?2=?0?i?s?1?i+s×?i?K, and ?=[?0, . . . , ?r?1]T?GF(2)r; accessing a first table with ?1 to obtain ?3=?1?1, computing ?2×?3 in field K, accessing a second table with ?2=?3 to obtain (1+?×?2×?3)?1=?4+?×?5, wherein ??1=(?1×(1+?×?2×?3))?1=?3×(?4+?×?5)=?3×?4+?×?3×?5; and computing products ?3×?4 and ?3×?5 to obtain ??1=?0?i?s?1?i×?i+?·?i?i?s?1?i+s=?i where ?i?GF(2).Type: ApplicationFiled: July 15, 2020Publication date: January 20, 2022Inventors: AVNER DOR, Amit Berman, Ariel Doubchak, Elik Almog Sheffi, Yaron Shany
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Publication number: 20210376859Abstract: Systems and methods are described for low power error correction coding (ECC) for embedded universal flash storage (eUFS) are described. The systems and methods may include identifying a first element of an algebraic field; generating a plurality of lookup tables for multiplying the first element; multiplying the first element by a plurality of additional elements of the algebraic field, wherein the multiplication for each of the additional elements is performed using an element from each of the lookup tables; and encoding information according to an ECC scheme based on the multiplication.Type: ApplicationFiled: May 28, 2020Publication date: December 2, 2021Inventors: AVNER DOR, Amit Berman, Ariel Doubchak
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Patent number: 11184029Abstract: Systems and methods are described for low power error correction coding (ECC) for embedded universal flash storage (eUFS) are described. The systems and methods may include identifying a first element of an algebraic field; generating a plurality of lookup tables for multiplying the first element; multiplying the first element by a plurality of additional elements of the algebraic field, wherein the multiplication for each of the additional elements is performed using an element from each of the lookup tables; and encoding information according to an ECC scheme based on the multiplication.Type: GrantFiled: May 28, 2020Date of Patent: November 23, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Avner Dor, Amit Berman, Ariel Doubchak
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Patent number: 11031956Abstract: A method for storing data within a memory device includes receiving data to be stored. The received data is encoded. The encoded data is stored within the memory device. Encoding the received data includes encoding the data into two or more sub-codewords. Each of the two or more sub-codewords includes a plurality of outer codewords. Two or more of the plurality of outer codewords are grouped to form a larger codeword that is larger than each of the plurality of outer codewords and the larger codeword is constructed to correct errors and/or erasures that are not correctable by the plurality of outer codewords, individually.Type: GrantFiled: June 25, 2019Date of Patent: June 8, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Amit Berman, Ariel Doubchak, Avner Dor
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Publication number: 20200412386Abstract: A method for storing data within a memory device includes receiving data to be stored. The received data is encoded. The encoded data is stored within the memory device. Encoding the received data includes encoding the data into two or more sub-codewords. Each of the two or more sub-codewords includes a plurality of outer codewords. Two or more of the plurality of outer codewords are grouped to form a larger codeword that is larger than each of the plurality of outer codewords and the larger codeword is constructed to correct errors and/or erasures that are not correctable by the plurality of outer codewords, individually.Type: ApplicationFiled: June 25, 2019Publication date: December 31, 2020Inventors: AMIT BERMAN, ARIEL DOUBCHAK, AVNER DOR
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Patent number: 10606760Abstract: A memory system includes a nonvolatile memory device having a plurality of physical sectors, a mapping table, and a memory controller including a plurality of hash functions. The memory controller is configured to access the physical sectors using the mapping table and the hash functions. The memory controller is configured to receive a sequence of logical block addresses (LBAs) from a host and logical sector data for each of the LBAs, generate a first virtual address by operating a selected hash function among the hash functions on a first logical block address (LBA) among the sequence, compress the logical sector data to generate compressed data, and store the compressed data in a first physical sector among the physical sectors that is associated with the first virtual address.Type: GrantFiled: August 23, 2017Date of Patent: March 31, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Elona Erez, Avner Dor, Moshe Twitto, Jun Jin Kong
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Patent number: 10528466Abstract: A method of operating a storage device including a nonvolatile memory can be provided by receiving, from a host, address change information including changing logical addresses for data to be stored in the nonvolatile memory. Physical addresses can be sequentially allocated to the changing logical addresses included in the address change information to provide a first journal. A portion of at least one physical address allocated to the changing logical addresses can be removed to provide a second journal and the second journal can be stored in the nonvolatile memory.Type: GrantFiled: June 7, 2018Date of Patent: January 7, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jong-Won Lee, Dashevsky Shmuel, Moshe Twitto, Elona Erez, Eran Hof, Jun-Jin Kong, Avner Dor, Michael Erlihson
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Patent number: 10387254Abstract: A method of encoding generalized concatenated error-correcting codes includes providing a parity matrix {tilde over (H)}j of a j-th layer code and predefined syndrome {tilde over (s)} of length n?{tilde over (k)}j, where the first n-kl coordinates are zero, n is a length of a codeword c of a first layer BCH code Cl of dimension {tilde over (k)}j, codeword c satisfies {tilde over (H)}jc={tilde over (s)}, a first layer code includes only a BCH code, and each subsequent layer includes a Reed-Solomon (RS) stage followed by a BCH code; finding a square matrix R, of dimension (n?{tilde over (k)}j)(n?{tilde over (k)}j) such that Rj{tilde over (H)}j=(A|I), where A is an arbitrary matrix, Rj=(Qj|Tj), where Q has n?kl columns Tj and has k1?{tilde over (k)}j columns; finding a vector c?(a b) where a is a vector of length {tilde over (k)}j and b is a vector of length n?{tilde over (k)}j; and solving ( A | I ) ? ( a b ) = ( Q j | T j ) ? s ~ = T j ? s ? ? where ? ? a = 0 ?Type: GrantFiled: October 12, 2017Date of Patent: August 20, 2019Assignee: SAMSUNG ELECTRONICS CO, LTD.Inventors: Moshe Twitto, Yaron Shany, Avner Dor, Elona Erez, Jun Jin Kong
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Patent number: 10333554Abstract: A method for generating a binary GTP codeword, comprised of N structure stages and each stage comprises at least one BCH codeword with error correction capability greater than a prior stage and smaller than a next stage, includes: receiving a syndrome vector s of a new stage 0 binary BCH codeword y over a field GF(2m) that comprises ?t syndromes of length m bits, wherein the syndrome vector s comprises l-th Reed-Solomon (RS) symbols of ?t RS codewords whose information symbols are delta syndromes of all BCH codewords from stage 0 until stage n?1; and multiplying s by a right submatrix ? of a matrix U, wherein U is an inverse of a parity matrix of an BCH code defined by tn, wherein the new binary BCH codeword is y=?·s.Type: GrantFiled: June 30, 2017Date of Patent: June 25, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Moshe Twitto, Moshe Ben Ari, Avner Dor, Elona Erez, Jun Jin Kong, Yaron Shany
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Patent number: 10289561Abstract: A method of controlling a nonvolatile memory device includes: receiving a plurality of logical pages associated with a plurality of physical addresses, respectively; storing the plurality of logical pages at the plurality of physical addresses in a selected one of a plurality of sub-clusters according to a given order of logical addresses of the logical pages; generating a first table including an entry for each one of the ordered logical addresses identifying a cluster of the selected sub-cluster and an offset into the selected sub-cluster; and generating a second table including an entry for the selected sub-cluster and the cluster indicating one of the ordered logical addresses associated with a first physical page of the selected sub-cluster.Type: GrantFiled: August 8, 2017Date of Patent: May 14, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Elona Erez, Avner Dor, Jun-Jin Kong
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Publication number: 20190114228Abstract: A method of encoding generalized concatenated error-correcting codes includes providing a parity Matrix {tilde over (H)}j of a j-th layer code and predefined syndrome {tilde over (s)} of length n?{tilde over (k)}j, where the first n?kl coordinates are zero, n is a length of a codeword c of a first layer BCH code Cl of dimension {tilde over (k)}j, codeword c satisfies {tilde over (H)}jc={tilde over (s)}, a first layer code includes only a BCH code, and each subsequent layer includes a Reed-Solomon (RS) stage followed by a BCH code; finding a square matrix Rj of dimension (n?{tilde over (k)}j)(n?{tilde over (k)}j) such that Rj{tilde over (H)}j=(A|I), where A is an arbitrary matrix, Rj=(Qj|Tj), where Q has n?kl columns and Tj has k1?{tilde over (k)} columns; finding a vector c=(a b) where a is a vector of length {tilde over (k)}j and b is a vector of length n?{tilde over (k)}j; and solving ( A | I ) ? ( a b ) = ( Q j | T j ) ? s ~ = T j ? s where a=0 and b=Tjs, and codType: ApplicationFiled: October 12, 2017Publication date: April 18, 2019Inventors: MOSHE TWITTO, YARON SHANY, AVNER DOR, ELONA EREZ, JUN JIN KONG