Abstract: A memory system includes a nonvolatile memory device having a plurality of physical sectors, a mapping table, and a memory controller including a plurality of hash functions. The memory controller is configured to access the physical sectors using the mapping table and the hash functions. The memory controller is configured to receive a sequence of logical block addresses (LBAs) from a host and logical sector data for each of the LBAs, generate a first virtual address by operating a selected hash function among the hash functions on a first logical block address (LBA) among the sequence, compress the logical sector data to generate compressed data, and store the compressed data in a first physical sector among the physical sectors that is associated with the first virtual address.

Abstract: A method of controlling a nonvolatile memory device includes: receiving a plurality of logical pages associated with a plurality of physical addresses, respectively; storing the plurality of logical pages at the plurality of physical addresses in a selected one of a plurality of sub-clusters according to a given order of logical addresses of the logical pages; generating a first table including an entry for each one of the ordered logical addresses identifying a cluster of the selected sub-cluster and an offset into the selected sub-cluster; and generating a second table including an entry for the selected sub-cluster and the cluster indicating one of the ordered logical addresses associated with a first physical page of the selected sub-cluster.

Abstract: A method for generating a binary GTP codeword, comprised of N structure stages and each stage comprises at least one BCH codeword with error correction capability greater than a prior stage and smaller than a next stage, includes: receiving a syndrome vector s of a new stage 0 binary BCH codeword y over a field GF(2m) that comprises ?t syndromes of length m bits, wherein the syndrome vector s comprises l-th Reed-Solomon (RS) symbols of ?t RS codewords whose information symbols are delta syndromes of all BCH codewords from stage 0 until stage n?1; and multiplying s by a right submatrix ? of a matrix U, wherein U is an inverse of a parity matrix of an BCH code defined by tn, wherein the new binary BCH codeword is y=?·s.

Abstract: A method of operating a storage device including a nonvolatile memory can be provided by receiving, from a host, address change information including changing logical addresses for data to be stored in the nonvolatile memory. Physical addresses can be sequentially allocated to the changing logical addresses included in the address change information to provide a first journal. A portion of at least one physical address allocated to the changing logical addresses can be removed to provide a second journal and the second journal can be stored in the nonvolatile memory.

Abstract: A flash memory device includes physical pages that store data sectors therein. The method of operating the flash memory device includes receiving write data sectors to be stored in the flash memory device, pairing the write data sectors with write data sectors and with written data sectors previously stored in physical pages of the flash memory device based upon a matching and deduplication operation to define data sector pairs and a difference therebetween, and rewriting to the physical pages of the flash memory device, in a partial-page writing mode, to store the difference between the write data sector and its respective paired data sector. The partial-page writing mode is performed on a respective physical page after a previous programming and before erasing. The written data sectors included in the data sector pairs only partially occupy the corresponding physical page of the flash memory device.

Abstract: A memory system includes a memory controller; and a memory device, the memory device including a memory cell array, the memory cell array including least a first memory page having a plurality of memory cells storing a plurality of stored bits, the memory controller being such that, the memory controller performs a first hard read operation on the first memory page to generate a plurality of read bits corresponding to the plurality of stored bits, and if the memory controller determines to change a value of one of a first group of bits, from among the plurality of read bits, the memory controller selects one of the first group of bits based on log likelihood ratio (LLR) values corresponding, respectively, to each of the first group of bits, and changes the value of the selected bit.

Abstract: A method, executed by a processor, for determining similarity between messages includes calculating a syndrome of each of first and second messages with respect to a linear code. A difference between the syndromes of the first and second messages is calculated, and a vector that minimizes a metric in a coset defined by the syndrome difference is identified. A compact representation of the second message that is based upon the first message is generated when a metric of the identified vector is less than or equal to a predetermined threshold. The compact representation of the second message is stored in a location of a memory device assigned for storing the second message, when the metric of the identified vector is less than or equal to the predetermined threshold.

Abstract: A flash memory device includes physical pages that store data sectors therein. The method of operating the flash memory device includes receiving write data sectors to be stored in the flash memory device, pairing the write data sectors with write data sectors and with written data sectors previously stored in physical pages of the flash memory device based upon a matching and deduplication operation to define data sector pairs and a difference therebetween, and rewriting to the physical pages of the flash memory device, in a partial-page writing mode, to store the difference between the write data sector and its respective paired data sector. The partial-page writing mode is performed on a respective physical page after a previous programming and before erasing. The written data sectors included in the data sector pairs only partially occupy the corresponding physical page of the flash memory device.

Abstract: A data storage device includes a flash memory that includes blocks of physical pages that include physical sectors configured to store data therein. A memory control unit, including a flash translation layer (FTL), is configured to receive write data sectors to be stored in the flash memory, determine at least one matched data sector by matching a write data sector with a reference data sector based upon a deduplication operation, and store the reference data sector corresponding to the matched data sector in a physical sector of a physical page of a block in the flash memory. Logical-to-physical addresses of the reference data sector and the corresponding matched data sector are mapped in the FTL, and physical-to-logical information regarding the corresponding matched data sector is written in a designated physical-to-logical information area of the flash memory.

Abstract: A method, executed by a processor, for determining similarity between messages includes calculating a syndrome of each of first and second messages with respect to a linear code. A difference between the syndromes of the first and second messages is calculated, and a vector that minimizes a metric in a coset defined by the syndrome difference is identified. A compact representation of the second message that is based upon the first message is generated when a metric of the identified vector is less than or equal to a predetermined threshold. The compact representation of the second message is stored in a location of a memory device assigned for storing the second message, when the metric of the identified vector is less than or equal to the predetermined threshold.

Abstract: A memory system includes a memory controller; and a memory device, the memory device including a memory cell array, the memory cell array including least a first memory page having a plurality of memory cells storing a plurality of stored bits, the memory controller being such that, the memory controller performs a first hard read operation on the first memory page to generate a plurality of read bits corresponding to the plurality of stored bits, and if the memory controller determines to change a value of one of a first group of bits, from among the plurality of read bits, the memory controller selects one of the first group of bits based on log likelihood ratio (LLR) values corresponding, respectively, to each of the first group of bits, and changes the value of the selected bit.

Abstract: Systems and methods of determining a similarity between data units in a nonvolatile memory are disclosed. One method includes obtaining first and second data units and dividing the first and second data units into a first plurality of non-overlapping chunks of data and a second plurality of non-overlapping chunks of data. The method further includes determining a first plurality of values and a second plurality of values associated with the chunks, and determining a similarity between the first second data units based on the first plurality values and of the second plurality of values. In one example embodiment, a similarity between an incoming data unit and another data unit is determined based on the number of buckets storing an incoming index value and another index value associated with the another data unit. A plurality of buckets in a table is determined based on a selected plurality of hash values.

Abstract: Provided are a coding/decoding method for use in a multi-level memory system. The coding method includes searching for a set of symbols that may generate a forbidden pattern that is set initially from an input data stream, and sticking at least one bit included in the searched set of the symbols that may generate the forbidden pattern so as not to generate the forbidden pattern.

Abstract: At least one example embodiment discloses a method of controlling a nonvolatile memory device including a plurality of blocks, each block including a plurality of physical pages. The method includes receiving a plurality of logical pages associated with a first plurality of logical addresses, respectively, and writing the first plurality of logical pages to the plurality physical addresses according to an ascending order of the logical addresses of the first plurality of logical pages.

Abstract: A method for protecting encoded data from algebraic manipulation includes receiving a data word s?Kd to be protected, randomly selecting two integers a ?{0, . . . , q?1} and b ?{0, . . . , ?q?1}, finding a point (?, ?) on a Hermitian curve over a field Fq that corresponds to the randomly selected integers (a, b) from a mapping (a, b)(?, ?)=(ua, ua?q+1z+vb), where u a := { 0 if ? ? a = 0 , ? 1 a - 1 otherwise , ? V b := { 0 if ? ? b = 0 , ? 2 b - 1 otherwise , and z is an element of the field Fq of unit trace, and where ?1 is a fixed primitive element of the field Fq and ?2 is a primitive element of a field F?q?Fq, and calculating a sum fs(?, ?)=?id+1?jd+1+?k=1d?ik?kjk for a set of d+1 integers pairs I ={(ik,jk)}k=1d+1, where the encoded word is a triple (s, (?, ?),fs(?, ?)).

Abstract: Example embodiments disclose methods and apparatuses for encoding and decoding data in a memory system. In an encoding method according to an example embodiment of inventive concepts, a codeword is generated based on a combination of data to be stored and auxiliary data according to stuck cells and an encoding matrix based on information regarding coordinates of the stuck cells and values of the stuck cells. The generated codeword includes data corresponding to the values of the stuck cells at addresses corresponding to the coordinates of the stuck cells. In a decoding method according to an example embodiment of inventive concepts, data may be generated by multiplying an inverse matrix of the encoding matrix used for encoding by the codeword.

Abstract: A method of processing data using a memory controller includes determining at least one cell state to which each of a plurality of multi-level cells can be changed to based on a current cell state of each multi-level cell, where each multi-level cell includes a plurality of data pages; determining one of the data pages as having a stuck bit when a value of the data page has a single mapping value based on mapping values mapped to the at least one cell state and generating stuck bit data regarding the stuck bit; and encoding write data to be stored in the multi-level cells based on the stuck bit data.

Abstract: At least one example embodiment discloses a method of controlling a nonvolatile memory device including a plurality of blocks, each block including a plurality of physical pages. The method includes receiving a plurality of logical pages associated with a first plurality of logical addresses, respectively, and writing the first plurality of logical pages to the plurality physical addresses according to an ascending order of the logical addresses of the first plurality of logical pages.

Abstract: At least one example embodiment discloses a method of determining a similarity in a nonvolatile memory. The method includes obtaining first data and second data units, the first data unit divided into a first plurality of non-overlapping chunks of data and the second data unit divided into a second plurality of non-overlapping chunks of data, determining a first plurality of values associated with the first plurality of chunks and a second plurality of values associated with the second plurality of chunks and determining a similarity between the first data unit and the second data unit based on whether any of the first plurality of values equals any of the second plurality of values.

Abstract: A method of programming a non-volatile memory device includes; defining a set of verification voltages, setting a maximum verification voltage among verification voltages that are less than or equal to a first target programming voltage to be a target verification voltage, calculating a number of extra pulses based on the target verification voltage and the first target programming voltage, verifying whether a threshold voltage of the memory cell is equal to or greater than the target verification voltage by applying an incremental step pulse program (ISPP) pulse to the memory cell and then applying at least one verification voltage in the set of verification voltages to the memory cell, and further applying the ISPP pulse to the memory cell a number of times equal to the number of extra pulses when the threshold voltage is verified to be equal to or greater than the target verification voltage.