Abstract: A method for data storage includes providing at least first and second readout configurations for reading storage values from analog memory cells, such that the first readout configuration reads the storage values with a first sense time and the second readout configuration reads the storage values with a second sense time, shorter than the first sense time. A condition is evaluated with respect to a read operation that is to be performed over a group of the memory cells. One of the first and second readout configurations is selected responsively to the evaluated condition. The storage values are read from the group of the memory cells using the selected readout configuration.

Abstract: A method for data storage includes storing data in a group of analog memory cells by writing respective storage values into the memory cells in the group. One or more of the memory cells in the group are read using a first readout operation that senses the memory cells with a first sense time. At least one of the memory cells in the group is read using a second readout operation that senses the memory cells with a second sense time, longer than the first sense time. The data stored in the group of memory cells is reconstructed based on readout results of the first and second readout operations.

Abstract: Methods, apparatus and computer readable medium for handling error correction in a memory are disclosed. In some embodiments, after an attempt is made to write original data to a ‘target’ memory, data is read back from the target memory in a ‘first read operation’, thereby generating first read data. After the first read operation, the first read data is compared to the original data and/or an indication of a difference between the original data and the first data is determined. The information obtained by effecting the data-comparison and/or information related to the difference indication is used when correcting errors in data read back from the target memory in a ‘second read operation.’. The presently-disclosed teachings are applicable to any kind of memory including (i) non-volatile memories such as flash memory, magnetic memory and optical storage and (ii) volatile memory such as SRAM or DRAM.

Abstract: A method for data storage includes storing two or more data items in a non-volatile memory. Redundancy information is calculated over the data items, and the redundancy information is stored in a volatile memory. Upon a failure to retrieve a data item from the non-volatile memory, the data item is reconstructed from remaining data items stored in the non-volatile memory and from the redundancy information stored in the volatile memory.

Abstract: A data storage method includes, in a memory controller that accepts memory access commands from a host for execution in one or more memory units, holding a definition of a policy to be applied by the memory controller in the execution of the memory access commands in the memory units. The policy is reported from the memory controller to the host so as to cause the host to format memory access commands based on the reported policy.

Abstract: A method for data storage includes storing data in a memory including multiple analog memory cells arranged in blocks. A first subset of the blocks is defined for storing first data with a first storage density, and a second subset of the blocks is defined for storing second data with a second storage density, larger than the first storage density. In each of the first and second subsets, one or more blocks are allocated to serve as spare blocks and blocks that become faulty are replaced with the spare blocks. Upon detecting that a number of the spare blocks in the second subset has decreased below a predefined threshold, the data is copied from at least one block in the second subset to the first subset, and the at least one block is added to the spare blocks of the second subset.

Abstract: A data storage method includes identifying, in a set of data items associated with respective logical addresses for storage in a memory, a first subset of the logical addresses associated with the data items containing application data, and a second subset of the logical addresses associated with the data items containing parity information that has been calculated over the application data. The data items associated with the first identified subset are stored in one or more first physical memory areas of the memory, and the data items associated with the second identified subset are stored in one or more second physical memory areas of the memory, different from the first physical memory areas. A memory management task is performed independently in the first physical memory areas and in the second physical memory areas.

Abstract: A method executed by a circuit for counting electrons in storage cells in an array of at least two storage cells is provided. The method includes providing a storage array of at least two storage cells, and each of said at least two storage cells containing an unknown amount of electrons. A receiving array of at least two receiving cells is provided, where said at least two receiving cells initially contain no electrons. Then, extracting a layer of said electrons from said storage array of cells and inserting said layer into corresponding locations in said receiving array. The method then repeats said steps of extracting and inserting while at least one of said at least two storage cells is not empty. The method counts, for each said storage cell in said storage array, a productive-extraction amount.

Abstract: A computer system includes a hard disk drive, a processor coupled to the hard disk drive, and a cache interface coupled to the processor and detachably connectable to a cache memory. The processor is adapted, subsequent to an initial interrogation of the cache interface, to determine whether the cache memory is connected to the cache interface by inspecting an indication of the presence or the absence of the cache memory, the indication being stored in a register in the processor or in a memory associated with the processor such that the inspecting avoids repeat interrogation of the cache interface, to communicate with the cache memory and the hard disk drive such that the processor has access to the cache memory when the cache memory is connected to the cache interface, and to communicate with the hard disk drive when the cache memory is disconnected from the cache interface.

Abstract: Methods and systems for counting items in storage containers in an array of at least two storage containers, the method including the steps of: providing a storage array of at least two storage containers, each of the storage containers containing an unknown amount of items; providing a receiving array of at least two receiving containers, wherein the receiving containers initially contain no items; extracting a layer of the items from the storage array; inserting the layer into corresponding locations in the receiving array; repeating the steps of extracting and inserting while at least one of the storage containers is not empty; counting, for each storage container in the storage array, a productive-extraction amount; and reporting, for at least some of the storage containers, the productive-extraction amount from each storage container. Preferably, the method further includes recovering a storage identity upon recovery from a system failure that erases the productive-extraction amount.

Abstract: A flash memory device includes a flash memory residing on at least one flash memory die. The flash memory device also includes a flash controller residing on a flash controller die that is separate from the at least one flash memory die. The flash memory and the flash controller reside within, reside on, or are attached to a common housing. The flash controller is configured to execute at least one test program to test at least one flash memory die.

Abstract: A computerized system is booted from a flash memory device configured to always operate one or more of its blocks only in a M-bit-per-cell mode and the rest of its blocks in a N>M-bit-per-cell mode. When the system is powered up, an initialization program is retrieved from the M-bit-per-cell block(s), corrected for errors using a first error correction method, and executed. Data accessed subsequently from the N-bit-per-cell blocks are corrected using an error correction method that corrects more errors per block than the first error correction method.

Abstract: The present invention teaches the recycling of a faulty multi-die memory package by isolating the functional part of the package and using it as a smaller memory package.

Abstract: A memory card includes a non-volatile memory, a connector configured to enable the memory card to be operatively coupled to a host computer, and a housing enclosing the non-volatile memory. The housing has a customized physical contour that is determined according to a user-selected value.

Abstract: Embodiments of the present invention relate to an apparatus, method and computer readable medium for recovering from a failed or aborted outgoing data transfer operation from a host device to a peripheral storage device. In some embodiments, before the peripheral storage device is corrupted by the failed outgoing data transfer operation, one or more recovery data objects are stored on the host-side. After the peripheral storage device is corrupted by the failed data transfer, the host device responds to a subsequent coupling with the peripheral storage device by repairing the corrupted peripheral storage device using one or more of the host-side stored recovery data objects. Optionally, the host device also restores the outgoing aborted or failed data transfer operation.

Abstract: A card vending machine includes a storage area, wherein each of a plurality of memory cards to be issued by a respective one of at least two different issuers are stored. A security mechanism conditions access of each issuer to only a respective portion of the storage area upon authorization of this issuer. An interface mechanism is operated by a user to define a purchasing transaction and a controller is operative, in accordance with the interface mechanism, to customize a memory card at least in part according to the purchasing transaction.

Abstract: A flash memory device includes a flash memory residing on at least one flash memory die. The flash memory device also includes a flash controller residing on a flash controller die that is separate from the at least one flash memory die. The flash memory and the flash controller reside within, reside on, or are attached to a common housing. The flash controller is configured to execute at least one test program to test at least one flash memory die.

Abstract: Methods, systems and devices for testing flash memory dies are disclosed. According to some embodiments, during the post-wafer sort stage of device manufacture, a plurality of flash memory devices, each of which includes a flash controller die and at least one flash memory die associated with a common housing, are subjected to a testing process, for examples, a batch testing process or a mass testing process. During testing, a respective flash controller residing on a respective flash controller die executes at least one test program to test one or more respective flash memory dies of the respective flash device. A testing system including at least 100 of the flash memory devices and a mass-testing board is disclosed. Furthermore, flash memory devices where the flash controller is operative to test one or more of the flash memory dies are disclosed. Exemplary testing includes but is not limited to bad block testing.

Abstract: A method of sending data from a memory to a host, and a data storage device that uses the method. The controller of the data storage device sends the data directly from the memory to a buffer in an interface to the host while simultaneously checking the data for errors. If sufficiently few errors are found, the data are sent from the buffer to the host. Otherwise, the data are corrected, the data in the buffer are replaced with the corrected data, and the corrected data are written to the memory. If the data are stored by segments, the simultaneous sending and checking is effected segmentwise. When a bad segment is found, an error flag is set. When all the data have been sent and checked, or when the buffer is full, if the error flag has not been set, the data in the buffer are sent to the host.

Abstract: Methods, apparatus and computer readable medium for handling error correction in a memory are disclosed. In some embodiments, after an attempt is made to write original data to a ‘target’ memory, data is read back from the target memory in a ‘first read operation’, thereby generating first read data. After the first read operation, the first read data is compared to the original data and/or an indication of a difference between the original data and the first data is determined. The information obtained by effecting the data-comparison and/or information related to the difference indication is used when correcting errors in data read back from the target memory in a ‘second read operation.’. The presently-disclosed teachings are applicable to any kind of memory including (i) non-volatile memories such as flash memory, magnetic memory and optical storage and (ii) volatile memory such as SRAM or DRAM.