Abstract: Techniques for fabricating semiconductor structures and devices with stacked structures having embedded capacitors are disclosed. In one example, a semiconductor structure includes a substrate having a first region and a second region. The semiconductor structure further includes a capacitor structure disposed in the second region of the substrate. The capacitor structure includes a capacitor conductor and a dielectric insulator disposed between the capacitor conductor and the substrate. The semiconductor structure further includes a stacked device disposed on the first region of the substrate. The stacked device includes a first transistor and a second transistor. At least a portion of the second transistor is disposed under at least a portion of the first transistor. The first transistor and the second transistor are each coupled to the capacitor conductor.

Abstract: A semiconductor structure may include one or more metal gates, one or more channels below the one or more metal gates, a gate dielectric layer separating the one or more metal gates from the one or more channels, and a high-k material embedded in the gate dielectric layer. Both the high-k material and the gate dielectric layer may be in direct contact with the one or more channels. The high-k material may provide threshold voltage variation in the one or more metal gates. The high-k material is a first high-k material or a second high-k material. The semiconductor structure may only include the first high-k material embedded in the gate dielectric layer. The semiconductor structure may only include the second high-k material embedded in the gate dielectric layer. The semiconductor structure may include both the first high-k material and the second high-k material embedded in the gate dielectric layer.

Abstract: A method of manufacturing a vertical transistor device comprises forming a bottom source region on a semiconductor substrate, forming a channel region extending vertically from the bottom source region, forming a top drain region on an upper portion of the channel region, forming a first gate region having a first gate length around the channel region, and forming a second gate region over the first gate region and around the channel region, wherein the second gate region has a second gate length different from the first gate length, and wherein at least one dielectric layer is positioned between the first and second gate regions.

Abstract: A memory device is provided that includes at least one MTJ pillar which can have a ternary program state as compared to a binary program state in a conventional device. The MTJ pillar contains a lower MTJ structure that includes at least a first magnetic reference material, a first tunnel barrier and a first magnetic free layer material, and an upper MTJ structure that includes at least a second magnetic reference material, a second tunnel barrier and a second magnetic free layer material; the upper MTJ structure is stacked atop the lower MTJ structure. The first and second magnetic free layer materials have different designs and/or compositions resulting in different switching voltages.

Abstract: A circuit may include a memory cell. The memory cell may include a first memory element, a second memory element, a first transistor, and a second transistor. The first memory element may be connected to a bit line. The second memory element may be connected to a select line. The first transistor may be connected to a first word line. The second transistor may be connected to a second word line. The first memory element may be programmed by applying a first write voltage to the bit line, applying a second write voltage to the second word line, applying a first intermediate voltage to the select line, and applying a second intermediate voltage to the first word line. The select line may be connected to a high impedance. The first write voltage may be a positive supply voltage, the second write voltage may be a negative supply voltage.

Abstract: An embodiment of the invention may include a method of forming and a resulting multiply-and-accumulate device. The device may include a capacitor in a second region. The capacitor comprises a dielectric located between a first metal contact and a second metal contact. The device may include a stacked nanosheet device in the first region from the nanosheet. The stacked nanosheet device may include a top transistor and a bottom transistor in contact with the first metal contact. The device may include a nanosheet device in the third region, wherein a source/drain of a transistor of the nanosheet device is in contact with the first metal contact.

Abstract: Semiconductor channel layers vertically aligned and stacked, separated by a work function metal and a gate dielectric partially surrounding and physically separating the work function metal from each, a first portion of the work function metal directly contacts a vertical sidewall of each layer. A first set and a second set of semiconductor channel layers vertically aligned and stacked, separated by a work function metal, a gate dielectric partially surrounding and physically separating the work function metal from each, a first portion of the work function metal between the first set and the second set directly contacts a sidewall of each layer. Forming an initial stack of alternating layers of a sacrificial and a semiconductor channel vertically aligned and stacked, forming a vertical opening creating a first stack of nanosheet layers and a second stack of nanosheet layers, and exposing vertical side surfaces of the alternating layers of both stacks.

Abstract: A vertical bipolar junction transistor may include an intrinsic base epitaxially grown on a first emitter or collector, the intrinsic base being compositionally graded, a second collector or emitter formed on the intrinsic base, and an extrinsic base formed all-around the intrinsic base. The extrinsic base may be isolated from the first emitter or collector by a first spacer. The extrinsic base may be isolated from the second collector or emitter by a second spacer. The extrinsic base may have a larger bandgap than the intrinsic base. The intrinsic base may be doped with a p-type dopant, and the first emitter or collector, and the second collector or emitter may be doped with an n-type dopant. The first emitter or collector, the intrinsic base, and the second collector or emitter may be made of a III-V semiconductor material.

Abstract: An embodiment of the invention may include a semiconductor structure, method of use and method of manufacture. The structure may include a heating element located underneath a temperature-controlled portion of the device. A method of operating the semiconductor device may include providing current to a thin film heater located beneath a temperature-controlled region of the semiconductor device. The method may include performing temperature dependent operations in the temperature-controlled region.

Abstract: A method for manufacturing a semiconductor device includes forming a first vertical transistor on a semiconductor substrate, and forming a second vertical transistor stacked on the first vertical transistor. In the method, a silicide layer is formed on a first drain region of the first vertical transistor and on a second drain region of the second vertical transistor. The silicide layer electrically connects the first and second drain regions to each other.

Abstract: Semiconductor channel layers vertically aligned and stacked, separated by a work function metal and a gate dielectric partially surrounding and physically separating the work function metal from each, a first portion of the work function metal directly contacts a vertical sidewall of each layer. A first set and a second set of semiconductor channel layers vertically aligned and stacked, separated by a work function metal, a gate dielectric partially surrounding and physically separating the work function metal from each, a first portion of the work function metal between the first set and the second set directly contacts a sidewall of each layer. Forming an initial stack of alternating layers of a sacrificial and a semiconductor channel vertically aligned and stacked, forming a vertical opening creating a first stack of nanosheet layers and a second stack of nanosheet layers, and exposing vertical side surfaces of the alternating layers of both stacks.

Abstract: A memory network can be constructed with at least memory write weightings, memory read weightings and at least one read vector, the memory write weightings parameterizing memory write operations of a neural network to the memory matrix, the memory read weightings parameterizing memory read operations of the neural network from the memory matrix. At least one of the write weightings, the read weightings, or elements of the at least one read vector, can be initialized to have sparsity and/or low discrepancy sampling pattern. The memory network can be trained to perform a task.

Abstract: A circuit may include a low-voltage flash memory integrated with a vertical field effect transistor and a non-volatile memory element. The low-voltage flash memory may be coupled to the non-volatile memory element by the vertical field effect transistor, one or more bit-lines, and one or more word-lines. The low-voltage flash memory may provide a lower significance conductance and the non-volatile memory element may provide a higher significance conductance. The low-voltage flash memory may include a source and a drain. The source may be separated from the drain by an epitaxial channel. The low-voltage flash memory may include a floating gate. The floating gate may be separated from the epitaxial channel by a first dielectric layer. The low-voltage flash memory may include a control gate. The control gate may be separated from the floating gate by a second dielectric layer.

Abstract: A first vertical T-FET has a source heavily doped with a source concentration of a source-type dopant, a drain doped with a drain concentration of a drain-type dopant, and a channel between the source and drain. The source, channel, and drain are stacked vertically in a fin or pillar perpendicular to a substrate. A gate stack encompasses the channel sides and has a drain overlap amount overlapping the drain sides and a source overlap amount overlapping the source sides. External contacts electrically connect the gate and source and/or drain. The source-type dopant and the drain-type dopant are opposite dopant types. In some embodiments, a second vertical T-FET is stacked on the first vertical T-FET. Different VT-FET devices are made by changing the materials, doping types and levels, and connections to the sources, channels, and drains. Device characteristics are designed/changed by changing the amount of source and drain overlaps of the gate stack(s).

Abstract: A memory device, and a method of making the same, includes a resistive random-access memory element electrically connected to an extrinsic base region of a bipolar junction transistor, the extrinsic base region of the bipolar junction transistor consisting of an epitaxially grown material that forms the bottom electrode of the resistive random-access memory element. Additionally, a method of writing to the memory device includes applying a first voltage on a word line of the memory device to form a filament in the resistive random-access memory element. A second voltage including an opposite polarity to the first voltage can be applied to the word line to remove a portion of the filament in the resistive random-access memory element.

Abstract: A complementary circuit, including a logic unit which includes pull-up depletion-mode MOS transistors and pull-down depletion-mode MOS transistors and a level shifting circuit coupled to the logic unit.

Abstract: A memory device, and a method of making the same, includes a resistive random-access memory element electrically connected to an extrinsic base region of a bipolar junction transistor, the extrinsic base region of the bipolar junction transistor consisting of an epitaxially grown material that forms the bottom electrode of the resistive random-access memory element. Additionally, a method of writing to the memory device includes applying a first voltage on a word line of the memory device to form a filament in the resistive random-access memory element. A second voltage including an opposite polarity to the first voltage can be applied to the word line to remove a portion of the filament in the resistive random-access memory element.

Abstract: A circuit may include a memory cell. The memory cell may include a first memory element, a second memory element, a first transistor, and a second transistor. The first memory element may be connected to a bit line. The second memory element may be connected to a select line. The first transistor may be connected to a first word line. The second transistor may be connected to a second word line. The first memory element may be programmed by applying a first write voltage to the bit line, applying a second write voltage to the second word line, applying a first intermediate voltage to the select line, and applying a second intermediate voltage to the first word line. The select line may be connected to a high impedance. The first write voltage may be a positive supply voltage, the second write voltage may be a negative supply voltage.

Abstract: A structure including a bottom electrode, a phase change material layer vertically aligned and an ovonic threshold switching layer vertically aligned above the phase change material layer. A structure including a bottom electrode, a phase change material layer and an ovonic threshold switching layer vertically aligned above the phase change material layer, and a first barrier layer physically separating the ovonic threshold switching layer from a top electrode. A method including forming a structure including a liner vertically aligned above a first barrier layer, the first barrier layer vertically aligned above a phase change material layer, the phase change material layer vertically aligned above a bottom electrode, forming a dielectric surrounding the structure, and forming an ovonic threshold switching layer on the first barrier layer, vertical side surfaces of the first buffer layer are vertically aligned with the first buffer layer, the phase change material layer and the bottom electrode.

Abstract: A circuit structure includes a first ferroelectric field effect transistor (FeFET) having a first gate electrode, a first source electrode, and a first drain electrode and a second FeFET having a second gate electrode, a second source electrode, and a second drain electrode. The first gate electrode is connected to a wordline, and the first source electrode and the second source electrode are connected to a bitline. The first drain electrode is connected to the second gate electrode and the second drain electrode is connected to a bias line. A weight synapse structure is constructed by combining two circuit structures. A plurality of weight synapse structures are incorporated into a crossbar array.