Patents by Inventor Balaji Kannan

Balaji Kannan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210064070
    Abstract: In an example, a circuit includes a first power switch device coupled between a voltage input and an output terminal, the first power switch device having a control input. A voltage divider circuit includes a first resistor and a second resistor. The first resistor is coupled between the voltage input and a sense node between the first resistor and the second resistor. The second resistor has a first terminal coupled to the sense node and a second terminal. A second switch device is coupled between the second terminal of the second resistor and an electrical ground terminal. A voltage clamp is coupled between the sense node and the electrical ground terminal.
    Type: Application
    Filed: August 27, 2019
    Publication date: March 4, 2021
    Inventors: MICHAEL RYAN HANSCHKE, FILIPPO MARINO, SUNGLYONG KIM, TOBIN DANIEL HAGAN, RICHARD LEE VALLEY, BHARATH BALAJI KANNAN, SALVATORE GIOMBANCO, SEETHARAMAN SRIDHAR
  • Patent number: 10938641
    Abstract: Techniques for providing an on-demand development environment are described. A service of a provider network receives a request to launch a development environment, such as a notebook, from an electronic device. The service obtains an identification of a computing cluster hosted by the provider network. The service obtains an identification of a compute instance hosted within the provider network, the compute instance executing a software environment to host one or more development environments. The service causes the compute instance to launch a development environment. The service sends a message to configure the launched development environment to execute a computer program written in the development environment using the computing cluster. The service generates a token to secure communications between the electronic device and the development environment and sends the token to an originator of the request.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: March 2, 2021
    Assignee: Amazon Technologies, Inc.
    Inventors: Jonathan Andrew Fritz, Balaji Kannan, Nivetha Purusothaman, Parag Pramod Chaudhari, Jalpan Randeri, Yishan Yang, Udit Mehrotra, Sneha Bharadwaj, Rui Liu, Ajay Baliram Jadhav, Anoop Kochummen Johnson, Konstantin Milyutin, Vignesh Rajamani, Sachin Suresh Bhat, Anthony Virtuoso, Stefano Stefani, Rahul Pathak, Anurag Gupta, Ashok Kumar
  • Patent number: 10936000
    Abstract: In an example, a circuit includes a first power switch device coupled between a voltage input and an output terminal, the first power switch device having a control input. A voltage divider circuit includes a first resistor and a second resistor. The first resistor is coupled between the voltage input and a sense node between the first resistor and the second resistor. The second resistor has a first terminal coupled to the sense node and a second terminal. A second switch device is coupled between the second terminal of the second resistor and an electrical ground terminal. A voltage clamp is coupled between the sense node and the electrical ground terminal.
    Type: Grant
    Filed: August 27, 2019
    Date of Patent: March 2, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Michael Ryan Hanschke, Filippo Marino, Sunglyong Kim, Tobin Daniel Hagan, Richard Lee Valley, Bharath Balaji Kannan, Salvatore Giombanco, Seetharaman Sridhar
  • Patent number: 10911998
    Abstract: Mobile communication devices may use too much power and/or take too much time when camping on a particular mobile communication network. An apparatus may implement functions that may decrease power usage and/or decrease time usage. The apparatus may be a UE configured to measure energy levels for each frequency channel of a set of frequency channels in a frequency band to determine measured energy levels. The apparatus may also be configured to determining whether a first cell that operates using a first RAT is detected on a frequency channel of the set of frequency channels based on the measured energy levels. Additionally, the apparatus may be configured to search for a second cell that operates using a second RAT, when no cell for the first RAT is detected on the set of frequency channels, wherein the UE searches for the second cell using the measured energy levels.
    Type: Grant
    Filed: February 20, 2019
    Date of Patent: February 2, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Bapineedu Chowdary Gummadi, Manikantha Desetty, Balaji Kannan
  • Publication number: 20210006236
    Abstract: In some examples, a circuit includes an input circuit, an output circuit, an auxiliary circuit, and a balancing circuit. The input circuit comprises a primary capacitor coupled to primary windings of a transformer. The output circuit comprises a secondary capacitor coupled to secondary windings of the transformer, wherein the secondary windings are coupled to the primary windings. The auxiliary circuit comprises auxiliary windings coupled to the primary windings. The balancing circuit is coupled to the output circuit, the auxiliary circuit, and the input circuit. The balancing circuit is configured to balance a voltage across the primary capacitor with a voltage across the secondary capacitor.
    Type: Application
    Filed: June 18, 2020
    Publication date: January 7, 2021
    Inventors: Pei-Hsin Liu, Richard Lee Valley, Bharath Balaji Kannan
  • Publication number: 20200267611
    Abstract: Mobile communication devices may use too much power and/or take too much time when camping on a particular mobile communication network. An apparatus may implement functions that may decrease power usage and/or decrease time usage. The apparatus may be a UE configured to measure energy levels for each frequency channel of a set of frequency channels in a frequency band to determine measured energy levels. The apparatus may also be configured to determining whether a first cell that operates using a first RAT is detected on a frequency channel of the set of frequency channels based on the measured energy levels. Additionally, the apparatus may be configured to search for a second cell that operates using a second RAT, when no cell for the first RAT is detected on the set of frequency channels, wherein the UE searches for the second cell using the measured energy levels.
    Type: Application
    Filed: February 20, 2019
    Publication date: August 20, 2020
    Inventors: Bapineedu Chowdary GUMMADI, Manikantha DESETTY, Balaji KANNAN
  • Patent number: 10741668
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to replacement metal gate structures and methods of manufacture. The structure includes at least one short channel device including a dielectric material, a workfunction metal, and a capping material, and a long channel device comprising the dielectric material, the workfunction metal and fluorine free gate conductor material.
    Type: Grant
    Filed: July 19, 2017
    Date of Patent: August 11, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Bala Haran, Ruilong Xie, Balaji Kannan, Katsunori Onishi, Vimal K. Kamineni
  • Patent number: 10727133
    Abstract: A method of forming a gate structure with an undercut region includes, among other things, forming a plurality of fins above a substrate and an isolation structure above the substrate and between the plurality of fins, forming a placeholder gate structure above the plurality of fins in a first region and above the isolation structure in a second region, selectively removing a portion of the placeholder structure in the second region to define an undercut recess, forming a spacer structure adjacent the sacrificial gate structure, forming a dielectric layer adjacent the spacer structure and in the undercut recess, removing remaining portions of the placeholder gate structure to define a gate cavity, and forming a replacement gate structure in the gate cavity.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: July 28, 2020
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Qun Gao, Balaji Kannan, Shesh Mani Pandey, Haiting Wang
  • Patent number: 10658363
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a cut inside a replacement metal gate trench to mitigate n-p proximity effects and methods of manufacture. The structure described herein includes: a first device; a second device, adjacent to the first device; a dielectric material, of the first device and the second device, including a cut within a trench between the first device and the second device; and a common gate electrode shared with the first device and the second device, the common gate electrode provided over the dielectric material and contacting underlying material within the cut.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: May 19, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Balaji Kannan, Ayse M. Ozbek, Tao Chu, Bala Haran, Vishal Chhabra, Katsunori Onishi, Guowei Xu
  • Publication number: 20200127575
    Abstract: A system includes an isolated converter having a power transformer with a primary winding, a secondary winding, and an auxiliary winding. The system also includes: 1) a first switch coupled to the primary winding; 2) a switch controller coupled to the first switch; and 3) a bias power regulator circuit coupled to the auxiliary winding and the switch controller. The bias power regulator circuit includes a second switch. The bias power regulator circuit is configured to provide a bias supply output voltage to the switch controller based on a first set of modes that modulate a switching frequency of the second switch and based on a second mode in which the second switch stays off.
    Type: Application
    Filed: October 9, 2019
    Publication date: April 23, 2020
    Inventors: Pei-Hsin LIU, Richard Lee VALLEY, Bharath Balaji KANNAN
  • Publication number: 20200091005
    Abstract: A method of forming a gate structure with an undercut region includes, among other things, forming a plurality of fins above a substrate and an isolation structure above the substrate and between the plurality of fins, forming a placeholder gate structure above the plurality of fins in a first region and above the isolation structure in a second region, selectively removing a portion of the placeholder structure in the second region to define an undercut recess, forming a spacer structure adjacent the sacrificial gate structure, forming a dielectric layer adjacent the spacer structure and in the undercut recess, removing remaining portions of the placeholder gate structure to define a gate cavity, and forming a replacement gate structure in the gate cavity.
    Type: Application
    Filed: September 18, 2018
    Publication date: March 19, 2020
    Inventors: Qun Gao, Balaji Kannan, Shesh Mani Pandey, Haiting Wang
  • Publication number: 20200036293
    Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed for adaptive synchronous rectifier control. An example apparatus includes an adaptive off-time control circuit to determine a first voltage and a second voltage when a drain voltage of a switch satisfies a voltage threshold, the first voltage based on a first off-time of the switch, the second voltage based on the first off-time and a first scaling factor, determine a third voltage based on a second scaling factor and a second off-time of the switch, the second off-time after the first off-time, and determine a third off-time of the switch based on at least one of the second voltage or the third voltage. The example apparatus further includes a driver to turn off the switch for at least the third off-time after the second off-time.
    Type: Application
    Filed: August 1, 2018
    Publication date: January 30, 2020
    Inventors: Bharath Balaji Kannan, Bing Lu
  • Patent number: 10531367
    Abstract: Certain aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment may receive extended access barring (EAB) information indicating whether the UE is subject to EAB. The UE may output an indication of whether the UE is subject to EAB based at least in part on receiving the EAB information. Numerous other aspects are provided.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: January 7, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Bapineedu Chowdary Gummadi, Balaji Kannan, Venkata A Naidu Babbadi
  • Publication number: 20190393221
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a cut inside a replacement metal gate trench to mitigate n-p proximity effects and methods of manufacture. The structure described herein includes: a first device; a second device, adjacent to the first device; a dielectric material, of the first device and the second device, including a cut within a trench between the first device and the second device; and a common gate electrode shared with the first device and the second device, the common gate electrode provided over the dielectric material and contacting underlying material within the cut.
    Type: Application
    Filed: September 6, 2019
    Publication date: December 26, 2019
    Inventors: Balaji KANNAN, Ayse M. OZBEK, Tao CHU, Bala HARAN, Vishal CHHABRA, Katsunori ONISHI, Guowei XU
  • Publication number: 20190318966
    Abstract: A integrated circuit including an n-doped high-k dielectric layer conformally within a first opening in a dielectric layer such that the n-doped high-k dielectric layer is in direct contact with a portion of a substrate exposed at a bottom of the first opening, a p-doped high-k dielectric layer conformally within a second opening in the dielectric layer such that the p-doped high-k dielectric layer is in direct contact with a portion of the substrate exposed at a bottom of the second opening, a shared work function metal conformally within the first opening and the second opening above and in direct contact with both the p-doped high-k dielectric layer and the n-doped high-k dielectric layer, and a bulk fill material above and in direct contact with the shared work function metal.
    Type: Application
    Filed: June 27, 2019
    Publication date: October 17, 2019
    Inventors: Takashi Ando, Balaji Kannan, Siddarth Krishnan, Unoh Kwon, Shahab Siddiqui
  • Patent number: 10446550
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a cut inside a replacement metal gate trench to mitigate n-p proximity effects and methods of manufacture. The structure described herein includes: a first device; a second device, adjacent to the first device; a dielectric material, of the first device and the second device, including a cut within a trench between the first device and the second device; and a common gate electrode shared with the first device and the second device, the common gate electrode provided over the dielectric material and contacting underlying material within the cut.
    Type: Grant
    Filed: October 13, 2017
    Date of Patent: October 15, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Balaji Kannan, Ayse M. Ozbek, Tao Chu, Bala Haran, Vishal Chhabra, Katsunori Onishi, Guowei Xu
  • Patent number: 10395993
    Abstract: A method for forming a replacement metal gate structure sharing a single work function metal for both the N-FET and the P-FET gates. The method oppositely dopes a high-k material of the N-FET and P-FET gate, respectively, using a single lithography step. The doping allows use of a single work function metal which in turn provides more space in the metal gate opening so that a bulk fill material may occupy more volume of the opening resulting in a lower resistance gate.
    Type: Grant
    Filed: October 4, 2016
    Date of Patent: August 27, 2019
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Balaji Kannan, Siddarth Krishnan, Unoh Kwon, Shahab Siddiqui
  • Patent number: 10332747
    Abstract: In an exemplary method, a dielectric layer is deposited on a substrate. A masking layer is formed over a first region and a second region of the dielectric layer. The masking layer is made of an oxide of lanthanum. The masking layer is removed from the second region of the dielectric layer. A work function layer is formed directly on only the second region of the dielectric layer. The work function layer is made of titanium nitride that is formed by using a combination of titanium tetrachloride and ammonia (TiCl4/NH3).
    Type: Grant
    Filed: January 24, 2018
    Date of Patent: June 25, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Koji Watanabe, Meng Zhu, Brian A. Cohen, Matthew T. Whitman, Balaji Kannan
  • Patent number: 10270354
    Abstract: A synchronous rectifier controller integrated circuit. The synchronous rectifier controller integrated circuit comprises a continuous current mode (CCM) detection circuit configured to detect CCM operation based on sensing a voltage at a pre-defined point in a rectification cycle; a multiplexer having a first reference voltage signal input, a second reference voltage signal input, an output, and a selector input coupled to the CCM detection circuit; and a gate voltage driver circuit coupled to the output of the multiplexer.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: April 23, 2019
    Assignee: Texas Instruments Incorporated
    Inventors: Bing Lu, Bharath Balaji Kannan
  • Publication number: 20190115346
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a cut inside a replacement metal gate trench to mitigate n-p proximity effects and methods of manufacture. The structure described herein includes: a first device; a second device, adjacent to the first device; a dielectric material, of the first device and the second device, including a cut within a trench between the first device and the second device; and a common gate electrode shared with the first device and the second device, the common gate electrode provided over the dielectric material and contacting underlying material within the cut.
    Type: Application
    Filed: October 13, 2017
    Publication date: April 18, 2019
    Inventors: Balaji KANNAN, Ayse M. OZBEK, Tao CHU, Bala HARAN, Vishal CHHABRA, Katsunori ONISHI, Guowei XU