HIGH K METAL GATE STACK WITH SINGLE WORK-FUNCTION METAL
A integrated circuit including an n-doped high-k dielectric layer conformally within a first opening in a dielectric layer such that the n-doped high-k dielectric layer is in direct contact with a portion of a substrate exposed at a bottom of the first opening, a p-doped high-k dielectric layer conformally within a second opening in the dielectric layer such that the p-doped high-k dielectric layer is in direct contact with a portion of the substrate exposed at a bottom of the second opening, a shared work function metal conformally within the first opening and the second opening above and in direct contact with both the p-doped high-k dielectric layer and the n-doped high-k dielectric layer, and a bulk fill material above and in direct contact with the shared work function metal.
The present invention generally relates to Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) made on a semiconductor substrate. In particular, the invention relates to making MOSFETs having a single work-function metal for both the N-FET and the P-FET in a replacement metal gate structure.
Description of Related ArtIn conjunction with Moore's law, gates of MOSFETs shrink with each technology node. In advanced MOSFETs, the gate may be made from a “replacement metal gate” (RMG) process which requires forming a gate opening in a dielectric layer and filling the gate opening with gate materials as opposed to patterning the gate materials and then surrounding them with a dielectric. Due to the number of work function materials required in current gates, the openings may be difficult to subsequently fill with the bulk material and may result in high gate resistances.
Attempts to create more room for a bulk fill material of a replacement metal gate structure included removing the stack of traditionally used WF metals from the sidewall of the opening. However, there are several drawbacks to work function metal recess: first, it requires several additional photolithography masks, patterning and etch steps; second, the wet etch and reactive ion etch (RIE) processes that are integral to this recess process alter the inherent work functions of the work function metals materials which remain at the bottom of the opening which leads to threshold voltage shifts; third, the repeatability and uniformity of the process is not very good, especially, with varying gate lengths of the transistors within each chip and across the entire wafer; and fourth, with the move to shorter gates (smaller vertical height of the opening) to reduce gate capacitance, the variability and control of work function recess process becomes worse. Thus, there is a need to create more space in the gate opening which provides substantial space for the bulk fill material to achieve low gate resistance while simultaneously providing that the correct work functions are set for N-FETs and P-FETs.
BRIEF SUMMARY OF THE INVENTIONThe current invention is a novel structure to both simplify and improve the performance of the replacement metal gate stack for advanced node FETs, and the method of making the same. The current invention allows the correct work functions to be set for N-FETs and P-FETs, while simultaneously allowing substantial space in the gate opening for the bulk fill material which results in lower gate resistance. More specifically, doping of a high-k dielectric film of the gates allows both the N-FET and P-FET gates to share the same, thin, work function metal (single work function metal).
An object of the current invention is a method to form high-k metal gates of a N-FET and a P-FETs by a replacement metal gate process in advanced nodes The replacement metal gate process may be a “high-k first” or a “high-k last” (an embodiment illustrated by the figures) process. The node may be 14 nm and below such that the gate opening may be less than 20 nanometers wide.
A further object of the current invention is that the gates of the N-FET and the P-FET share the same, thin work function metal.
Another object of the current invention is that the gate oxide is doped. The dopants differ in the N-FET gate oxide and the P-FET gate oxide.
Yet a further object of the current invention is to provide a low resistance gate structure by increasing the amount of bulk fill material in the gate opening lined by the work function metal. Despite the gate opening being less than 20 nm, the bulk fill width may be 20-70% of the gate opening width.
An object of the present invention is to form an integrated circuit (IC) including a first gate of an N-FET and a second gate of a P-FET on the substrate wherein the first and second gates have a gate opening width of less than 20 nanonmeters. The IC also includes a work function metal lining both the first gate opening and the second gate opening. Furthermore, a high dielectric material is between the work function metal and the substrate wherein the high dielectric material is doped with an n-dopant in the first gate and is doped with a p-dopant in the second gate. Finally a bulk fill material fills a remainder of gate opening.
Another object of the current invention is a method of forming an N-FET metal gate and a P-FET metal gate sharing the same work function metal, the method comprising. The method provides a dielectric layer over a substrate wherein the dielectric layer has a first opening over an N-FET region of the substrate and a second opening over a P-FET region of the substrate. A high dielectric constant material is formed so as to be in contact with the substrate in the N-FET region and in the P-FET region. A work function metal lines the first and second openings which are subsequently a bulk fill material.
Other characteristics and advantages of the invention will become obvious in combination with the description of accompanying drawings, wherein the same number represents the same or similar parts in all figures.
The basic principle of the invention is a method forming oppositely doped high dielectric constant replacement metal gates which have the same work function (WF) metal stack. This is in contrast to normal methods in which work function tuning of an FET is achieved by varying the WF metal materials and thicknesses of materials. Work function tuning is a way to adjust threshold voltages of a device, thus creating two work function regions which, in turn creates two threshold voltage regions.
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A first important feature of the present invention is that the shared work-function metal 135 itself is only a few tens of Angstroms (Å) thick. As mentioned above, the thickness of the WF metal 135 in an embodiment may be about 25-50 Å, with a typical thickness about 30 Å. Referring to
A second important point of the present invention is that the effective work function of the N-FET is a combination of the inherent work function of the work function metal (TiN of the preferred embodiment) and the additional work function reduction caused by the electric dipole/charges due to the n-dopant (for example, lanthanum) diffused into the high k material. Effective work functions of the N-FET have been demonstrated to be 5.5 to 4.35 eV and ranges therebetween. Similarly, the effective work function of the P-FET is a combination of the inherent work function of the work function metal (TiN of the preferred embodiment) and the additional work function increase caused by the electric dipole/charges due to the p-dopant (for example, aluminum) diffused into the high k material.
Taken together, these two points mean that there is a substantial amount of room in the gate opening to fill the bulk metal while the work function is set by doping. The result is a lower resistance gate contact. Another advantage of the above described method is that only a single mask was needed to incorporate the dopants and set separate N-FET and P-FET work functions. In addition, there is a substantial benefit of PBTI (positive bias temperature instability) with the same Tiny (inverse of gate capacitance) and threshold voltage (Vt). PBTI directly depends on the work function of the NFET work function metal stack that is deposited on the NFET. The higher the work function the lower (i.e. better) the PBTI. The present invention allows the use of a work function metal that has substantially higher work function because the NFET Vt can be reduced using a dipole-induced Vt shift that lanthanum provides. Therefore, a low NFET Vt that is needed for optimal device performance is achieved, but simultaneously improved PBTI through the use of a high work function metal is also achieved.
While the present invention has been described with reference to what are presently considered to be the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. On the contrary, the invention is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims. The scope of the following claims is to be accorded the broadcast interpretation so as to encompass all such modifications and equivalent structures and functions.
Claims
1. An integrated circuit comprising:
- a first gate of an N-FET and a second gate of a P-FET on a substrate, wherein the first gate and the second gate each have a gate opening width of less than 20 nanometers;
- a work function metal lining both the first gate opening and the second gate opening;
- a high dielectric material between the work function metal and the substrate wherein the high dielectric material is doped with an n-dopant in the first gate and is doped with a p-dopant in the second gate; and
- a bulk fill material filling a remainder of the gate opening.
2. The integrated circuit of claim 1, wherein the work function metal is a titanium nitride layer having a thickness from about 25 angstroms to about 50 angstroms.
3. The integrated circuit of claim 1, wherein the high dielectric material lines the sidewalls of the first gate opening and the second gate opening.
4. The integrated circuit of claim 1, wherein the high dielectric material includes an interfacial layer.
5. The integrated circuit of claim 1, wherein the p-dopant is aluminum.
6. The integrated circuit of claim 1, wherein the n-dopant is lanthanum.
7. The integrated circuit of claim 1, wherein the bulk fill material comprises tungsten.
8. The integrated circuit of claim 1, wherein the width of the bulk fill material is about 20 to about 70% of the width of the gate opening in each of the first and second gates.
9. The integrated circuit of claim 1, wherein a width of the bulk fill material is about 20 percent to about 50 percent of the width of the gate opening in each of the first gate and the second gate, and wherein the gate opening width is less than about 17 nanometers.
10. An integrated circuit having an N-FET metal gate and a P-FET metal gate sharing the same work function metal, the integrated circuit comprising:
- an n-doped high dielectric constant material only along a bottom of a first opening in a dielectric layer, the n-doped high dielectric constant material is in direct contact with a portion of a substrate exposed at the bottom of the first opening;
- a p-doped high dielectric constant material only along a bottom of a second opening in the dielectric layer, the p-doped high dielectric constant material is in direct contact with a portion of the substrate exposed at the bottom of the second opening;
- a work function metal above and in direct contact with the p-doped high dielectric constant material and the n-doped high dielectric constant material; and
- a bulk fill material directly on top of the work function metal, wherein a width of the bulk fill material comprises more than about 30% of the width of each of the first opening and the second opening, wherein the work function metal is less than about 40 angstroms thick, and wherein the width of the first opening and the second opening are each less than 20 nanometers.
11. The integrated circuit of claim 10, wherein the p-doped high dielectric constant material comprises aluminum.
12. The integrated circuit of claim 10, wherein the n-doped high dielectric constant material comprises lanthanum.
13. The integrated circuit of claim 10, wherein an effective work function of the N-FET metal gate is a combination of an inherent work function of the work function metal and the additional work function reduction caused by n-dopants of the n-doped high dielectric constant material, and an effective work function of the P-FET metal gate is a combination of an inherent work function of the work function metal and the additional work function increase caused by p-dopants of the p-doped high dielectric constant material.
14. A integrated circuit comprising:
- an n-doped high-k dielectric layer conformally within a first opening in a dielectric layer such that the n-doped high-k dielectric layer is in direct contact with a portion of a substrate exposed at a bottom of the first opening;
- a p-doped high-k dielectric layer conformally within a second opening in the dielectric layer such that the p-doped high-k dielectric layer is in direct contact with a portion of the substrate exposed at a bottom of the second opening;
- a shared work function metal conformally within the first opening and the second opening above and in direct contact with both the p-doped high-k dielectric layer and the n-doped high-k dielectric layer; and
- a bulk fill material above and in direct contact with the shared work function metal.
15. The integrated circuit of claim 14, wherein the first opening is in an N-FET region of the substrate and the second opening is in a P-FET region of the substrate.
16. The integrated circuit of claim 14, wherein the p-doped high-k dielectric layer comprises aluminum.
17. The integrated circuit of claim 14, wherein the n-doped high-k dielectric layer comprises lanthanum.
18. The integrated circuit of claim 14, wherein the shared work function metal comprises titanium nitride and the bulk fill material comprises tungsten.
19. The integrated circuit of claim 14, wherein a width of the first opening and the second opening are each less than 20 nanometers, a thickness of the shared work function metal is less than about 40 angstroms, and a width of the bulk fill material is more than 45% of the width of each of the first opening and the second opening.
Type: Application
Filed: Jun 27, 2019
Publication Date: Oct 17, 2019
Inventors: Takashi Ando (Tuckahoe, NY), Balaji Kannan (Fishkill, NY), Siddarth Krishnan (Newark, CA), Unoh Kwon (Clifton Park, NJ), Shahab Siddiqui (Somers, NY)
Application Number: 16/454,178