Patents by Inventor Balasubramanian Pranatharthiharan

Balasubramanian Pranatharthiharan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9997419
    Abstract: A technique relates to manufacturing a finFET device. A plurality of first and second semiconductor fins are formed on a substrate. Gate stacks are formed on the substrate, each including a gate, a hard mask and an oxide layer. A dielectric spacer layer is deposited. A sacrificial fill material is deposited on the finFET device and planarized. A second hard mask is deposited, a trench area is patterned in the hard mask parallel to the first and second semiconductor fins, and the sacrificial fill material is anisotropically etched to create a trench. A dielectric wall is formed in the trench and the second hard mask and sacrificial fill material are removed.
    Type: Grant
    Filed: May 19, 2016
    Date of Patent: June 12, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Sivananda K. Kanakasabapathy, Balasubramanian Pranatharthiharan
  • Patent number: 9985024
    Abstract: The present invention relates generally to semiconductors, and more particularly, to a structure and method of minimizing shorting between epitaxial regions in small pitch fin field effect transistors (FinFETs). In an embodiment, a dielectric region may be formed in a middle portion of a gate structure. The gate structure be formed using a gate replacement process, and may cover a middle portion of a first fin group, a middle portion of a second fin group and an intermediate region of the substrate between the first fin group and the second fin group. The dielectric region may be surrounded by the gate structure in the intermediate region. The gate structure and the dielectric region may physically separate epitaxial regions formed on the first fin group and the second fin group from one another.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: May 29, 2018
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Balasubramanian Pranatharthiharan, Alexander Reznicek, Charan V. Surisetty
  • Publication number: 20180122711
    Abstract: A method for fabricating a dual silicide device includes growing source and drain (S/D) regions for an N-type device, forming a protection layer over a gate structure and the S/D regions of the N-type device and growing S/D regions for a P-type device. A first dielectric layer is conformally deposited and portions removed to expose the S/D regions. Exposed S/D regions for the P-type device are silicided to form a liner. A second dielectric layer is conformally deposited. A dielectric fill is formed over the second dielectric layer. Contact holes are opened through the second dielectric layer to expose the liner for the P-type device and expose the protection layer for the N-type device. The S/D regions for the N-type device are exposed by opening the protection layer. Exposed S/D regions adjacent to the gate structure are silicided to form a liner for the N-type device. Contacts are formed.
    Type: Application
    Filed: December 19, 2017
    Publication date: May 3, 2018
    Inventors: Balasubramanian Pranatharthiharan, Ruilong Xie, Chun-Chen Yeh
  • Patent number: 9953976
    Abstract: After forming a gate stack straddling a portion of each semiconductor fin of a plurality of semiconductor fins located over a substrate, a gate liner is formed on sidewalls of a lower portion of the gate stack that contacts the plurality of semiconductor fins and a gate spacer having a width greater than a width of the gate liner is formed on sidewalls of an upper portion of the gate stack that is located above the plurality of semiconductor fins. The width of the gate spacer thus is not limited by the fin pitch, and can be optimized to improve the device performance.
    Type: Grant
    Filed: January 10, 2017
    Date of Patent: April 24, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Injo Ok, Sanjay C. Mehta, Balasubramanian Pranatharthiharan, Soon-Cheon Seo, Charan V. Surisetty
  • Publication number: 20180108749
    Abstract: A method for forming self-aligned contacts includes patterning a mask between fin regions of a semiconductor device, etching a cut region through a first dielectric layer between the fin regions down to a substrate and filling the cut region with a first material, which is selectively etchable relative to the first dielectric layer. The first dielectric layer is isotropically etched to reveal source and drain regions in the fin regions to form trenches in the first material where the source and drain regions are accessible. The isotropic etching is super selective to remove the first dielectric layer relative to the first material and relative to gate structures disposed between the source and drain regions. Metal is deposited in the trenches to form silicide contacts to the source and drain regions.
    Type: Application
    Filed: December 19, 2017
    Publication date: April 19, 2018
    Inventors: Andrew M. Greene, Balasubramanian Pranatharthiharan, Ruilong Xie
  • Publication number: 20180108660
    Abstract: A method of forming a semiconductor structure includes depositing a spacer material over a top surface of a substrate and two or more spaced-apart gates formed on the top surface of the substrate. The method also includes depositing a sacrificial liner over the spacer material and etching the sacrificial liner and the spacer material to expose portions of the top surface of the substrate between the two or more spaced-apart gates. The method further includes removing the sacrificial liner such that remaining spacer material forms two or more spacers between the two or more spaced-apart gates, each of the spacers including a first portion proximate the top surface of the substrate having a first width and a second portion above the first portion with a second width smaller than the first width.
    Type: Application
    Filed: October 18, 2016
    Publication date: April 19, 2018
    Inventors: Balasubramanian Pranatharthiharan, Eric R. Miller, Soon-Cheon Seo, John R. Sporre
  • Patent number: 9935168
    Abstract: A method of forming a semiconductor structure includes forming a gate structure having a first conductive material above a semiconductor substrate, gate spacers on opposing sides of the first conductive material, and a first interlevel dielectric (ILD) layer surrounding the gate spacers and the first conductive material. An upper portion of the first conductive material is recessed. The gate spacers are recessed until a height of the gate spacers is less than a height of the gate structure. An isolation liner is deposited above the gate spacers and the first conductive material. A portion of the isolation liner is removed so that a top surface of the first conductive material is exposed. A second conductive material is deposited in a contact hole created above the first conductive material and the gate spacers to form a gate contact.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: April 3, 2018
    Assignees: International Business Machines Corporation, GLOBALFOUNDRIES INC.
    Inventors: David V. Horak, Shom S. Ponoth, Balasubramanian Pranatharthiharan, Ruilong Xie
  • Patent number: 9935003
    Abstract: A method for filling gaps between structures includes forming a plurality of high aspect ratio structures adjacent to one another with gaps, forming a first dielectric layer on tops of the structures and conformally depositing a spacer dielectric layer over the structures. The spacer dielectric layer is removed from horizontal surfaces and a protection layer is conformally deposited over the structures. The gaps are filled with a flowable dielectric, which is recessed to a height along sidewalls of the structures by a selective etch process such that the protection layer protects the spacer dielectric layer on sidewalls of the structures. The first dielectric layer and the spacer dielectric layer are exposed above the height using a higher etch resistance than the protection layer to maintain dimensions of the spacer layer dielectric through the etching processes. The gaps are filled by a high density plasma fill.
    Type: Grant
    Filed: February 7, 2017
    Date of Patent: April 3, 2018
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC.
    Inventors: Huiming Bu, Andrew M. Greene, Balasubramanian Pranatharthiharan, Ruilong Xie
  • Publication number: 20180090566
    Abstract: A semiconductor structure is provided that includes a semiconductor substrate including a first device region and a second device region. First trench isolation structures surround the first and second device regions and extend below first and second pedestal portions of the semiconductor substrate. A first semiconductor material fin stack is located above the first pedestal portion of the semiconductor substrate, and a second semiconductor material fin stack is located above the second pedestal portion of the semiconductor substrate. Second trench isolation structures are located at ends of each first and second semiconductor material fin stacks. A portion of each second trench isolation structure is located directly between a bottommost surface of the first or second semiconductor material fin stack and the first or second pedestal portion of the semiconductor substrate.
    Type: Application
    Filed: November 29, 2017
    Publication date: March 29, 2018
    Inventors: Balasubramanian Pranatharthiharan, Injo Ok, Soon-Cheon Seo, Charan Veera Venkata Satya Surisetty
  • Publication number: 20180090375
    Abstract: According to an embodiment of the present invention, self-aligned gate cap, comprises a gate located on a substrate; a gate cap surrounding a side of the gate; a contact region self-aligned to the gate; and a low dielectric constant oxide having a dielectric constant of less than 3.9 located on top of the gate. According to an embodiment of the present invention, a method of forming a self-aligned contact comprises removing at least a portion of an interlayer dielectric layer to expose a top surface of a gate cap located on a substrate; recessing the gate cap to form a recessed area; depositing a low dielectric constant oxide having a dielectric constant of less than 3.9 in the recessed area; and polishing a surface of the low dielectric constant oxide to expose a contact area.
    Type: Application
    Filed: December 11, 2017
    Publication date: March 29, 2018
    Inventors: Balasubramanian Pranatharthiharan, Injo Ok, Charan V.V.S. Surisetty
  • Publication number: 20180090390
    Abstract: Semiconductor structures with different devices each having spacers of equal thickness and methods of manufacture are disclosed. The method includes forming a first gate stack and a second gate stack. The method further includes forming sidewall spacers of equal thickness for both the first gate stack and the second gate stack by depositing a liner material over spacer material on sidewalls of the first gate stack and the second gate stack and within a space formed between the spacer material and source and drain regions of the first gate stack.
    Type: Application
    Filed: November 30, 2017
    Publication date: March 29, 2018
    Inventors: Kangguo CHENG, Balasubramanian PRANATHARTHIHARAN, Soon-Cheon SEO
  • Patent number: 9929059
    Abstract: A method for fabricating a dual silicide device includes growing source and drain (S/D) regions for an N-type device, forming a protection layer over a gate structure and the S/D regions of the N-type device and growing S/D regions for a P-type device. A first dielectric layer is conformally deposited and portions removed to expose the S/D regions. Exposed S/D regions for the P-type device are silicided to form a liner. A second dielectric layer is conformally deposited. A dielectric fill is formed over the second dielectric layer. Contact holes are opened through the second dielectric layer to expose the liner for the P-type device and expose the protection layer for the N-type device. The S/D regions for the N-type device are exposed by opening the protection layer. Exposed S/D regions adjacent to the gate structure are silicided to form a liner for the N-type device. Contacts are formed.
    Type: Grant
    Filed: December 1, 2016
    Date of Patent: March 27, 2018
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC.
    Inventors: Balasubramanian Pranatharthiharan, Ruilong Xie, Chun-Chen Yeh
  • Patent number: 9929057
    Abstract: A method for filling gaps between structures includes forming a plurality of high aspect ratio structures adjacent to one another with gaps, forming a first dielectric layer on tops of the structures and conformally depositing a spacer dielectric layer over the structures. The spacer dielectric layer is removed from horizontal surfaces and a protection layer is conformally deposited over the structures. The gaps are filled with a flowable dielectric, which is recessed to a height along sidewalls of the structures by a selective etch process such that the protection layer protects the spacer dielectric layer on sidewalls of the structures. The first dielectric layer and the spacer dielectric layer are exposed above the height using a higher etch resistance than the protection layer to maintain dimensions of the spacer layer dielectric through the etching processes. The gaps are filled by a high density plasma fill.
    Type: Grant
    Filed: November 3, 2016
    Date of Patent: March 27, 2018
    Assignees: International Business Machines Corporation, GlobalFoundries, Inc.
    Inventors: Huiming Bu, Andrew M. Greene, Balasubramanian Pranatharthiharan, Ruilong Xie
  • Publication number: 20180082895
    Abstract: According to an embodiment of the present invention, self-aligned gate cap, comprises a gate located on a substrate; a gate cap surrounding a side of the gate; a contact region self-aligned to the gate; and a low dielectric constant oxide having a dielectric constant of less than 3.9 located on top of the gate. According to an embodiment of the present invention, a method of forming a self-aligned contact comprises removing at least a portion of an interlayer dielectric layer to expose a top surface of a gate cap located on a substrate; recessing the gate cap to form a recessed area; depositing a low dielectric constant oxide having a dielectric constant of less than 3.9 in the recessed area; and polishing a surface of the low dielectric constant oxide to expose a contact area.
    Type: Application
    Filed: November 29, 2017
    Publication date: March 22, 2018
    Inventors: Balasubramanian Pranatharthiharan, Injo Ok, Charan V.V.S. Surisetty
  • Patent number: 9923078
    Abstract: A method for forming self-aligned contacts includes patterning a mask between fin regions of a semiconductor device, etching a cut region through a first dielectric layer between the fin regions down to a substrate and filling the cut region with a first material, which is selectively etchable relative to the first dielectric layer. The first dielectric layer is isotropically etched to reveal source and drain regions in the fin regions to form trenches in the first material where the source and drain regions are accessible. The isotropic etching is super selective to remove the first dielectric layer relative to the first material and relative to gate structures disposed between the source and drain regions. Metal is deposited in the trenches to form silicide contacts to the source and drain regions.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: March 20, 2018
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC.
    Inventors: Andrew M. Greene, Balasubramanian Pranatharthiharan, Ruilong Xie
  • Publication number: 20180069007
    Abstract: Semiconductor structures with different devices each having spacers of equal thickness and methods of manufacture are disclosed. The method includes forming a first gate stack and a second gate stack. The method further includes forming sidewall spacers of equal thickness for both the first gate stack and the second gate stack by depositing a liner material over spacer material on sidewalls of the first gate stack and the second gate stack and within a space formed between the spacer material and source and drain regions of the first gate stack.
    Type: Application
    Filed: October 30, 2017
    Publication date: March 8, 2018
    Inventors: Kangguo CHENG, Balasubramanian PRANATHARTHIHARAN, Soon-Cheon SEO
  • Publication number: 20180069026
    Abstract: A method for constructing an advanced FinFET structure is described. A first long silicon fin for n-type FinFET devices and a first long silicon germanium fin for p-type FinFET devices are provided on a strain relaxation buffer (SRB) substrate. The first long silicon fin is cut forming a first and a second cut silicon fin so that the first and second cut silicon fin have a vertical face at a fin end. The first long silicon germanium fin is cut forming a first and a second cut silicon germanium fin, the first and the second cut silicon germanium cut fin have a vertical face at a fin end. A tensile dielectric structure is formed which contacts the vertical faces of the first and second cut silicon fins to maintain tensile strain in the first and second cut silicon fins. A compressive dielectric structure is formed which contacts the vertical faces of the silicon germanium fins to maintain compressive strain in the first and second cut silicon germanium fins.
    Type: Application
    Filed: October 22, 2017
    Publication date: March 8, 2018
    Inventors: Kangguo Cheng, Juntao Li, Balasubramanian Pranatharthiharan
  • Publication number: 20180069118
    Abstract: A FinFET device includes a strain relaxation buffer (SRB) substrate. A set of cut silicon fins is on the SRB substrate. Each fin in the set of cut silicon fins has a pair of long vertical faces and a pair of short vertical faces. Pairs of the cut silicon fins are oriented so that respective short vertical faces of the pair are oriented opposite to each other. A set of cut silicon germanium fins is on the SRB substrate. Each fin in the set of silicon germanium fins has a pair of long vertical faces and a pair of short vertical faces. Pairs of the cut silicon germanium fins are oriented so that respective short vertical faces of the pair are oriented opposite to each other. A set of tensile dielectric structures bridge between the short vertical faces of respective pairs of the cut silicon fins to maintain tensile strain at the fin ends of the pair of cut silicon fins.
    Type: Application
    Filed: October 22, 2017
    Publication date: March 8, 2018
    Inventors: Kangguo Cheng, Juntao Li, Balasubramanian Pranatharthiharan
  • Patent number: 9905463
    Abstract: According to an embodiment of the present invention, self-aligned gate cap, comprises a gate located on a substrate; a gate cap surrounding a side of the gate; a contact region self-aligned to the gate; and a low dielectric constant oxide having a dielectric constant of less than 3.9 located on top of the gate. According to an embodiment of the present invention, a method of forming a self-aligned contact comprises removing at least a portion of an interlayer dielectric layer to expose a top surface of a gate cap located on a substrate; recessing the gate cap to form a recessed area; depositing a low dielectric constant oxide having a dielectric constant of less than 3.9 in the recessed area; and polishing a surface of the low dielectric constant oxide to expose a contact area.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: February 27, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Balasubramanian Pranatharthiharan, Injo Ok, Charan V. V. S. Surisetty
  • Patent number: 9905421
    Abstract: A multi-gate finFET structure and formation thereof. The multi-gate finFET structure has a first gate structure that includes an inner side and an outer side. Adjacent to the first gate structure is a second gate structure. The inner side of the first gate structure faces, at least in part, the second gate structure. A stress-inducing material fills a fin cut trench that is adjacent to the outer side of the first gate structure. An epitaxial semiconductor layer fills, at least in part, an area between the first gate structure and the second gate structure.
    Type: Grant
    Filed: July 28, 2016
    Date of Patent: February 27, 2018
    Assignee: International Business Machines Corporation
    Inventors: Injo Ok, Balasubramanian Pranatharthiharan, Soon-cheon Seo, Charan Veera Venkata Satya Surisetty