Patents by Inventor Balasubramanian Pranatharthiharan

Balasubramanian Pranatharthiharan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor devices with sidewall spacers of equal thickness
    Patent number: 9905479
    Abstract: Semiconductor structures with different devices each having spacers of equal thickness and methods of manufacture are disclosed. The method includes forming a first gate stack and a second gate stack. The method further includes forming sidewall spacers of equal thickness for both the first gate stack and the second gate stack by depositing a liner material over spacer material on sidewalls of the first gate stack and the second gate stack and within a space formed between the spacer material and source and drain regions of the first gate stack.
    Type: Grant
    Filed: January 5, 2017
    Date of Patent: February 27, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Balasubramanian Pranatharthiharan, Soon-Cheon Seo
  • METHOD AND STRUCTURE OF IMPROVING CONTACT RESISTANCE FOR PASSIVE AND LONG CHANNEL DEVICES
    Publication number: 20180053851
    Abstract: A semiconductor device includes a gate arranged on a substrate; a source/drain formed on the substrate adjacent to the gate; a source/drain contact extending from the source/drain and through an interlayer dielectric (ILD) over the source/drain, a portion of the source/drain positioned adjacent to the source/drain contact; and a silicide positioned along a sidewall of the source/drain contact between the portion of the source/drain and the source/drain contact, and along an endwall of the source/drain contact between the source/drain contact and the substrate.
    Type: Application
    Filed: November 13, 2017
    Publication date: February 22, 2018
    Inventors: Injo Ok, Soon-Cheon Seo, Balasubramanian Pranatharthiharan, Charan V. V. S. Surisetty
  • Integrated circuit (IC) with offset gate sidewall contacts and method of manufacture
    Patent number: 9893085
    Abstract: A method of forming logic cell contacts, forming CMOS integrated circuit (IC) chips including the FETs and the IC chips. After forming replacement metal gates (RMG) on fin field effect transistor (finFET) pairs, gates are cut on selected pairs, separating PFET gates from NFET gates. An insulating plug formed between the cut gates isolates the pairs of cut gates from each other. Etching offset gate contacts at the plugs partially exposes each plug and one end of a gate sidewall at each cut gate. A second etch partially exposes cut gates. Filling the open offset contacts with conductive material, e.g., metal forms sidewall cut gate contacts and stitches said cut gate pairs together.
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: February 13, 2018
    Assignee: International Business Machines Corporation
    Inventors: Injo Ok, Balasubramanian Pranatharthiharan, Soon-Cheon Seo, Charan V. Surisetty
  • Semiconductor devices with sidewall spacers of equal thickness
    Patent number: 9887198
    Abstract: Semiconductor structures with different devices each having spacers of equal thickness and methods of manufacture are disclosed. The method includes forming a first gate stack and a second gate stack. The method further includes forming sidewall spacers of equal thickness for both the first gate stack and the second gate stack by depositing a liner material over spacer material on sidewalls of the first gate stack and the second gate stack and within a space formed between the spacer material and source and drain regions of the first gate stack.
    Type: Grant
    Filed: September 22, 2016
    Date of Patent: February 6, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Balasubramanian Pranatharthiharan, Soon-Cheon Seo
  • Method and structure of improving contact resistance for passive and long channel devices
    Patent number: 9887289
    Abstract: A semiconductor device includes a gate arranged on a substrate; a source/drain formed on the substrate adjacent to the gate; a source/drain contact extending from the source/drain and through an interlayer dielectric (ILD) over the source/drain, a portion of the source/drain positioned adjacent to the source/drain contact; and a silicide positioned along a sidewall of the source/drain contact between the portion of the source/drain and the source/drain contact, and along an endwall of the source/drain contact between the source/drain contact and the substrate.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: February 6, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Injo Ok, Soon-Cheon Seo, Balasubramanian Pranatharthiharan, Charan V. V. S. Surisetty
  • Strained CMOS on strain relaxation buffer substrate
    Patent number: 9882050
    Abstract: An advanced FinFET structure is described. The structure includes a strain relaxation buffer (SRB) substrate. A set of cut silicon fins is on the SRB substrate. Each fin in the set of cut silicon fins has a vertical face at a fin end of a respective cut silicon fin. A set of cut silicon germanium fins is on the substrate. Each fin in the set of silicon germanium fins has a vertical face at a fin end of a respective cut silicon germanium fin. A set of tensile dielectric structures contact the vertical faces of the cut silicon fins to maintain tensile strain at the fin ends of the set of cut silicon fins. A set of compressive dielectric structures contact the vertical faces of respective fin ends of the cut silicon germanium fins to maintain compressive strain at the fin ends of the set of cut silicon fins.
    Type: Grant
    Filed: April 12, 2017
    Date of Patent: January 30, 2018
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Juntao Li, Balasubramanian Pranatharthiharan
  • Nanosheet isolation for bulk CMOS non-planar devices
    Patent number: 9871099
    Abstract: A semiconductor structure is provided that includes a semiconductor substrate including a first device region and a second device region. First trench isolation structures surround the first and second device regions and extend below first and second pedestal portions of the semiconductor substrate. A first semiconductor material fin stack is located above the first pedestal portion of the semiconductor substrate, and a second semiconductor material fin stack is located above the second pedestal portion of the semiconductor substrate. Second trench isolation structures are located at ends of each first and second semiconductor material fin stacks. A portion of each second trench isolation structure is located directly between a bottommost surface of the first or second semiconductor material fin stack and the first or second pedestal portion of the semiconductor substrate.
    Type: Grant
    Filed: November 9, 2015
    Date of Patent: January 16, 2018
    Assignee: International Business Machines Corporation
    Inventors: Balasubramanian Pranatharthiharan, Injo Ok, Soon-Cheon Seo, Charan Veera Venkata Satya Surisetty
  • SEMICONDUCTOR STRUCTURE CONTAINING LOW-RESISTANCE SOURCE AND DRAIN CONTACTS
    Publication number: 20180012892
    Abstract: Semiconductor structures having a source contact and a drain contact that exhibit reduced contact resistance and methods of forming the same are disclosed. In one embodiment of the present application, the reduced contact resistance is provided by forming a layer of a dipole metal or metal-insulator-semiconductor (MIS) oxide between an epitaxial semiconductor material (providing the source region and the drain region of the device) and an overlying metal semiconductor alloy. In yet other embodiment, the reduced contact resistance is provided by increasing the area of the source region and drain region by patterning the epitaxial semiconductor material that constitutes at least an upper portion of the source region and drain region of the device.
    Type: Application
    Filed: September 7, 2017
    Publication date: January 11, 2018
    Inventors: Injo Ok, Balasubramanian Pranatharthiharan, Charan Veera Venkata Satya Surisetty
  • SURFACE AREA AND SCHOTTKY BARRIER HEIGHT ENGINEERING FOR CONTACT TRENCH EPITAXY
    Publication number: 20180006141
    Abstract: Forming a contact is disclosed. A trench through an interlayer dielectric layer is opened down to a substrate. The interlayer dielectric layer is formed on the substrate such that the substrate is the bottom surface of the trench. A cleaning process of the trench is performed. The bottom surface of the trench is recessed. A trench contact epitaxial layer is formed in the trench. An oxide layer is formed on top of the trench contact epitaxial layer in the trench. A metal oxide layer is formed on top of the oxide layer in the trench. A metal contact is formed on top of the metal oxide layer, where the oxide layer and the metal oxide layer together form a dipole layer.
    Type: Application
    Filed: May 17, 2017
    Publication date: January 4, 2018
    Inventors: Jody Fronheiser, Shogo Mochizuki, Hiroaki Niimi, Balasubramanian Pranatharthiharan, Mark Raymond, Tenko Yamashita
  • SURFACE AREA AND SCHOTTKY BARRIER HEIGHT ENGINEERING FOR CONTACT TRENCH EPITAXY
    Publication number: 20180006140
    Abstract: Forming a contact is disclosed. A trench through an interlayer dielectric layer is opened down to a substrate. The interlayer dielectric layer is formed on the substrate such that the substrate is the bottom surface of the trench. A cleaning process of the trench is performed. The bottom surface of the trench is recessed. A trench contact epitaxial layer is formed in the trench. An oxide layer is formed on top of the trench contact epitaxial layer in the trench. A metal oxide layer is formed on top of the oxide layer in the trench. A metal contact is formed on top of the metal oxide layer, where the oxide layer and the metal oxide layer together form a dipole layer.
    Type: Application
    Filed: June 29, 2016
    Publication date: January 4, 2018
    Inventors: Jody Fronheiser, Shogo Mochizuki, Hiroaki Niimi, Balasubramanian Pranatharthiharan, Mark Raymond, Tenko Yamashita
  • Strained CMOS on strain relaxation buffer substrate
    Patent number: 9853056
    Abstract: A set of silicon fins for n-type FinFET devices and a set of silicon germanium fins for p-type FinFET devices are provided on a strain relaxation buffer (SRB) substrate. Each fin in the set of silicon fins is cut forming a set of cut silicon fins having a set of vertical faces at a fin end of a respective cut silicon fin. Each fin in the set of silicon germanium fins is cut forming a set of cut silicon germanium fins having a set of vertical faces at a fin end of a respective silicon germanium fin. A set of tensile dielectric structures is formed. Each of the tensile dielectric structures respectively contact the vertical faces of respective fin ends of the cut silicon fins to maintain tensile strain at the fin ends of the set of cut silicon fins. A set of compressive dielectric structures are formed.
    Type: Grant
    Filed: September 2, 2016
    Date of Patent: December 26, 2017
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Juntao Li, Balasubramanian Pranatharthiharan
  • Minimizing shorting between FinFET epitaxial regions
    Patent number: 9852951
    Abstract: The present invention relates generally to semiconductors, and more particularly, to a structure and method of minimizing shorting between epitaxial regions in small pitch fin field effect transistors (FinFETs). In an embodiment, a dielectric region may be formed in a middle portion of a gate structure. The gate structure be formed using a gate replacement process, and may cover a middle portion of a first fin group, a middle portion of a second fin group and an intermediate region of the substrate between the first fin group and the second fin group. The dielectric region may be surrounded by the gate structure in the intermediate region. The gate structure and the dielectric region may physically separate epitaxial regions formed on the first fin group and the second fin group from one another.
    Type: Grant
    Filed: August 16, 2016
    Date of Patent: December 26, 2017
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Balasubramanian Pranatharthiharan, Alexander Reznicek, Charan V. Surisetty
  • SOURCE AND DRAIN EPITAXIAL SEMICONDUCTOR MATERIAL INTEGRATION FOR HIGH VOLTAGE SEMICONDUCTOR DEVICES
    Publication number: 20170365521
    Abstract: A method of forming a semiconductor device that includes providing a first set of fin structures having a first pitch, and a second set of fin structure having a second pitch, wherein the second pitch is greater than the first pitch. An epitaxial semiconductor material on the first and second set of fin structures. The epitaxial semiconductor material on the first fin structures is merging epitaxial material and the epitaxial material on the second fin structures is non-merging epitaxial material. A dielectric liner is formed atop the epitaxial semiconductor material that is present on the first and second sets of fin structures. The dielectric liner is removed from a portion of the non-merging epitaxial material that is present on the second set of fin structures. A bridging epitaxial semiconductor material is formed on exposed surfaces of the non-merging epitaxial material.
    Type: Application
    Filed: August 29, 2017
    Publication date: December 21, 2017
    Inventors: Balasubramanian Pranatharthiharan, Junli Wang, Ruilong Xie
  • SOURCE AND DRAIN EPITAXIAL SEMICONDUCTOR MATERIAL INTEGRATION FOR HIGH VOLTAGE SEMICONDUCTOR DEVICES
    Publication number: 20170365682
    Abstract: A method of forming a semiconductor device that includes providing a first set of fin structures having a first pitch, and a second set of fin structure having a second pitch, wherein the second pitch is greater than the first pitch. An epitaxial semiconductor material on the first and second set of fin structures. The epitaxial semiconductor material on the first fin structures is merging epitaxial material and the epitaxial material on the second fin structures is non-merging epitaxial material. A dielectric liner is formed atop the epitaxial semiconductor material that is present on the first and second sets of fin structures. The dielectric liner is removed from a portion of the non-merging epitaxial material that is present on the second set of fin structures. A bridging epitaxial semiconductor material is formed on exposed surfaces of the non-merging epitaxial material.
    Type: Application
    Filed: August 29, 2017
    Publication date: December 21, 2017
    Inventors: Balasubramanian Pranatharthiharan, Junli Wang, Ruilong Xie
  • Method to prevent lateral epitaxial growth in semiconductor devices
    Patent number: 9825044
    Abstract: The method for preventing epitaxial growth in a semiconductor device begins with cutting a set of long fins into a set of fins of a FinFET structure, the set of fins having respective cut faces of a set of cut faces located at respective fin ends of a set of fin ends. A photoresist layer is patterned over the set of fin ends of the set of fins of the FinFET structure. The photoresist pattern over the set of fin ends differs from the photoresist pattern over other areas of the FinFET structure as the photoresist pattern over the set of fin ends protects the first dielectric material at the set of fin ends. A set of dielectric blocks is formed at the set of fin ends, wherein each of the dielectric blocks covers at least one cut face. The set of dielectric blocks prevents epitaxial growth at the set of fin ends in a subsequent epitaxial growth step.
    Type: Grant
    Filed: October 8, 2016
    Date of Patent: November 21, 2017
    Assignees: International Business Machines Corporation, Global Foundries
    Inventors: Balasubramanian Pranatharthiharan, Hui Zang
  • FET TRENCH DIPOLE FORMATION
    Publication number: 20170330802
    Abstract: A semiconductor structure includes a first layered dipole structure formed within a gate trench within a first polarity region of the semiconductor structure. A second layered dipole structure is formed within a gate trench within a second polarity region of the semiconductor structure and formed upon the first layered dipole structure. The layered dipole structure nearest to the bottom of the gate trench includes a dipole layer of opposite polarity relative to the polarity region of the semiconductor structure where the gate trench is located and reduces source to drain leakage.
    Type: Application
    Filed: August 3, 2017
    Publication date: November 16, 2017
    Inventors: Injo Ok, Balasubramanian Pranatharthiharan, Soon-Cheon Seo, Charan V. V. S. Surisetty
  • Forming stressed epitaxial layers between gates separated by different pitches
    Patent number: 9818873
    Abstract: Various embodiments include methods and integrated circuit structures. In some cases, a method of forming an integrated circuit structure can include: forming a doped silicon layer over a substrate; forming a plurality of fin structures from the doped silicon layer; forming a plurality of gate structures over the plurality of fin structures, each of the plurality of gate structures separated from a neighboring gate structure by a first pitch; forming a mask over the plurality of gate structures, exposing at least one of the plurality of gate structures; removing the at least one of the plurality of gate structures, wherein two of the remaining gate structures after the removing are separated by a second pitch larger than the first pitch; and forming an epitaxial region over the substrate between the two of the remaining gate structures.
    Type: Grant
    Filed: October 9, 2015
    Date of Patent: November 14, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Emre Alptekin, Lars W. Liebmann, Injo Ok, Balasubramanian Pranatharthiharan, Ravikumar Ramachandran, Soon-Cheon Seo, Charan V. V. S. Surisetty, Mickey H. Yu
  • MINIMIZE MIDDLE-OF-LINE CONTACT LINE SHORTS
    Publication number: 20170323833
    Abstract: Semiconductor structures and methods of forming such structures are disclosed. In an embodiment, the semiconductor structure comprises a substrate, a dielectric layer, and a plurality of gates, including a first gate and a pair of adjacent gates. The method comprises forming gate caps on the adjacent gates, including etching portions of the gate electrodes in the adjacent gates to recess the gate electrodes therein, and forming the caps above the recessed gate electrodes. Conductive metal trenches are formed in the dielectric layer, on the sides of the first gate; and after forming the trenches, a contact is formed over the gate electrode of the first gate and over and on one of the conductive trenches. In embodiments, the contact is a gate contact, and in other embodiments, the contact is a non-gate contact.
    Type: Application
    Filed: May 17, 2017
    Publication date: November 9, 2017
    Inventors: Injo Ok, Balasubramanian Pranatharthiharan, Soon-Cheon Seo, Charan V. Surisetty
  • Method to prevent lateral epitaxial growth in semiconductor devices
    Patent number: 9812368
    Abstract: The method for preventing epitaxial growth in a semiconductor device begins with cutting a set of long fins into a set of fins of a FinFET structure. Each of the set of fins has respective cut faces located at the fin ends of a set of fin ends. A photoresist layer is patterned over the set of fin ends on the set of fins of the FinFET structure. The set of fins are isolated from one another by a first dielectric material. The photoresist is patterned over the set of fin ends so that it differs from the photoresist pattern over other areas of the FinFET structure. A set of dielectric blocks is formed on the set of fin ends using the photoresist pattern. The set of dielectric blocks prevents epitaxial growth at the set of fin ends in a subsequent epitaxial growth step.
    Type: Grant
    Filed: October 8, 2016
    Date of Patent: November 7, 2017
    Assignees: International Business Machines Corporation, Global Foundries
    Inventors: Balasubramanian Pranatharthiharan, Hui Zang
  • FinFET spacer formation on gate sidewalls, between the channel and source/drain regions
    Patent number: 9806078
    Abstract: FinFET spacer formation includes, for example, providing an intermediate semiconductor structure having a substrate having one or more fin having a first and a second plurality of gates disposed thereon, and a first plurality of spacers disposed on sides of the first and second plurality of gates, depositing a first liner on the structure, depositing a fill material at a level along inner portions of the first liner between the gates adjacent to the one or more fin, removing outer portions of the first spacers and the first liner away from the fill material, the remaining portions of the first spacers and the first liner defining a first thickness, and depositing a second liner having a second thickness over the gates and over the remaining portions of the first spacers and the first liner, and the fill material, and wherein the first thickness is greater than the second thickness.
    Type: Grant
    Filed: November 2, 2016
    Date of Patent: October 31, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ruilong Xie, Christopher Prindle, Tenko Yamashita, Balasubramanian Pranatharthiharan, Pietro Montanini, Soon-Cheon Seo