Patents by Inventor Balasubramanian S. Haran
Balasubramanian S. Haran has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9548356Abstract: Shallow trench isolation structures are provided for use with UTBB (ultra-thin body and buried oxide) semiconductor substrates, which prevent defect mechanisms from occurring, such as the formation of electrical shorts between exposed portions of silicon layers on the sidewalls of shallow trench of a UTBB substrate, in instances when trench fill material of the shallow trench is subsequently etched away and recessed below an upper surface of the UTBB substrate.Type: GrantFiled: May 18, 2015Date of Patent: January 17, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Bruce B. Doris, Kangguo Cheng, Balasubramanian S. Haran, Ali Khakifirooz, Pranita Kerber, Arvind Kumar, Shom Ponoth
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Patent number: 9478549Abstract: An improved finFET and method of fabrication using a silicon-on-nothing process flow is disclosed. Nitride spacers protect the fin sides during formation of cavities underneath the fins for the silicon-on-nothing (SON) process. A flowable oxide fills the cavities to form an insulating dielectric layer under the fins.Type: GrantFiled: October 31, 2014Date of Patent: October 25, 2016Assignee: GLOBALFOUNDRIES Inc.Inventors: Kangguo Cheng, Balasubramanian S. Haran, Shom Ponoth, Theodorus Eduardus Standaert, Tenko Yamashita
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Patent number: 9406570Abstract: A method for fabricating a field effect transistor device includes removing a portion of a first semiconductor layer and a first insulator layer to expose a portion of a second semiconductor layer, wherein the second semiconductor layer is disposed on a second insulator layer, the first insulator layer is disposed on the second semiconductor layer, and the first semiconductor layer is disposed on the first insulator layer, removing portions of the first semiconductor layer to form a first fin disposed on the first insulator layer and removing portions of the second semiconductor layer to form a second fin disposed on the second insulator layer, and forming a first gate stack over a portion of the first fin and forming a second gate stack over a portion of the second fin.Type: GrantFiled: April 27, 2015Date of Patent: August 2, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Kangguo Cheng, Balasubramanian S. Haran, Shom Ponoth, Theodorus E. Standaert, Tenko Yamashita
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Patent number: 9406790Abstract: A mandrel having vertical planar surfaces is formed on a single crystalline semiconductor layer. An epitaxial semiconductor layer is formed on the single crystalline semiconductor layer by selective epitaxy. A first spacer is formed around an upper portion of the mandrel. The epitaxial semiconductor layer is vertically recessed employing the first spacers as an etch mask. A second spacer is formed on sidewalls of the first spacer and vertical portions of the epitaxial semiconductor layer. Horizontal bottom portions of the epitaxial semiconductor layer are etched from underneath the vertical portions of the epitaxial semiconductor layer to form a suspended ring-shaped semiconductor fin that is attached to the mandrel. A center portion of the mandrel is etched employing a patterned mask layer that covers two end portions of the mandrel. A suspended semiconductor fin is provided, which is suspended by a pair of support structures.Type: GrantFiled: October 2, 2014Date of Patent: August 2, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Kangguo Cheng, James J. Demarest, Balasubramanian S. Haran
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Patent number: 9406679Abstract: A substrate is provided, having formed thereon a first region and a second region of a complementary type to the first region. A gate dielectric is deposited over the substrate, and a first full metal gate stack is deposited over the gate dielectric. The first full metal gate stack is removed over the first region to produce a resulting structure. Over the resulting structure, a second full metal gate stack is deposited, in contact with the gate dielectric over the first region. The first and second full metal gate stacks are encapsulated.Type: GrantFiled: July 26, 2015Date of Patent: August 2, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Lisa F. Edge, Hemanth Jagannathan, Balasubramanian S. Haran
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Patent number: 9368590Abstract: A method is provided for fabricating an integrated circuit that includes multiple transistors. A replacement gate stack is formed on a semiconductor layer, a gate spacer is formed, and a dielectric layer is formed. The dummy gate stack is removed to form a cavity. A gate dielectric and a work function metal layer are formed in the cavity. The cavity is filled with a gate conductor. One and only one of the gate conductor and the work function metal layer are selectively recessed. An oxide film is formed in the recess such that its upper surface is co-planar with the upper surface of the dielectric layer. The oxide film is used to selectively grow an oxide cap. An interlayer dielectric is formed and etched to form a cavity for a source/drain contact. A source/drain contact is formed in the contact cavity, with a portion of the source/drain contact being located directly on the oxide cap.Type: GrantFiled: November 6, 2013Date of Patent: June 14, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Susan S. Fan, Balasubramanian S. Haran, David V. Horak, Charles W. Koburger
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Publication number: 20160126352Abstract: A substrate including a handle substrate, a lower insulator layer, a buried semiconductor layer, an upper insulator layer, and a top semiconductor layer is provided. Semiconductor fins can be formed by patterning a portion of the buried semiconductor layer after removal of the upper insulator layer and the top semiconductor layer in a fin region, while a planar device region is protected by an etch mask. A disposable fill material portion is formed in the fin region, and a shallow trench isolation structure can be formed in the planar device region. The disposable fill material portion is removed, and gate stacks for a planar field effect transistor and a fin field effect transistor can be simultaneously formed. Alternately, disposable gate structures and a planarization dielectric layer can be formed, and replacement gate stacks can be subsequently formed.Type: ApplicationFiled: January 13, 2016Publication date: May 5, 2016Applicant: GLOBALFOUNDRIES INC.Inventors: Kangguo Cheng, Balasubramanian S. Haran, Shom Ponoth, Theodorus E. Standaert, Tenko Yamashita
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Patent number: 9299719Abstract: An apparatus and a method for creating a CMOS with a dual raised source and drain for NMOS and PMOS. The spacers on both stack gates are of equal thickness. In this method, a first insulating layer is formed on the surface. The first region is then masked while the other region has the first layer etched away and has an epitaxial source and drain grown on the region. A second layer is formed to all exposed surfaces. The second region is then masked while the first region is etched away. The epitaxial source and drain is formed on the first region. The second region can also be masked by adding a thin layer of undoped silicon and then oxidize it. Another way to mask the second region is to use a hard mask. Another way to form the second source and drain is to use amorphous material.Type: GrantFiled: January 29, 2015Date of Patent: March 29, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Kangguo Cheng, Bruce B. Doris, Balasubramanian S. Haran, Ali Khakifirooz
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Patent number: 9275911Abstract: A substrate including a handle substrate, a lower insulator layer, a buried semiconductor layer, an upper insulator layer, and a top semiconductor layer is provided. Semiconductor fins can be formed by patterning a portion of the buried semiconductor layer after removal of the upper insulator layer and the top semiconductor layer in a fin region, while a planar device region is protected by an etch mask. A disposable fill material portion is formed in the fin region, and a shallow trench isolation structure can be formed in the planar device region. The disposable fill material portion is removed, and gate stacks for a planar field effect transistor and a fin field effect transistor can be simultaneously formed. Alternately, disposable gate structures and a planarization dielectric layer can be formed, and replacement gate stacks can be subsequently formed.Type: GrantFiled: October 12, 2012Date of Patent: March 1, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Kangguo Cheng, Balasubramanian S. Haran, Shom Ponoth, Theodorus E. Standaert, Tenko Yamashita
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Patent number: 9269629Abstract: FinFET structures with dielectric fins and methods of fabrication are disclosed. A gas cluster ion beam (GCIB) tool is used to apply an ion beam to exposed fins, which converts the fins from a semiconductor material such as silicon, to a dielectric such as silicon nitride or silicon oxide. Unlike some prior art techniques, where some fins are removed prior to fin merging, in embodiments of the present invention, fins are not removed. Instead, semiconductor (silicon) fins are converted to dielectric (nitride/oxide) fins where it is desirable to have isolation between groups of fins that comprise various finFET devices on an integrated circuit (IC).Type: GrantFiled: October 30, 2014Date of Patent: February 23, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Kangguo Cheng, Balasubramanian S. Haran, Ali Khakifirooz, Shom Ponoth, Theodorus Eduardus Standaert, Tenko Yamashita
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Patent number: 9263466Abstract: An apparatus and a method for creating a CMOS with a dual raised source and drain for NMOS and PMOS. The spacers on both stack gates are of equal thickness. In this method, a first insulating layer is formed on the surface. The first region is then masked while the other region has the first layer etched away and has an epitaxial source and drain grown on the region. A second layer is formed to all exposed surfaces. The second region is then masked while the first region is etched away. The epitaxial source and drain is formed on the first region. The second region can also be masked by adding a thin layer of undoped silicon and then oxidize it. Another way to mask the second region is to use a hard mask. Another way to form the second source and drain is to use amorphous material.Type: GrantFiled: January 29, 2015Date of Patent: February 16, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Kangguo Cheng, Bruce B. Doris, Balasubramanian S. Haran, Ali Khakifirooz
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Patent number: 9263465Abstract: An apparatus and a method for creating a CMOS with a dual raised source and drain for NMOS and PMOS. The spacers on both stack gates are of equal thickness. In this method, a first insulating layer is formed on the surface. The first region is then masked while the other region has the first layer etched away and has an epitaxial source and drain grown on the region. A second layer is formed to all exposed surfaces. The second region is then masked while the first region is etched away. The epitaxial source and drain is formed on the first region. The second region can also be masked by adding a thin layer of undoped silicon and then oxidize it. Another way to mask the second region is to use a hard mask. Another way to form the second source and drain is to use amorphous material.Type: GrantFiled: January 29, 2015Date of Patent: February 16, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Kangguo Cheng, Bruce B. Doris, Balasubramanian S. Haran, Ali Khakifirooz
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Patent number: 9257350Abstract: A method for fabricating a field effect transistor device includes removing a portion of a first semiconductor layer and a first insulator layer to expose a portion of a second semiconductor layer, wherein the second semiconductor layer is disposed on a second insulator layer, the first insulator layer is disposed on the second semiconductor layer, and the first semiconductor layer is disposed on the first insulator layer, removing portions of the first semiconductor layer to form a first fin disposed on the first insulator layer and removing portions of the second semiconductor layer to form a second fin disposed on the second insulator layer, and forming a first gate stack over a portion of the first fin and forming a second gate stack over a portion of the second fin.Type: GrantFiled: April 27, 2015Date of Patent: February 9, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Kangguo Cheng, Balasubramanian S. Haran, Shom Ponoth, Theodorus E. Standaert, Tenko Yamashita
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Patent number: 9257531Abstract: A metallic top surface of a replacement gate structure is oxidized to convert a top portion of the replacement gate structure into a dielectric oxide. After removal of a planarization dielectric layer, selective epitaxy is performed to form a raised source region and a raised drain region that extends higher than the topmost surface of the replacement gate structure. A gate level dielectric layer including a first dielectric material is deposited and subsequently planarized employing the raised source and drain regions as stopping structures. A contact level dielectric layer including a second dielectric material is formed over the gate level dielectric layer, and contact via holes are formed employing an etch chemistry that etches the second dielectric material selective to the first dielectric material. Raised source and drain regions are recessed. Self-aligned contact structures can be formed by filling the contact via holes with a conductive material.Type: GrantFiled: September 9, 2014Date of Patent: February 9, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Soon-Cheon Seo, Balasubramanian S. Haran, Alexander Reznicek
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Patent number: 9245965Abstract: A structure including a first plurality of fins and a second plurality of fins etched from a semiconductor substrate, and a fill material located above the semiconductor substrate and between the first plurality of fins and the second plurality of fins, the fill material does not contact either the first plurality of fins or the second plurality of fins.Type: GrantFiled: July 10, 2014Date of Patent: January 26, 2016Assignee: GLOBALFOUNDRIES Inc.Inventors: Balasubramanian S. Haran, Sanjay Mehta, Shom Ponoth, Ravikumar Ramachandran, Stefan Schmitz, Theodorus E. Standaert
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Patent number: 9219068Abstract: An improved finFET and method of fabrication using a silicon-on-nothing process flow is disclosed. Nitride spacers protect the fin sides during formation of cavities underneath the fins for the silicon-on-nothing (SON) process. A flowable oxide fills the cavities to form an insulating dielectric layer under the fins.Type: GrantFiled: October 31, 2014Date of Patent: December 22, 2015Assignee: GLOBALFOUNDRIES INCInventors: Kangguo Cheng, Balasubramanian S. Haran, Shom Ponoth, Theodorus Eduardus Standaert, Tenko Yamashita
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Patent number: 9214378Abstract: A method of making a silicon-on-insulator (SOI) semiconductor device includes etching an undercut isolation trench into an SOI substrate, the SOI substrate comprising a bottom substrate, a buried oxide (BOX) layer formed on the bottom substrate, and a top SOI layer formed on the BOX layer, wherein the undercut isolation trench extends through the top SOI layer and the BOX layer and into the bottom substrate such that a portion of the undercut isolation trench is located in the bottom substrate underneath the BOX layer. The undercut isolation trench is filled with an undercut fill comprising an insulating material to form an undercut isolation region. A field effect transistor (FET) device is formed on the top SOI layer adjacent to the undercut isolation region, wherein the undercut isolation region extends underneath a source/drain region of the FET.Type: GrantFiled: June 29, 2012Date of Patent: December 15, 2015Assignee: International Business Machines CorporationInventors: Kangguo Cheng, Bruce B. Doris, Balasubramanian S. Haran, Shom Ponoth, Theodorus E. Standaert, Tenko Yamashita
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Publication number: 20150340288Abstract: An improved finFET and method of fabrication using a silicon-on-nothing process flow is disclosed. Nitride spacers protect the fin sides during formation of cavities underneath the fins for the silicon-on-nothing (SON) process. A flowable oxide fills the cavities to form an insulating dielectric layer under the fins.Type: ApplicationFiled: October 31, 2014Publication date: November 26, 2015Applicant: International Business Machines CorporationInventors: Kangguo Cheng, Balasubramanian S. Haran, Shom Ponoth, Theodorus Eduardus Standaert, Tenko Yamashita
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Publication number: 20150333065Abstract: A substrate is provided, having formed thereon a first region and a second region of a complementary type to the first region. A gate dielectric is deposited over the substrate, and a first full metal gate stack is deposited over the gate dielectric. The first full metal gate stack is removed over the first region to produce a resulting structure. Over the resulting structure, a second full metal gate stack is deposited, in contact with the gate dielectric over the first region. The first and second full metal gate stacks are encapsulated.Type: ApplicationFiled: July 26, 2015Publication date: November 19, 2015Inventors: Lisa F. Edge, Hemanth Jagannathan, Balasubramanian S. Haran
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Patent number: 9190465Abstract: A method for fabricating a field effect transistor device includes removing a portion of a first semiconductor layer and a first insulator layer to expose a portion of a second semiconductor layer, wherein the second semiconductor layer is disposed on a second insulator layer, the first insulator layer is disposed on the second semiconductor layer, and the first semiconductor layer is disposed on the first insulator layer, removing portions of the first semiconductor layer to form a first fin disposed on the first insulator layer and removing portions of the second semiconductor layer to form a second fin disposed on the second insulator layer, and forming a first gate stack over a portion of the first fin and forming a second gate stack over a portion of the second fin.Type: GrantFiled: February 26, 2014Date of Patent: November 17, 2015Assignee: GLOBALFOUNDRIES INC.Inventors: Kangguo Cheng, Balasubramanian S. Haran, Shom Ponoth, Theodorus E. Standaert, Tenko Yamashita