Abstract: A cooling sleeve for an electric machine is provided. The cooling sleeve includes: a cylindrical body having an exterior surface, a first channel formed in the cylindrical body and having a first inlet for receiving a cooling fluid, and a second channel formed in the cylindrical body and having a second inlet for receiving the cooling fluid. The first inlet and the second inlet are formed on the exterior surface at a center along a length of the cylindrical body. A plurality of turbulators are formed in the first channel and the second channel and a cylindrical cover is configured to be disposed over the cylindrical body.

Abstract: In an embodiment, a method for managing self-tests in an integrated circuit (IC) includes: receiving built-in-self-test (BIST) configuration data; configuring a first clock to a first frequency based on the BIST configuration data; performing a first BIST test at the first frequency; configuring a second clock to a second frequency that is different from the first frequency; and performing a second BIST test at the second frequency.

Abstract: The present invention relates to the stereospecific synthesis of (R)-5-((E)-2-pyrrolidin-3-ylvinyl)pyrimidine, its salt forms, and novel polymorphic forms of these salts.

Abstract: Provided is a method for producing thermoplastic articles. The method comprises forming a hollow parison of heated thermoplastic material and positioning the parison within a cavity of a mold tool, the cavity defining the external configuration of the desired article. Fluid pressure is then applied to an internal chamber defined by the parison upon closure of the mold tool, to expand the parison to conform to the mold cavity. The formed article is then subjected to an in-mold cooling phase to reduce the thermal energy of the formed article sufficiently to permit for safe ejection with reduced distortion. The cooling phase is defined by a variable cooling protocol that applies one or more cycles of thermal shock to the formed article during the in-mold cooling phase.

Abstract: Disclosed herein is a method of operating a system in a test mode. When the test mode is an ATPG test mode, the method includes beginning stuck-at testing by setting a scan control signal to a logic one, setting a transition mode signal to a logic 0, and initializing FIFO buffer for ATPG test mode. The FIFO buffer is initialized for ATPG test mode by setting a scan reset signal to a logic 0 to place a write data register and a read data register associated with the FIFO buffer into a reset state, enabling latches of the FIFO buffer using an external enable signal, removing the external enable signal to cause the latches to latch, and setting the scan reset signal to a logic 1 to release the write data register and the read data register from the reset state, while not clocking the write data register.

Abstract: Disclosed herein is logic circuitry and techniques for operation that hardware to enable the construction of first-in-first-out (FIFO) buffers from latches while permitting stuck-at-1 fault testing for the enable pin of those latches, as well as testing the data path at individual points through the FIFO buffer.

Abstract: Disclosed herein is logic circuitry and techniques for operation that hardware to enable the construction of first-in-first-out (FIFO) buffers from latches while permitting stuck-at-1 fault testing for the enable pin of those latches, as well as testing the data path at individual points through the FIFO buffer.

Abstract: The present invention relates to the stereospecific synthesis of (R)-5-((E)-2-pyrrolidin-3-ylvinyl)pyrimidine, its salt forms, and novel polymorphic forms of these salts.

Abstract: In an embodiment, a method for managing self-tests in an integrated circuit (IC) includes: receiving built-in-self-test (BIST) configuration data; configuring a first clock to a first frequency based on the BIST configuration data; performing a first BIST test at the first frequency; configuring a second clock to a second frequency that is different from the first frequency; and performing a second BIST test at the second frequency.

Abstract: The present invention relates to the stereospecific synthesis of (R)-5-((E)-2-pyrrolidin-3-ylvinyl)pyrimidine, its salt forms, and novel polymorphic forms of these salts.

Abstract: A disconnect assembly for an input shaft and an output shaft includes a sleeve configured to be disposed about the input shaft and the output shaft. A cam is disposed about the sleeve. A cam follower is configured to contact the cam. An interfacing element is configured to operatively interface the sleeve, the input shaft, and the output shaft. The sleeve, the cam, the cam follower, and the interfacing element are configured to move between a respective connect position and a respective disconnect position.

Abstract: A transmitter circuit for use in a source synchronous type interface includes a flip-flop having a data input configured to receive serial data, a clock input configured to receive a source clock and a data output coupled to a data line. A first multiplexer has a first input configured to receive the source clock, a second input configured to receive a phase shifted clock (shifted by ninety degrees from the source clock), and a clock output coupled to a clock line. A control circuit operates to control selection by the first multiplexer of the source clock as a transmit clock sent over the clock line for a delay on clock at destination implementation. Alternatively, the control circuit causes selection by the first multiplexer of the phase shifted clock as the transmit clock sent over the clock line if the system is configured for a delay on clock at source implementation.

Abstract: The present invention relates to the stereospecific synthesis of (R)-5-((E)-2-pyrrolidin-3-ylvinyl)pyrimidine, its salt forms, and novel polymorphic forms of these salts.

Abstract: Systems, apparatuses, and methods for performing efficient data transfer in a computing system are disclosed. A computing system includes multiple transmitters sending singled-ended data signals to multiple receivers. A termination voltage is generated and sent to the multiple receivers. The termination voltage is coupled to each of signal termination circuitry and signal sampling circuitry within each of the multiple receivers. Any change in the termination voltage affects the termination circuitry and affects comparisons performed by the sampling circuitry. Received signals are reconstructed at the receivers using the received signals, the signal termination circuitry and the signal sampling circuitry.

Abstract: The present invention relates to compounds that modulate nicotinic receptors as non-competitive antagonists, methods for use, and their pharmaceutical compositions.

Abstract: The present invention relates to the stereospecific synthesis of (R)-5-((E)-2-pyrrolidin-3-ylvinyl)pyrimidine, its salt forms, and novel polymorphic forms of these salts.

Abstract: Systems, apparatuses, and methods for performing efficient data transfer in a computing system are disclosed. A termination voltage generator includes an inverter-based chopper circuit, which uses a first group of an even number of serially connected inverters coupled between the output node of the chopper circuit and the gate terminal of an output pmos transistor. Additionally, a second group of an even number of serially connected inverters is coupled between the output node and the gate terminal of an output nmos transistor. A replica inverter includes two serially connected pmos transistors and two serially connected nmos transistors. Each of one pmos transistor and one nmos transistor receives a generated voltage set as the expected value of the termination voltage. Each of the other pmos transistor and nmos transistor receives an output based on a comparison between the expected value to the output of the replica inverter.

Abstract: Systems, apparatuses, and methods for performing efficient data transfer in a computing system are disclosed. A computing system includes multiple transmitters sending singled-ended data signals to multiple receivers. A termination voltage is generated and sent to the multiple receivers. The termination voltage is coupled to each of signal termination circuitry and signal sampling circuitry within each of the multiple receivers. Any change in the termination voltage affects the termination circuitry and affects comparisons performed by the sampling circuitry. Received signals are reconstructed at the receivers using the received signals, the signal termination circuitry and the signal sampling circuitry.

Abstract: Systems, apparatuses, and methods for performing efficient data transfer in a computing system are disclosed. A termination voltage generator includes an inverter-based chopper circuit, which uses a first group of an even number of serially connected inverters coupled between the output node of the chopper circuit and the gate terminal of an output pmos transistor. Additionally, a second group of an even number of serially connected inverters is coupled between the output node and the gate terminal of an output nmos transistor. A replica inverter includes two serially connected pmos transistors and two serially connected nmos transistors. Each of one pmos transistor and one nmos transistor receives a generated voltage set as the expected value of the termination voltage. Each of the other pmos transistor and nmos transistor receives an output based on a comparison between the expected value to the output of the replica inverter.

Abstract: A computer processing device for providing access to one or more electronic devices is provided. The device comprising processing means (103) configured to: determine a location identifier associated with a user login event; associate the location identifier with a user session identifier; and communicate (3013) the location identifier and associated user session identifier to an application (109).