Patents by Inventor Balwinder Singh

Balwinder Singh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10692545
    Abstract: Systems, apparatuses, and methods for performing efficient data transfer in a computing system are disclosed. A termination voltage generator includes an inverter-based chopper circuit, which uses a first group of an even number of serially connected inverters coupled between the output node of the chopper circuit and the gate terminal of an output pmos transistor. Additionally, a second group of an even number of serially connected inverters is coupled between the output node and the gate terminal of an output nmos transistor. A replica inverter includes two serially connected pmos transistors and two serially connected nmos transistors. Each of one pmos transistor and one nmos transistor receives a generated voltage set as the expected value of the termination voltage. Each of the other pmos transistor and nmos transistor receives an output based on a comparison between the expected value to the output of the replica inverter.
    Type: Grant
    Filed: September 24, 2018
    Date of Patent: June 23, 2020
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Milam Paraschou, Balwinder Singh, Gerald R. Talbot, Alushulla Jack Ambundo, Edoardo Prete, Thomas H. Likens, III, Michael A. Margules
  • Publication number: 20200098399
    Abstract: Systems, apparatuses, and methods for performing efficient data transfer in a computing system are disclosed. A termination voltage generator includes an inverter-based chopper circuit, which uses a first group of an even number of serially connected inverters coupled between the output node of the chopper circuit and the gate terminal of an output pmos transistor. Additionally, a second group of an even number of serially connected inverters is coupled between the output node and the gate terminal of an output nmos transistor. A replica inverter includes two serially connected pmos transistors and two serially connected nmos transistors. Each of one pmos transistor and one nmos transistor receives a generated voltage set as the expected value of the termination voltage. Each of the other pmos transistor and nmos transistor receives an output based on a comparison between the expected value to the output of the replica inverter.
    Type: Application
    Filed: September 24, 2018
    Publication date: March 26, 2020
    Inventors: Milam Paraschou, Balwinder Singh, Gerald R. Talbot, Alushulla Jack Ambundo, Edoardo Prete, Thomas H. Likens, III, Michael A. Margules
  • Publication number: 20200099406
    Abstract: Systems, apparatuses, and methods for performing efficient data transfer in a computing system are disclosed. A computing system includes multiple transmitters sending singled-ended data signals to multiple receivers. A termination voltage is generated and sent to the multiple receivers. The termination voltage is coupled to each of signal termination circuitry and signal sampling circuitry within each of the multiple receivers. Any change in the termination voltage affects the termination circuitry and affects comparisons performed by the sampling circuitry. Received signals are reconstructed at the receivers using the received signals, the signal termination circuitry and the signal sampling circuitry.
    Type: Application
    Filed: September 24, 2018
    Publication date: March 26, 2020
    Inventors: Balwinder Singh, Milam Paraschou, Chad S. Gallun, Jeffrey Cooper, Dean E. Gonzales, Alushulla Jack Ambundo, Thomas H. Likens, III, Gerald R. Talbot
  • Publication number: 20200045547
    Abstract: A computer processing device for providing access to one or more electronic devices is provided. The device comprising processing means (103) configured to: determine a location identifier associated with a user login event; associate the location identifier with a user session identifier; and communicate (3013) the location identifier and associated user session identifier to an application (109).
    Type: Application
    Filed: March 7, 2018
    Publication date: February 6, 2020
    Inventors: Balwinder SINGH ATWAL, Matthys Christiaan SERFONTEIN, Shamus Edward GLEASON, Mian TAMUR UL HAQ, Eric Richard TORBENSON
  • Publication number: 20190323583
    Abstract: A disconnect assembly for an input shaft and an output shaft includes a sleeve configured to be disposed about the input shaft and the output shaft. A cam is disposed about the sleeve. A cam follower is configured to contact the cam. An interfacing element is configured to operatively interface the sleeve, the input shaft, and the output shaft. The sleeve, the cam, the cam follower, and the interfacing element are configured to move between a respective connect position and a respective disconnect position.
    Type: Application
    Filed: April 23, 2018
    Publication date: October 24, 2019
    Applicant: HONEYWELL INTERNATIONAL INC.
    Inventors: Jens Gehrke, Cesar Abraham Davila, Arturo Maceda, Tom Phielix, Balwinder Singh Birdi
  • Patent number: 10421745
    Abstract: The present invention relates to the stereospecific synthesis of (R)-5-((E)-2-pyrrolidin-3-ylvinyl)pyrimidine, its salt forms, and novel polymorphic forms of these salts.
    Type: Grant
    Filed: April 25, 2018
    Date of Patent: September 24, 2019
  • Patent number: 10393804
    Abstract: A test circuit is operable in ATPG mode and LBIST mode. The test circuit includes a clock selection circuit. The clock selection circuit includes clock logic circuitry to receive an LBIST mode signal and an ATPG mode signal and to generate an indication of whether the test circuit is operating in either the ATPG mode or the LBIST mode, a multiplexing circuit to receive an ATPG clock and a functional clock as input and output a selected one of the ATPG clock and the functional clock, and a clock gate circuit enabled in response to enable signals. The enable signals are an inverse of a selected one of the ATPG clock and the functional clock. The clock gate circuit receives the indication of whether the test circuit is operating in either the ATPG mode or the LBIST mode and generates a test clock as a function of the indication.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: August 27, 2019
    Assignee: STMicroelectronics International N.V.
    Inventors: Venkata Narayanan Srinivasan, Nimit Endlay, Balwinder Singh Soni
  • Publication number: 20190254991
    Abstract: The present invention relates to compounds that modulate nicotinic receptors as non-competitive antagonists, methods for use, and their pharmaceutical compositions.
    Type: Application
    Filed: April 15, 2019
    Publication date: August 22, 2019
    Inventors: Srinivasa Rao Akireddy, Balwinder Singh Bhatti, Ronald Joseph Heemstra, Jason Speake, Daniel Yohannes, Matt S. Melvin, Yunde Xiao
  • Patent number: 10258582
    Abstract: The present invention relates to compounds that modulate nicotinic receptors as non-competitive antagonists, methods for their synthesis, methods for use, and their pharmaceutical compositions.
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: April 16, 2019
    Assignee: Catalyst BioSciences, Inc.
    Inventors: Srinivasa Rao Akireddy, Balwinder Singh Bhatti, Ronald Joseph Heemstra, Jason Speake, Daniel Yohannes, Matt S. Melvin, Yunde Xiao
  • Patent number: 10228420
    Abstract: A test circuit receives LBIST and ATPG mode signals, and generates a first output as high when in ATPG or LBIST, and a second output as low when in ATPG or LBIST. A multiplexing circuit receives an ATPG clock and functional clock, and outputs one. A clock gate circuit includes a first latch receiving the second output, and an enable input receiving an inverse of the ATPG clock or functional clock. A second latch receives the first output, and has an enable input receiving the inverse of the ATPG clock or functional clock. The clock gate circuit includes a first AND gate receiving output of the first latch and ATPG clock or functional clock, a second AND gate receiving output of the second latch and the ATPG clock or LBIST clock, and an OR gate receiving outputs of the first and second AND gates, and generating a test clock.
    Type: Grant
    Filed: September 19, 2016
    Date of Patent: March 12, 2019
    Assignee: STMicroelectronics International N.V.
    Inventors: Venkata Narayanan Srinivasan, Nimit Endlay, Balwinder Singh Soni
  • Publication number: 20190071428
    Abstract: The present invention relates to the stereospecific synthesis of (R)-5-((E)-2-pyrrolidin-3-ylvinyl)pyrimidine, its salt forms, and novel polymorphic forms of these salts.
    Type: Application
    Filed: April 25, 2018
    Publication date: March 7, 2019
  • Publication number: 20190064268
    Abstract: A test circuit is operable in ATPG mode and LBIST mode. The test circuit includes a clock selection circuit. The clock selection circuit includes clock logic circuitry to receive an LBIST mode signal and an ATPG mode signal and to generate an indication of whether the test circuit is operating in either the ATPG mode or the LBIST mode, a multiplexing circuit to receive an ATPG clock and a functional clock as input and output a selected one of the ATPG clock and the functional clock, and a clock gate circuit enabled in response to enable signals. The enable signals are an inverse of a selected one of the ATPG clock and the functional clock. The clock gate circuit receives the indication of whether the test circuit is operating in either the ATPG mode or the LBIST mode and generates a test clock as a function of the indication.
    Type: Application
    Filed: October 25, 2018
    Publication date: February 28, 2019
    Applicant: STMicroelectronics International N.V.
    Inventors: Venkata Narayanan Srinivasan, Nimit Endlay, Balwinder Singh Soni
  • Publication number: 20180271806
    Abstract: The present invention relates to compounds that modulate nicotinic receptors as non-competitive antagonists, methods for their synthesis, methods for use, and their pharmaceutical compositions.
    Type: Application
    Filed: January 23, 2018
    Publication date: September 27, 2018
    Inventors: Srinivasa Rao Akireddy, Balwinder Singh Bhatti, Ronald Joseph Heemstra, Jason Speake, Daniel Yohannes, Matt S. Melvin, Yunde Xiao
  • Patent number: 9981949
    Abstract: The present invention relates to the stereospecific synthesis of (R)-5-((E)-2-pyrrolidin-3-ylvinyl)pyrimidine, its salt forms, and novel polymorphic forms of these salts.
    Type: Grant
    Filed: November 17, 2016
    Date of Patent: May 29, 2018
  • Publication number: 20180080987
    Abstract: A test circuit receives LBIST and ATPG mode signals, and generates a first output as high when in ATPG or LBIST, and a second output as low when in ATPG or LBIST. A multiplexing circuit receives an ATPG clock and functional clock, and outputs one. A clock gate circuit includes a first latch receiving the second output, and an enable input receiving an inverse of the ATPG clock or functional clock. A second latch receives the first output, and has an enable input receiving the inverse of the ATPG clock or functional clock. The clock gate circuit includes a first AND gate receiving output of the first latch and ATPG clock or functional clock, a second AND gate receiving output of the second latch and the ATPG clock or LBIST clock, and an OR gate receiving outputs of the first and second AND gates, and generating a test clock.
    Type: Application
    Filed: September 19, 2016
    Publication date: March 22, 2018
    Applicant: STMicroelectronics International N.V.
    Inventors: Venkata Narayanan Srinivasan, Nimit Endlay, Balwinder Singh Soni
  • Publication number: 20170260167
    Abstract: The present invention relates to the stereospecific synthesis of (R)-5-((E)-2-pyrrolidin-3-ylvinyl)pyrimidine, its salt forms, and novel polymorphic forms of these salts.
    Type: Application
    Filed: November 17, 2016
    Publication date: September 14, 2017
  • Patent number: 9664232
    Abstract: A generator assembly may include a bearing liner and a bearing retainer configured to reduce vibration response in a bearing assembly under high frequency operation of a rotor. The bearing liner may be configured to provide a clearance between the bearing assembly and an adjacent housing/bearing liner to prevent high vibration output from the bearing assembly on for example, the rotor shaft. The bearing retainer may include a recess to accommodate axial movement of the bearing assembly in response to rotation of the rotor. In some embodiments, the bearing retainer may include a dampener to dampen contact of the bearing assembly with the retainer.
    Type: Grant
    Filed: July 18, 2013
    Date of Patent: May 30, 2017
    Assignee: HONEYWELL INTERNATIONAL INC.
    Inventors: Balwinder Singh Birdi, Simon Waddell, William Scherzinger, David Windish, Robert Cisneroz
  • Publication number: 20170071878
    Abstract: The present invention relates to compounds that modulate nicotinic receptors as non-competitive antagonists, methods for their synthesis, methods for use, and their pharmaceutical compositions.
    Type: Application
    Filed: November 23, 2016
    Publication date: March 16, 2017
    Inventors: Srinivasa Rao Akireddy, Balwinder Singh Bhatti, Ronald Joseph Heemstra, Jason Speake, Daniel Yohannes, Matt S. Melvin, Yunde Xiao
  • Patent number: 9532974
    Abstract: The present invention relates to compounds that modulate nicotinic receptors as non-competitive antagonists, methods for their synthesis, methods for use, and their pharmaceutical compositions.
    Type: Grant
    Filed: August 27, 2015
    Date of Patent: January 3, 2017
    Assignee: Targacept, Inc.
    Inventors: Srinivasa Rao Akireddy, Balwinder Singh Bhatti, Ronald Joseph Heemstra, Matt S. Melvin, Jason Speake, Yunde Xiao, Daniel Yohannes
  • Publication number: 20160046609
    Abstract: The present invention relates to the stereospecific synthesis of (R)-5-((E)-2-pyrrolidin-3-ylvinyl)pyrimidine, its salt forms, and novel polymorphic forms of these salts.
    Type: Application
    Filed: August 21, 2015
    Publication date: February 18, 2016