Patents by Inventor Baosuo Zhou

Baosuo Zhou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10784086
    Abstract: Methods of etching cobalt on substrates are provided. Some methods involve exposing the substrate to a boron-containing halide gas and an additive, and exposing the substrate to an activation gas and a plasma. Additives improve selectively depositing a thicker layer of a boron-containing halide material on a surface of a mask than on a surface of a metal. Additives include H2, CH4, CF4, NF3, and Cl2. Boron-containing halide gases include BCl3, BBr3, BF3, and BI3. Exposures may be performed in two or more cycles, with variations in durations and/or bias power for each exposure in the two or more cycles.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: September 22, 2020
    Assignee: LAM RESEARCH CORPORATION
    Inventors: Jialing Yang, Baosuo Zhou, Meihua Shen, Thorsten Lill, John Hoang
  • Publication number: 20200203171
    Abstract: A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be etched is provided, then an initial sacrificial patterning layer, for example formed using optical lithography, is formed over the layer to be etched. Depending on the embodiment, the patterning layer may be trimmed, then a series of spacer layers formed and etched. The number of spacer layers and their target dimensions depends on the desired increase in feature density. An in-process semiconductor device and electronic system is also described.
    Type: Application
    Filed: March 2, 2020
    Publication date: June 25, 2020
    Applicant: Micron Technology, Inc.
    Inventors: Baosuo Zhou, Mirzafer K. Abatchev, Ardavan Niroomand, Paul A. Morgan, Shuang Meng, Joseph Neil Greeley, Brian J. Coppa
  • Patent number: 10607844
    Abstract: A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be etched is provided, then an initial sacrificial patterning layer, for example formed using optical lithography, is formed over the layer to be etched. Depending on the embodiment, the patterning layer may be trimmed, then a series of spacer layers formed and etched. The number of spacer layers and their target dimensions depends on the desired increase in feature density. An in-process semiconductor device and electronic system is also described.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: March 31, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Baosuo Zhou, Mirzafer K. Abatchev, Ardavan Niroomand, Paul A. Morgan, Shuang Meng, Joseph Neil Greeley, Brian J. Coppa
  • Patent number: 10096483
    Abstract: A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be etched is provided, then an initial sacrificial patterning layer, for example formed using optical lithography, is formed over the layer to be etched. Depending on the embodiment, the patterning layer may be trimmed, then a series of spacer layers formed and etched. The number of spacer layers and their target dimensions depends on the desired increase in feature density. An in-process semiconductor device and electronic system is also described.
    Type: Grant
    Filed: August 18, 2017
    Date of Patent: October 9, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Baosuo Zhou, Mirzafer K. Abatchev, Ardavan Niroomand, Paul A. Morgan, Shuang Meng, Joseph Neil Greeley, Brian J. Coppa
  • Publication number: 20180286693
    Abstract: A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be etched is provided, then an initial sacrificial patterning layer, for example formed using optical lithography, is formed over the layer to be etched. Depending on the embodiment, the patterning layer may be trimmed, then a series of spacer layers formed and etched. The number of spacer layers and their target dimensions depends on the desired increase in feature density. An in-process semiconductor device and electronic system is also described.
    Type: Application
    Filed: May 30, 2018
    Publication date: October 4, 2018
    Applicant: Micron Technology, Inc.
    Inventors: Baosuo Zhou, Mirzafer K. Abatchev, Ardavan Niroomand, Paul A. Morgan, Shuang Meng, Joseph Neil Greeley, Brian J. Coppa
  • Publication number: 20180102236
    Abstract: Methods of etching cobalt on substrates are provided. Some methods involve exposing the substrate to a boron-containing halide gas and an additive, and exposing the substrate to an activation gas and a plasma. Additives improve selectively depositing a thicker layer of a boron-containing halide material on a surface of a mask than on a surface of a metal. Additives include H2, CH4, CF4, NF3, and Cl2. Boron-containing halide gases include BCl3, BBr3, BF3, and Bl3. Exposures may be performed in two or more cycles, with variations in durations and/or bias power for each exposure in the two or more cycles.
    Type: Application
    Filed: November 28, 2017
    Publication date: April 12, 2018
    Applicant: Lam Research Corporation
    Inventors: Jialing Yang, Baosuo Zhou, Meihua Shen, Thorsten Lill, John Hoang
  • Patent number: 9870899
    Abstract: Methods of etching cobalt on substrates are provided. Some methods involve exposing the substrate to a boron-containing halide gas and an additive, and exposing the substrate to an activation gas and a plasma. Additives improve selectively depositing a thicker layer of a boron-containing halide material on a surface of a mask than on a surface of a metal. Additives include H2, CH4, CF4, NF3, and Cl2. Boron-containing halide gases include BCl3, BBr3, BF3, and BI3. Exposures may be performed in two or more cycles, with variations in durations and/or bias power for each exposure in the two or more cycles.
    Type: Grant
    Filed: June 24, 2015
    Date of Patent: January 16, 2018
    Assignee: LAM RESEARCH CORPORATION
    Inventors: Jialing Yang, Baosuo Zhou, Meihua Shen, Thorsten Lill, John Hoang
  • Publication number: 20170372913
    Abstract: A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be etched is provided, then an initial sacrificial patterning layer, for example formed using optical lithography, is formed over the layer to be etched. Depending on the embodiment, the patterning layer may be trimmed, then a series of spacer layers formed and etched. The number of spacer layers and their target dimensions depends on the desired increase in feature density. An in-process semiconductor device and electronic system is also described.
    Type: Application
    Filed: August 18, 2017
    Publication date: December 28, 2017
    Applicant: Micron Technology, Inc.
    Inventors: Baosuo Zhou, Mirzafer K. Abatchev, Ardavan Niroomand, Paul A. Morgan, Shuang Meng, Joseph Neil Greeley, Brian J. Coppa
  • Patent number: 9761457
    Abstract: A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be etched is provided, then an initial sacrificial patterning layer, for example formed using optical lithography, is formed over the layer to be etched. Depending on the embodiment, the patterning layer may be trimmed, then a series of spacer layers formed and etched. The number of spacer layers and their target dimensions depends on the desired increase in feature density. An in-process semiconductor device and electronic system is also described.
    Type: Grant
    Filed: March 21, 2016
    Date of Patent: September 12, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Baosuo Zhou, Mirzafer K. Abatchev, Ardavan Niroomand, Paul A. Morgan, Shuang Meng, Joseph Neil Greeley, Brian J. Coppa
  • Patent number: 9679781
    Abstract: Various pattern transfer and etching steps can be used to create features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form superimposed, pitch-reduced patterns of crossing elongate features that can be consolidated into a single layer. Planarizing techniques using a filler layer and a protective layer are disclosed. Portions of an integrated circuit having different heights can be etched to a common plane.
    Type: Grant
    Filed: April 13, 2015
    Date of Patent: June 13, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Mirzafer Abatchev, David Wells, Baosuo Zhou, Krupakar Murali Subramanian
  • Patent number: 9589853
    Abstract: A method of planarizing an upper surface of a semiconductor substrate in a plasma etch chamber comprises supporting the substrate on a support surface of a substrate support assembly that includes an array of independently controlled thermal control elements therein which are operable to control the spatial and temporal temperature of the support surface of the substrate support assembly to form independently controllable heater zones which are formed to correspond to a desired temperature profile across the upper surface of the semiconductor substrate. The etch rate across the upper surface of the semiconductor substrate during plasma etching depends on a localized temperature thereof wherein the desired temperature profile is determined such that the upper surface of the semiconductor substrate is planarized within a predetermined time. The substrate is plasma etched for the predetermined time thereby planarizing the upper surface of the substrate.
    Type: Grant
    Filed: July 22, 2014
    Date of Patent: March 7, 2017
    Assignee: LAM RESEARCH CORPORATION
    Inventors: Monica Titus, Gowri Kamarthy, Harmeet Singh, Yoshie Kimura, Meihua Shen, Baosuo Zhou, Yifeng Zhou, John Hoang
  • Patent number: 9570320
    Abstract: A method of opening a barrier film below copper structures in a stack is provided. A pulsed gas is provided into a plasma processing chamber, wherein the providing the pulsed gas comprises providing a pulsed H2 containing gas and providing a pulsed halogen containing gas, wherein the pulsed H2 containing gas and the pulsed halogen containing gas are pulsed out of phase, and wherein the pulsed H2 containing gas has an H2 high flow period and the pulsed halogen containing gas has a halogen containing gas high flow period, wherein the H2 high flow period is greater than the halogen containing gas high flow period. The pulsed gas is formed into a plasma. The copper structures and the barrier film are exposed to the plasma, which etches the barrier film. In another embodiment, a wet and dry cyclical process may be used.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: February 14, 2017
    Assignee: Lam Research Corporation
    Inventors: Meihua Shen, Ji Zhu, Shuogang Huang, Baosuo Zhou, John Hoang, Prithu Sharma, Thorsten Lill
  • Publication number: 20160314985
    Abstract: Methods of etching cobalt on substrates are provided. Some methods involve exposing the substrate to a boron-containing halide gas and an additive, and exposing the substrate to an activation gas and a plasma. Additives improve selectively depositing a thicker layer of a boron-containing halide material on a surface of a mask than on a surface of a metal. Additives include H2, CH4, CF4, NF3, and Cl2. Boron-containing halide gases include BCl3, BBr3, BF3, and BI3. Exposures may be performed in two or more cycles, with variations in durations and/or bias power for each exposure in the two or more cycles.
    Type: Application
    Filed: June 24, 2015
    Publication date: October 27, 2016
    Inventors: Jialing Yang, Baosuo Zhou, Meihua Shen, Thorsten Lill, John Hoang
  • Publication number: 20160203993
    Abstract: A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be etched is provided, then an initial sacrificial patterning layer, for example formed using optical lithography, is formed over the layer to be etched. Depending on the embodiment, the patterning layer may be trimmed, then a series of spacer layers formed and etched. The number of spacer layers and their target dimensions depends on the desired increase in feature density. An in-process semiconductor device and electronic system is also described.
    Type: Application
    Filed: March 21, 2016
    Publication date: July 14, 2016
    Inventors: Baosuo Zhou, Mirzafer K. Abatchev, Ardavan Niroomand, Paul A. Morgan, Shuang Meng, Joseph Neil Greeley, Brian J. Coppa
  • Patent number: 9330934
    Abstract: Methods of forming a pattern on a substrate include forming carbon-comprising material over a base material, and spaced first features over the carbon-comprising material. Etching is conducted only partially into the carbon-comprising material and spaced second features are formed within the carbon-comprising material which comprise the partially etched carbon-comprising material. Spacers can be formed along sidewalls of the spaced second features. The carbon-comprising material can be etched through to the base material using the spacers as a mask. Spaced third features can be formed which comprise the anisotropically etched spacers and the carbon-comprising material.
    Type: Grant
    Filed: May 18, 2009
    Date of Patent: May 3, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Baosuo Zhou, Alex J. Schrinsky
  • Publication number: 20160104630
    Abstract: A method of opening a barrier film below copper structures in a stack is provided. A pulsed gas is provided into a plasma processing chamber, wherein the providing the pulsed gas comprises providing a pulsed H2 containing gas and providing a pulsed halogen containing gas, wherein the pulsed H2 containing gas and the pulsed halogen containing gas are pulsed out of phase, and wherein the pulsed H2 containing gas has an H2 high flow period and the pulsed halogen containing gas has a halogen containing gas high flow period, wherein the H2 high flow period is greater than the halogen containing gas high flow period. The pulsed gas is formed into a plasma. The copper structures and the barrier film are exposed to the plasma, which etches the barrier film. In another embodiment, a wet and dry cyclical process may be used.
    Type: Application
    Filed: December 22, 2014
    Publication date: April 14, 2016
    Inventors: Meihua SHEN, Ji ZHU, Shuogang HUANG, Baosuo ZHOU, John HOANG, Prithu SHARMA, Thorsten LILL
  • Patent number: 9305782
    Abstract: A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be etched is provided, then an initial sacrificial patterning layer, for example formed using optical lithography, is formed over the layer to be etched. Depending on the embodiment, the patterning layer may be trimmed, then a series of spacer layers formed and etched. The number of spacer layers and their target dimensions depends on the desired increase in feature density. An in-process semiconductor device and electronic system is also described.
    Type: Grant
    Filed: October 6, 2014
    Date of Patent: April 5, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Baosuo Zhou, Mirzafer K. Abatchev, Ardavan Niroomand, Paul A. Morgan, Shuang Meng, Joseph Neil Greely, Brian J. Coppa
  • Patent number: 9184159
    Abstract: A method for fabricating a semiconductor device comprises patterning a layer of photoresist material to form a plurality of mandrels. The method further comprises depositing an oxide material over the plurality of mandrels by an atomic layer deposition (ALD) process. The method further comprises anisotropically etching the oxide material from exposed horizontal surfaces. The method further comprises selectively etching photoresist material.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: November 10, 2015
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Ardavan Niroomand, Baosuo Zhou, Ramakanth Alapati
  • Publication number: 20150287610
    Abstract: Various pattern transfer and etching steps can be used to create features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form superimposed, pitch-reduced patterns of crossing elongate features that can be consolidated into a single layer. Planarizing techniques using a filler layer and a protective layer are disclosed. Portions of an integrated circuit having different heights can be etched to a common plane.
    Type: Application
    Filed: April 13, 2015
    Publication date: October 8, 2015
    Inventors: MIRZAFER ABATCHEV, DAVID WELLS, BAOSUO ZHOU, KRUPAKAR MURALI SUBRAMANIAN
  • Publication number: 20150249016
    Abstract: A method of planarizing an upper surface of a semiconductor substrate in a plasma etch chamber comprises supporting the substrate on a support surface of a substrate support assembly that includes an array of independently controlled thermal control elements therein which are operable to control the spatial and temporal temperature of the support surface of the substrate support assembly to form independently controllable heater zones which are formed to correspond to a desired temperature profile across the upper surface of the semiconductor substrate. The etch rate across the upper surface of the semiconductor substrate during plasma etching depends on a localized temperature thereof wherein the desired temperature profile is determined such that the upper surface of the semiconductor substrate is planarized within a predetermined time. The substrate is plasma etched for the predetermined time thereby planarizing the upper surface of the substrate.
    Type: Application
    Filed: July 22, 2014
    Publication date: September 3, 2015
    Inventors: Monica Titus, Gowri Kamarthy, Harmeet Singh, Yoshie Kimura, Meihua Shen, Baosuo Zhou, Yifeng Zhou, John Hoang