Patents by Inventor Baosuo Zhou
Baosuo Zhou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20120244708Abstract: Some embodiments include methods of forming openings. For instance, a construction may have a material over a plurality of electrically conductive lines. A plurality of annular features may be formed over the material, with the annular features crossing the lines. A patterned mask may be formed over the annular features, with the patterned mask leaving segments of the annular features exposed through a window in the patterned mask. The exposed segments of the annular features may define a plurality of openings, and such openings may be transferred into the material to form openings extending to the electrically conductive lines.Type: ApplicationFiled: June 7, 2012Publication date: September 27, 2012Applicant: MICRON TECHNOLOGY, INC.Inventors: Vishal Sipani, Baosuo Zhou, Ming-Chuan Yang
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Patent number: 8216939Abstract: Some embodiments include methods of forming openings. For instance, a construction may have a material over a plurality of electrically conductive lines. A plurality of annular features may be formed over the material, with the annular features crossing the lines. A patterned mask may be formed over the annular features, with the patterned mask leaving segments of the annular features exposed through a window in the patterned mask. The exposed segments of the annular features may define a plurality of openings, and such openings may be transferred into the material to form openings extending to the electrically conductive lines.Type: GrantFiled: August 20, 2010Date of Patent: July 10, 2012Assignee: Micron Technology, Inc.Inventors: Vishal Sipani, Baosuo Zhou, Ming-Chuan Yang
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Publication number: 20120045896Abstract: Some embodiments include methods of forming openings. For instance, a construction may have a material over a plurality of electrically conductive lines. A plurality of annular features may be formed over the material, with the annular features crossing the lines. A patterned mask may be formed over the annular features, with the patterned mask leaving segments of the annular features exposed through a window in the patterned mask. The exposed segments of the annular features may define a plurality of openings, and such openings may be transferred into the material to form openings extending to the electrically conductive lines.Type: ApplicationFiled: August 20, 2010Publication date: February 23, 2012Inventors: Vishal Sipani, Baosuo Zhou, Ming-Chuan Yang
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Publication number: 20110316114Abstract: A method for fabricating a semiconductor device comprises patterning a layer of photoresist material to form a plurality of mandrels. The method further comprises depositing an oxide material over the plurality of mandrels by an atomic layer deposition (ALD) process. The method further comprises anisotropically etching the oxide material from exposed horizontal surfaces. The method further comprises selectively etching photoresist material.Type: ApplicationFiled: September 12, 2011Publication date: December 29, 2011Applicant: Micron Technology, Inc.Inventors: Ardavan Niroomand, Baosuo Zhou, Ramakanth Alapati
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Publication number: 20110294294Abstract: Various pattern transfer and etching steps can be used to create features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form superimposed, pitch-reduced patterns of crossing elongate features that can be consolidated into a single layer. Planarizing techniques using a filler layer and a protective layer are disclosed. Portions of an integrated circuit having different heights can be etched to a common plane.Type: ApplicationFiled: August 11, 2011Publication date: December 1, 2011Applicant: Micron Technology, Inc.Inventors: Mirzafer Abatchev, David Wells, Baosuo Zhou, Krupakar M. Subramanian
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Publication number: 20110244674Abstract: A method of forming a plurality of spaced features includes forming sacrificial hardmask material over underlying material. The sacrificial hardmask material has at least two layers of different composition. Portions of the sacrificial hardmask material are removed to form a mask over the underlying material. Individual features of the mask have at least two layers of different composition, with one of the layers of each of the individual features having a tensile intrinsic stress of at least 400.0 MPa. The individual features have a total tensile intrinsic stress greater than 0.0 MPa. The mask is used while etching into the underlying material to form a plurality of spaced features comprising the underlying material. Other implementations are disclosed.Type: ApplicationFiled: March 30, 2010Publication date: October 6, 2011Inventors: Farrell Good, Baosuo Zhou, Xiaolong Fang, Fatma Arzum Simsek-Ege
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Patent number: 8030217Abstract: A method for fabricating a semiconductor device comprises patterning a layer of photoresist material to form a plurality of mandrels. The method further comprises depositing an oxide material over the plurality of mandrels by an atomic layer deposition (ALD) process. The method further comprises anisotropically etching the oxide material from exposed horizontal surfaces. The method further comprises selectively etching photoresist material.Type: GrantFiled: April 30, 2010Date of Patent: October 4, 2011Assignee: Micron Technology, Inc.Inventors: Ardavan Niroomand, Baosuo Zhou, Ramakanth Alapati
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Patent number: 8011090Abstract: Various pattern transfer and etching steps can be used to create features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form superimposed, pitch-reduced patterns of crossing elongate features that can be consolidated into a single layer. Planarizing techniques using a filler layer and a protective layer are disclosed. Portions of an integrated circuit having different heights can be etched to a common plane.Type: GrantFiled: May 19, 2008Date of Patent: September 6, 2011Assignee: Micron Technology, Inc.Inventors: Mirzafer Abatchev, David Wells, Baosuo Zhou, Krupakar M. Subramanian
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Patent number: 7910483Abstract: Methods of etching substrates employing a trim process for critical dimension control for integrated circuits are disclosed. In one embodiment, the method of etching includes providing a first hard mask layer over a target layer; providing a second hard mask layer over the first hard mask layer; providing a photoresist layer over the second hard mask layer; forming a pattern in the photoresist layer; transferring the pattern into the second hard mask layer; and trimming the second hard mask layer with the photoresist layer on top of the second hard mask layer. The top surface of the second hard mask layer is protected by the photoresist and the substrate is protected by the overlying first hard mask layer during the trim etch, which can therefore be aggressive.Type: GrantFiled: February 2, 2010Date of Patent: March 22, 2011Assignee: Micron Technology, Inc.Inventors: Mirzafer K Abatchev, Krupaker Murali Subramanian, Baosuo Zhou
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Patent number: 7902074Abstract: A method for fabricating a semiconductor device comprises patterning a layer of photoresist material to form a plurality of mandrels in a device array region. The method further comprises depositing an oxide material over the plurality of mandrels and over a device peripheral region. The method further comprises forming a pattern of photoresist material over the oxide material in the device peripheral region. The method further comprises anisotropically etching the oxide material from exposed horizontal surfaces in the device array region. The method further comprises selectively etching photoresist material from the device array region and from the device peripheral region.Type: GrantFiled: April 7, 2006Date of Patent: March 8, 2011Assignee: Micron Technology, Inc.Inventors: Ardavan Niroomand, Baosuo Zhou, Ramakanth Alapati
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Publication number: 20110006402Abstract: A method of forming features on a target layer. The features have a critical dimension that is triple- or quadruple-reduced compared to the critical dimension of portions of a resist layer used as a mask. An intermediate layer is deposited over a target layer and the resist layer is formed over the intermediate layer. After patterning the resist layer, first spacers are formed on sidewalls of remaining portions of the resist layer, masking portions of the intermediate layer. Second spacers are formed on sidewalls of the portions of the intermediate layer. After removing the portions of the intermediate layer, the second spacers are used as a mask to foil the features on the target layer. A partially fabricated integrated circuit device is also disclosed.Type: ApplicationFiled: September 22, 2010Publication date: January 13, 2011Applicant: MICRON TECHNOLOGY, INC.Inventor: Baosuo Zhou
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Publication number: 20100291771Abstract: Methods of forming a pattern on a substrate include forming carbon-comprising material over a base material, and spaced first features over the carbon-comprising material. Etching is conducted only partially into the carbon-comprising material and spaced second features are formed within the carbon-comprising material which comprise the partially etched carbon-comprising material. Spacers can be formed along sidewalls of the spaced second features. The carbon-comprising material can be etched through to the base material using the spacers as a mask. Spaced third features can be formed which comprise the anisotropically etched spacers and the carbon-comprising material.Type: ApplicationFiled: May 18, 2009Publication date: November 18, 2010Inventors: Baosuo Zhou, Alex J. Schrinsky
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Patent number: 7807575Abstract: A method of forming features on a target layer. The features have a critical dimension that is triple- or quadruple-reduced compared to the critical dimension of portions of a resist layer used as a mask. An intermediate layer is deposited over a target layer and the resist layer is formed over the intermediate layer. After patterning the resist layer, first spacers are formed on sidewalls of remaining portions of the resist layer, masking portions of the intermediate layer. Second spacers are formed on sidewalls of the portions of the intermediate layer. After removing the portions of the intermediate layer, the second spacers are used as a mask to form the features on the target layer. A partially fabricated integrated circuit device is also disclosed.Type: GrantFiled: November 29, 2006Date of Patent: October 5, 2010Assignee: Micron Technology, Inc.Inventor: Baosuo Zhou
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Publication number: 20100216307Abstract: A method for fabricating a semiconductor device comprises patterning a layer of photoresist material to form a plurality of mandrels. The method further comprises depositing an oxide material over the plurality of mandrels by an atomic layer deposition (ALD) process. The method further comprises anisotropically etching the oxide material from exposed horizontal surfaces. The method further comprises selectively etching photoresist material.Type: ApplicationFiled: April 30, 2010Publication date: August 26, 2010Applicant: Micron Technology, Inc.Inventors: Ardavan Niroomand, Baosuo Zhou, Ramakanth Alapati
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Publication number: 20100173498Abstract: Methods of etching substrates employing a trim process for critical dimension control for integrated circuits are disclosed. In one embodiment, the method of etching includes providing a first hard mask layer over a target layer; providing a second hard mask layer over the first hard mask layer; providing a photoresist layer over the second hard mask layer; forming a pattern in the photoresist layer; transferring the pattern into the second hard mask layer; and trimming the second hard mask layer with the photoresist layer on top of the second hard mask layer. The top surface of the second hard mask layer is protected by the photoresist and the substrate is protected by the overlying first hard mask layer during the trim etch, which can therefore be aggressive.Type: ApplicationFiled: February 2, 2010Publication date: July 8, 2010Applicant: MICRON TECHNOLOGY, INC.Inventors: Mirzafer K. Abatchev, Krupaker Murali Subramanian, Baosuo Zhou
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Patent number: 7732343Abstract: A method for fabricating a semiconductor device comprises patterning a layer of photoresist material to form a plurality of mandrels. The method further comprises depositing an oxide material over the plurality of mandrels by an atomic layer deposition (ALD) process. The method further comprises anisotropically etching the oxide material from exposed horizontal surfaces. The method further comprises selectively etching photoresist material.Type: GrantFiled: May 3, 2007Date of Patent: June 8, 2010Assignee: Micron Technology, Inc.Inventors: Ardavan Niroomand, Baosuo Zhou, Ramakanth Alapati
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Publication number: 20100112818Abstract: Methods are disclosed, such as those involving increasing the density of isolated features in an integrated circuit. In one or more embodiments, a method is provided for forming an integrated circuit with a pattern of isolated features having a final density of isolated features that is greater than a starting density of isolated features in the integrated circuit by a multiple of two or more. The method can include forming a pattern of pillars having a density X, and forming a pattern of holes amongst the pillars, the holes having a density at least X. The pillars can be selectively removed to form a pattern of holes having a density at least 2X. In some embodiments, plugs can be formed in the pattern of holes, such as by epitaxial deposition on the substrate, in order to provide a pattern of pillars having a density 2X. In other embodiments, the pattern of holes can be transferred to the substrate by etching.Type: ApplicationFiled: January 13, 2010Publication date: May 6, 2010Applicant: MICRON TECHNOLOGY, INC.Inventors: Baosuo Zhou, Gurtej S. Sandhu, Ardavan Niroomand
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Patent number: 7662718Abstract: Methods of etching substrates employing a trim process for critical dimension control for integrated circuits are disclosed. In one embodiment, the method of etching includes providing a first hard mask layer over a target layer; providing a second hard mask layer over the first hard mask layer; providing a photoresist layer over the second hard mask layer; forming a pattern in the photoresist layer; transferring the pattern into the second hard mask layer; and trimming the second hard mask layer with the photoresist layer on top of the second hard mask layer. The top surface of the second hard mask layer is protected by the photoresist and the substrate is protected by the overlying first hard mask layer during the trim etch, which can therefore be aggressive.Type: GrantFiled: March 9, 2006Date of Patent: February 16, 2010Assignee: Micron Technology, Inc.Inventors: Mirzafer K. Abatchev, Krupakar Murali Subramanian, Baosuo Zhou
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Patent number: 7659208Abstract: Methods are disclosed, such as those involving increasing the density of isolated features in an integrated circuit. In one or more embodiments, a method is provided for forming an integrated circuit with a pattern of isolated features having a final density of isolated features that is greater than a starting density of isolated features in the integrated circuit by a multiple of two or more. The method can include forming a pattern of pillars having a density X, and forming a pattern of holes amongst the pillars, the holes having a density at least X. The pillars can be selectively removed to form a pattern of holes having a density at least 2X. In some embodiments, plugs can be formed in the pattern of holes, such as by epitaxial deposition on the substrate, in order to provide a pattern of pillars having a density 2X. In other embodiments, the pattern of holes can be transferred to the substrate by etching.Type: GrantFiled: December 6, 2007Date of Patent: February 9, 2010Assignee: Micron Technology, IncInventors: Baosuo Zhou, Gurtej S. Sandhu, Ardavan Niroomand
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Publication number: 20090149026Abstract: Methods are disclosed, such as those involving increasing the density of isolated features in an integrated circuit. In one or more embodiments, a method is provided for forming an integrated circuit with a pattern of isolated features having a final density of isolated features that is greater than a starting density of isolated features in the integrated circuit by a multiple of two or more. The method can include forming a pattern of pillars having a density X, and forming a pattern of holes amongst the pillars, the holes having a density at least X. The pillars can be selectively removed to form a pattern of holes having a density at least 2X. In some embodiments, plugs can be formed in the pattern of holes, such as by epitaxial deposition on the substrate, in order to provide a pattern of pillars having a density 2X. In other embodiments, the pattern of holes can be transferred to the substrate by etching.Type: ApplicationFiled: December 6, 2007Publication date: June 11, 2009Applicant: MICRON TECHNOLOGY, INC.Inventors: Baosuo Zhou, Gurtej S. Sandhu, Ardavan Niroomand