Abstract: An interconnection for a device in an integrated circuit includes a substrate on which a first metal line is embedded in a first dielectric layer. A via gouge is etched in the first metal line. A second dielectric layer is deposited over the first metal line and the first dielectric layer. A first via recess is etch through the second dielectric layer where the first via recess aligned to the via gouge. A second metal layer is deposited in the first via recess and the via gouge, forming a first via.

Abstract: A phase change memory (PCM) cell in an integrated circuit and a method of fabricating it involve depositing a layer of PCM material on a surface of a dielectric, and patterning the layer of PCM material into a plurality of PCM blocks. Heater material is formed on both sidewalls of each of the plurality of the PCM blocks to form a plurality of PCM cells. Each of the plurality of the PCM blocks and the heater material on both the sidewalls represents a PCM cell. An additional layer of the dielectric is deposited above and between the plurality of the PCM cells, and trenches are formed in the dielectric. Trenches are formed in contact with each side of each of the plurality of the PCM cells. Metal is deposited in each of the trenches. Current flow in the metal heats the heater material of one of the PCM cells.

Abstract: Interconnect structures having enhanced reliability is provided in which an electrically conductive structure having a line portion and a via portion is formed utilizing a subtractive process. In some embodiments, a non-conductive barrier liner is formed on physically exposed sidewalls of the via portion and physically exposed sidewalls and a topmost surface of the line portion of the electrically conductive structure. An electrically conductive metal cap is formed on a topmost surface of the via portion of the electrically conductive structure. In other embodiments, a conductive barrier spacer is formed on physically exposed sidewalls of the via portion and physically exposed sidewalls of the line portion of the electrically conductive structure. An electrically conductive metal cap is formed on a topmost surface of the via portion of the electrically conductive structure.

Abstract: An electrode structure is located at least partially in a via opening having a small feature size and containing a fuse element which is composed of a fuse element-containing seed layer that is subjected to a reflow anneal. The electrode structure is composed of a material having a higher electromigration (EM) resistance than the material that provides the fuse element. Prior to programming, the fuse element is present along sidewalls and a bottom wall of the electrode structure. After programming, a void is formed in the fuse element along at least one sidewall of the electrode structure and the resistance of the device will increase sharply.

Abstract: An IC device, such as a wafer, chip, die, processor, application specific integrated circuit (ASIC), field programmable gate array (FPGA), or the like include a chamfered VIA that connects an upper wiring line and a first lower wiring line. The chamfered VIA includes a chamfer or fillet upon the edge that connects the VIA sidewall(s) with the VIA contact surface that is connected to the first lower wiring line. The chamfer or fillet effectively increases the amount of a dielectric material, such as a high-k dielectric material, within a trench of the VIA and that is between the chamfered VIA and a second lower wiring line that neighbors the first lower wiring line. This increased dielectric material improves TDDB between the chamfered VIA and the second lower wiring line and mitigates TDDB effects, such as electrical shorts between the chamfered VIA and the second lower wiring line.

Abstract: A void-less bottom electrode structure is formed at least partially in a via opening having a small feature size and containing a conductive landing pad structure which is composed of a metal-containing seed layer that is subjected to a reflow anneal. A metal-containing structure is located on a topmost surface of the bottom electrode structure. The metal-containing structure may be composed of an electrically conductive metal-containing material or a material stack of electrically conductive metal-containing materials. In some embodiments, the bottom electrode and the metal-containing structure collectively provide a non-volatile memory device.

Abstract: An integrated circuit (IC) structure includes an active area of the IC structure insulator positioned over a substrate. The active area includes an interconnection structure comprised of a first plurality of levels. Each of the interconnect structure levels including an interlayer dielectric (ILD) layer, a barrier layer disposed over the ILD and a conductor metal layer over the barrier layer. The structure also includes a crack stop area which includes a crack stop structure having a second plurality of levels. The interconnect and crack stop structures have an equal number of levels. A third plurality of the crack stop structure levels include a high modulus layer unique to the respective crack stop structure level as compared to the corresponding interconnect structure level.

Abstract: A BEOL eFuse is provided that includes a fuse element-containing layer having an entirely planar topmost surface. An upper portion of the fuse element-containing layer including the entirely planar topmost surface is present above a topmost surface of a second interconnect dielectric material layer, and a lower portion of the fuse-element containing layer is present in an opening that is formed in the second interconnect dielectric material layer and has a surface that contacts a first electrode structure that is partially embedded in a first interconnect dielectric material layer which underlies the second interconnect dielectric material layer. A second electrode structure that is present in a third interconnect dielectric material layer that overlies the second interconnect dielectric material layer contacts a portion of the planar topmost surface of the fuse-element-containing layer.

Abstract: A method for creating an integrated circuit (IC) structure includes an active area of the IC structure insulator positioned over a substrate. The active area includes an interconnection structure comprised of a plurality of levels, each of the interconnect structure levels including an interlayer dielectric (ILD) layer, a barrier layer disposed over the ILD and a conductor metal layer over the barrier layer. The IC structure also includes a crack stop area which includes a crack stop structure having an equal plurality of levels as the interconnect structure. Each of the crack stop structure levels includes at least one of the layers of the interconnection structure at a same level. At least one crack stop structure level also includes a high modulus layer unique to the crack stop structure level as compared to the corresponding interconnect structure level. In another aspect of the invention, a method for producing the structure is described.

Abstract: An integrated circuit (IC) structure includes an active area of the IC structure insulator positioned over a substrate. The active area includes an interconnection structure comprised of a plurality of levels, each of the interconnect structure levels including an interlayer dielectric (ILD) layer, a barrier layer disposed over the ILD and a conductor metal layer over the barrier layer. The IC structure also includes a crack stop area which includes a crack stop structure having an equal plurality of levels as the interconnect structure. Each of the crack stop structure levels includes at least one of the layers of the interconnection structure at a same level. At least one crack stop structure level also includes a high modulus layer unique to the crack stop structure level as compared to the corresponding interconnect structure level.

Abstract: A phase change memory (PCM) cell in an integrated circuit and a method of fabricating it involve depositing a layer of PCM material on a surface of a dielectric, and patterning the layer of PCM material into a plurality of PCM blocks. Heater material is formed on both sidewalls of each of the plurality of the PCM blocks to form a plurality of PCM cells. Each of the plurality of the PCM blocks and the heater material on both the sidewalls represents a PCM cell. An additional layer of the dielectric is deposited above and between the plurality of the PCM cells, and trenches are formed in the dielectric. Trenches are formed in contact with each side of each of the plurality of the PCM cells. Metal is deposited in each of the trenches. Current flow in the metal heats the heater material of one of the PCM cells.

Abstract: An e-Fuse device including a first electronic feature and a second electronic feature comprised of a conductive material, each of the first electronic feature and the second electronic feature having a width at least as great as a ground rule of a patterning process; and a fuse element comprised of the conductive material having a width less than the ground rule of the patterning process, the fuse element connecting a bottom portion of the first electronic feature and a bottom portion of the second electronic feature. Also disclosed is a method of making the e-Fuse device.

Abstract: A mandrel structure includes a first mandrel, a second mandrel and a third mandrel in a parallel arrangement. The second mandrel is located between the first and third mandrels and has a cut larger than a minimum ground rule feature. A sidewall layer is formed over the mandrel structure. The sidewall layer has two long parallel gaps for two contact lines and a third gap for a fuse element. The third gap is orthogonal to and connects the two long parallel gaps. The sidewall pattern is used to form a trench structure comprising two parallel contact line trenches having a width at least as great as a ground rule of the patterning process for the contact lines and an orthogonal fuse element trench having a width less than the ground rule for the fuse element. A conductive material forms the contact lines and a fuse element.

Abstract: A semiconductor device includes a first dielectric layer including a first contact hole, a second dielectric layer formed on the first dielectric layer, and including a second contact hole aligned with the first contact hole, and a reflowed copper layer formed in the first and second contact holes.

Abstract: A phase change memory (PCM) cell in an integrated circuit and a method of fabricating it involve depositing a layer of PCM material on a surface of a dielectric, and patterning the layer of PCM material into a plurality of PCM blocks. Heater material is formed on both sidewalls of each of the plurality of the PCM blocks to form a plurality of PCM cells. Each of the plurality of the PCM blocks and the heater material on both the sidewalls represents a PCM cell. An additional layer of the dielectric is deposited above and between the plurality of the PCM cells, and trenches are formed in the dielectric. Trenches are formed in contact with each side of each of the plurality of the PCM cells. Metal is deposited in each of the trenches. Current flow in the metal heats the heater material of one of the PCM cells.

Abstract: An interconnection for a device in an integrated circuit includes a substrate on which a first metal line is embedded in a first dielectric layer. A via gouge is etched in the first metal line. A second dielectric layer is deposited over the first metal line and the first dielectric layer. A first via recess is etch through the second dielectric layer where the first via recess aligned to the via gouge. A second metal layer is deposited in the first via recess and the via gouge, forming a first via.

Abstract: A resistive random access memory (RRAM) device and a method for constructing the device is described. A capping layer structure is provided over a bottom contact where the capping layer includes a recess situated over the bottom contact. A first portion of the recess is filled with a lower electrode such that the width of the recess defines the width of the lower electrode. A second portion of the recess is filled with a high-K layer so that a bottom surface of the high-K layer has a stepped profile. A top electrode is formed on the high-K layer and a top contact is formed on the top electrode. The width of the high-K layer is greater than the width of the lower electrode to prevent shorting between the top contact and the lower electrode of the RRAM device.

Abstract: Back end of the line precision resistors that allow for high currents and for configuration as an eFuse by embedding a single thin film high resistive metal material within a dielectric layer, wherein the resisters are coupled to sidewalls of adjacent metal interconnects are described. The resistors can be formed in the metal one (M1) dielectric layer and can be coupled to sidewalls of the M1 interconnects. Also described are processes for fabricating integrated circuits including the resistors and/or e-Fuses.

Abstract: An antifuse structure having enhanced programming efficiency is provided in which there is limited contact between the antifuse material and top and bottom electrodes. The antifuse material has a circular ring shape (i.e., donate shape having a hole in the middle (center) thereof) in which a dielectric material structure composed of a dielectric material having a dielectric constant of great than 4.0 is contained in the hole of the circular ring shaped antifuse material. The antifuse material is composed of a dielectric material having a lower dielectric breakdown strength as compared to the dielectric material structure.

Abstract: A via and a method of fabricating a via in an integrated circuit involve forming a trench in dielectric material deposited above a first cap of a first metal level. The method includes patterning a collar from insulator material directly above the first cap, and etching through the first cap, within an area surrounded by the collar, to a first metal layer of the first metal level directly below the first cap. A liner is conformally deposited. The liner lines sidewalls of the collar. A metal conductor is deposited to form the via and a second metal layer of a second metal level.