Patents by Inventor Barry A. Hoberman
Barry A. Hoberman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8587079Abstract: A memory device includes a first plurality of magnetic random access memory (MRAM) cells positioned along a first direction, and a first bit line electrically connected to the first plurality of MRAM cells, the bit line oriented in the first direction. The device includes a first plurality of field lines oriented in a second direction different from the first direction, the first plurality of field lines being spaced such that only a corresponding first one of the first plurality of MRAM cells is configurable by each of the first plurality of field lines. The device includes a second plurality of field lines oriented in a third direction different from the first direction and the second direction, the second plurality of field lines being spaced such that only a corresponding second one of the first plurality of MRAM cells is configurable by each of the second plurality of field lines.Type: GrantFiled: August 10, 2012Date of Patent: November 19, 2013Assignee: Crocus Technology Inc.Inventors: Bertrand F. Cambou, Douglas J. Lee, Anthony J. Tether, Barry Hoberman
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Publication number: 20130241536Abstract: An apparatus includes circuits, a field line configured to generate a magnetic field based on an input, a sensing module configured to determine a parameter of each circuit, and a magnetic field direction determination module configured to determine an angular orientation of the apparatus relative to an external magnetic field based on the parameter. Each circuit includes multiple magnetic tunnel junctions. Each magnetic tunnel junction includes a storage layer having a storage magnetization direction and a sense layer having a sense magnetization direction configured based on the magnetic field. Each magnetic tunnel junction is configured such that the sense magnetization direction and a resistance of the magnetic tunnel junction vary based on the external magnetic field. The parameter varies based on the resistances of the multiple magnetic tunnel junctions. The magnetic field direction determination module is implemented in at least one of a memory or a processing device.Type: ApplicationFiled: March 6, 2013Publication date: September 19, 2013Applicant: CROCUS TECHNOLOGY INC.Inventors: Bertrand F. Cambou, Douglas J. Lee, Ken Mackay, Barry Hoberman
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Publication number: 20130037898Abstract: A memory device includes a first plurality of magnetic random access memory (MRAM) cells positioned along a first direction, and a first bit line electrically connected to the first plurality of MRAM cells, the bit line oriented in the first direction. The device includes a first plurality of field lines oriented in a second direction different from the first direction, the first plurality of field lines being spaced such that only a corresponding first one of the first plurality of MRAM cells is configurable by each of the first plurality of field lines. The device includes a second plurality of field lines oriented in a third direction different from the first direction and the second direction, the second plurality of field lines being spaced such that only a corresponding second one of the first plurality of MRAM cells is configurable by each of the second plurality of field lines.Type: ApplicationFiled: August 10, 2012Publication date: February 14, 2013Applicant: CROCUS TECHNOLOGY, INC.Inventors: Bertrand F. Cambou, Douglas J. Lee, Anthony J. Tether, Barry Hoberman
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Publication number: 20130027125Abstract: An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal that has a negative voltage. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry.Type: ApplicationFiled: August 8, 2012Publication date: January 31, 2013Inventors: Barry A. Hoberman, Daniel L. Hillman, William G. Walker, John M. Callahan, Michael A. Zampaglione, Andrew Cole
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Patent number: 8253438Abstract: An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal that has a negative voltage. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry.Type: GrantFiled: March 29, 2011Date of Patent: August 28, 2012Assignee: Mosaid Technologies IncorporatedInventors: Barry A. Hoberman, Daniel L. Hillman, William G. Walker, John M. Callahan, Michael A. Zampaglione, Andrew Cole
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Publication number: 20110272231Abstract: Systems (102) and methods (600) for adjusting a volume of an article of manufacture (AOM). The methods involve displacing a first actuator (FA) in a first direction along tracks (308, 310) until FA (312) disengages a first track (308) and abuts a first stop mechanism (504) formed at an end (510) ofa second track (310). A first flexible insert (FFI) is unfolded so as to adjust the volume of AOM by a first amount defined by geometrical dimensions of FFI (306). A second actuator (SA) is displaced in a second direction along tracks until SA (424) abuts a second stop mechanism (432) formed at ends (454) of the tracks (420, 422). A second flexible insert (SFI) is unfolded so as to further adjust the volume of AOM by a second amount defined by geometrical dimensions of SFI (406).Type: ApplicationFiled: February 3, 2010Publication date: November 10, 2011Inventors: Barry Hoberman, Robin Rankin
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Publication number: 20110260785Abstract: An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal that has a negative voltage. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry.Type: ApplicationFiled: March 29, 2011Publication date: October 27, 2011Applicant: MOSAID Technologies IncorporatedInventors: Barry A. Hoberman, Daniel L. Hillman, William G. Walker, John M. Callahan, Michael A. Zampaglione, Andrew Cole
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Publication number: 20110163145Abstract: A bag carried by a user, comprises at least one compartment sized and shaped for carrying articles. The compartment is defined by a front panel, a rear panel, a bottom panel and at least one side panel which are joined together via at least one joinder line. The side panel extends along each side of the bag and across the top of the bag. At least one securement loop is connected to the bag to extend across a width of the rear panel. The securement loop is configured for selectively attaching the bag to a selectively extendable handle of a wheeled article, and for preventing the bag from shifting and interfering with a maneuvering of the wheeled article.Type: ApplicationFiled: January 3, 2011Publication date: July 7, 2011Applicant: HOLIDAY GROUP, INC.Inventors: Martin Bedard, Barry Hoberman
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Patent number: 7940081Abstract: An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal that has a negative voltage. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry.Type: GrantFiled: August 17, 2009Date of Patent: May 10, 2011Assignee: MOSAID Technologies IncorporatedInventors: Barry A. Hoberman, Daniel L. Hillman, William G. Walker, John M. Callahan, Michael A. Zampaglione, Andrew Cole
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Publication number: 20100060319Abstract: An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal that has a negative voltage. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry.Type: ApplicationFiled: August 17, 2009Publication date: March 11, 2010Applicant: MOSAID Technologies CorporationInventors: Barry A. Hoberman, Daniel L. Hillman, William G. Walker, John M. Callahan, Michael A. Zampaglione, Andrew Cole
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Patent number: 7592837Abstract: An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal that has a negative voltage. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry.Type: GrantFiled: September 19, 2008Date of Patent: September 22, 2009Assignee: MOSAID Technologies CorporationInventors: Barry A. Hoberman, Daniel L. Hillman, William G. Walker, John M. Callahan, Michael A. Zampaglione, Andrew Cole
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Publication number: 20090027080Abstract: An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal that has a negative voltage. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry.Type: ApplicationFiled: September 19, 2008Publication date: January 29, 2009Applicant: Mosaid Technologies, Inc.Inventors: Barry A. Hoberman, Daniel L. Hillman, William G. Walker, John M. Callahan, Michael A. Zampaglione, Andrew Cole
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Publication number: 20080277220Abstract: An article of upright rolling luggage with wheels is provided having one or more adjustable feet for stabilizing the luggage case in the upright position. The luggage case includes one or more wheels rotatably mounted to a portion of the luggage case substantially at a rear edge of a bottom wall of the luggage case. One or more bases extend from the bottom wall and have at least one portion spaced apart from the wheel. One or more feet are movably mounted to the base where the foot is movable from a first position substantially adjacent to the bottom wall to a second position extending away from the bottom wall. A locking mechanism is provided which allows the foot to be held in the first position and manually rotated and automatically looked into the second position. Upon depressing a release mechanism, the foot is unlocked and automatically rotated from the second position into the first position.Type: ApplicationFiled: May 9, 2007Publication date: November 13, 2008Applicant: TRAVELPRO INTERNATIONAL, INC.Inventors: Long Hoang, Barry Hoberman, Jacqueline N. Miller
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Patent number: 7443197Abstract: An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry.Type: GrantFiled: November 30, 2007Date of Patent: October 28, 2008Assignee: Mosaid Technologies, Inc.Inventors: Barry A. Hoberman, Daniel L. Hillman, William G. Walker, John M. Callahan, Michael A. Zampaglione, Andrew Cole
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Publication number: 20080084775Abstract: An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry.Type: ApplicationFiled: November 30, 2007Publication date: April 10, 2008Inventors: Barry Hoberman, Daniel Hillman, William Walker, John Callahan, Michael Zampaglione, Andrew Cole
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Patent number: 7348804Abstract: An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal that has a negative voltage. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry.Type: GrantFiled: April 2, 2007Date of Patent: March 25, 2008Assignee: MOSAID Delaware, Inc.Inventors: Barry A. Hoberman, Daniel L. Hillman, William G. Walker, John M. Callahan, Michael A. Zampaglione, Andrew Cole
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Publication number: 20070176639Abstract: An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal that has a negative voltage. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry.Type: ApplicationFiled: April 3, 2007Publication date: August 2, 2007Inventors: Barry Hoberman, Daniel Hillman, William Walker, John Callahan, Michael Zampaglione, Andrew Cole
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Patent number: 7227383Abstract: An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal that has a negative voltage. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry.Type: GrantFiled: January 20, 2005Date of Patent: June 5, 2007Assignee: Mosaid Delaware, Inc.Inventors: Barry A. Hoberman, Daniel L. Hillman, William G. Walker, John M. Callahan, Michael A. Zampaglione, Andrew Cole
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Publication number: 20060123365Abstract: A system for an integrated circuit comprising a plurality of power islands includes a first power manager and a second power manager. The first power manager manages a first power consumption for the integrated circuit based on needs and operation of the integrated circuit. The second power manager communicates with the first power manager and manages a second power consumption for one of the power islands.Type: ApplicationFiled: January 20, 2006Publication date: June 8, 2006Inventors: Barry Hoberman, Daniel Hillman, Jon Shiell
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Patent number: 7036642Abstract: Laptop computer carrying case of a generally parallelepiped form for transporting laptop computers of small and oversized dimensions. The carrying/case includes a front panel, a rear panel spaced apart and opposed from the front panel and a pair of side panels attached to the front and rear panels along corresponding side edges of the front and rear panels. A base panel is attached to the front, rear and side panels. A cover flap is attached to the case and is adjustably latched to the case. One or more side straps protect oversized computers from damage.Type: GrantFiled: January 28, 2004Date of Patent: May 2, 2006Assignee: Travelpro International, Inc.Inventors: Barry Hoberman, Jacqueline N. Miller