Abstract: A photoconductor marking apparatus is disclosed. The apparatus includes a radiation source to emit radiation capable of irreversibly modifying photoconductive properties of a layer of a multi-layered photoconductor. The apparatus also includes processing apparatus to: determine a pattern to be applied to a photoconductor to be used in a print apparatus, the photoconductor having an imaging area within which print agent is to be deposited; and control the radiation source to direct radiation towards the photoconductor in a region outside the imaging area, so as to irreversibly modify photoconductive properties of a layer of the photoconductor according to the determined pattern. A method and a machine-readable medium are also disclosed.

Abstract: Capacitances are measured for a level measurement capacitive sensor (18) spanning from a lower end to a higher end of a fluid level measurement range (30), a first capacitive calibration sensor (20) below the fluid level measurement range (30), and a second capacitive calibration sensor (22) above the fluid level measurement range (30). A degree to which the lower end of the fluid level measurement range (30) is immersed in a first fluid and the upper end of the fluid level measurement range (30) is immersed in a second fluid is determined based on a capacitance of the level measurement capacitive sensor (18), a first calibration value characterizing the first fluid and derived from a capacitance of the first capacitive calibration sensor (20), and a second calibration value characterizing the second fluid and derived from a capacitance of the second capacitive calibration sensor (22).

Abstract: Capacitances are measured for a level measurement capacitive sensor (18) spanning from a lower end to a higher end of a fluid level measurement range (30), a first capacitive calibration sensor (20) below the fluid level measurement range (30), and a second capacitive calibration sensor (22) above the fluid level measurement range (30). A degree to which the lower end of the fluid level measurement range (30) is immersed in a first fluid and the upper end of the fluid level measurement range (30) is immersed in a second fluid is determined based on a capacitance of the level measurement capacitive sensor (18), a first calibration value characterizing the first fluid and derived from a capacitance of the first capacitive calibration sensor (20), and a second calibration value characterizing the second fluid and derived from a capacitance of the second capacitive calibration sensor (22).

Abstract: Hard imaging methods and hard imaging devices are described. According to one embodiment, a hard imaging method includes forming a plurality of latent images, using a development assembly, developing the latent images using a liquid marking agent, transporting the liquid marking agent relative to the development assembly during the developing, and performing a bubble reduction operation to reduce a presence of bubbles in the liquid marking agent during the developing and transporting compared with not performing the bubble reduction operation. Additional embodiments are described in the disclosure.

Abstract: Hard imaging methods and hard imaging devices are described. According to one embodiment, a hard imaging method includes forming a plurality of latent images, using a development assembly, developing the latent images using a liquid marking agent, transporting the liquid marking agent relative to the development assembly during the developing, and performing a bubble reduction operation to reduce a presence of bubbles in the liquid marking agent during the developing and transporting compared with not performing the bubble reduction operation. Additional embodiments are described in the disclosure.

Abstract: A controller interconnect structure within a RAID disk array enables continuous low latency/high bandwidth communications between a plurality of controller pairs within the array. Mirror buses carry high speed mirror traffic between mirrored controllers performing mirrored memory operations. Loop buses carry inter-processor communications and other traffic between controller pairs coupled together in a controller loop. Benefits of the interconnect structure include an ability to support continued controller communications and online disk array operations under various failure and repair conditions that might otherwise render a disk array inoperable. In addition, the controller interconnect structure provides for easy expansion of the number of controllers within disk arrays as arrays continue to be scaled up in size to meet increasing storage demands from user host systems.

Abstract: Fault tolerant data storage systems and methods of operating a fault tolerant data storage system are presented. In one aspect of the invention, a fault tolerant data storage system comprises: a plurality of coupled components individually including: an interface adapted to couple with a data connection and to selectively receive a plurality of transactions from the data connection; transaction processing circuitry coupled with the interface and configured to process transactions received from the interface; and analysis circuitry configured to detect error conditions within the transactions and to prevent entry of transactions individually including an error condition into the respective component responsive to the detection.

Abstract: A disk controller includes memory that is accessible by both a microprocessor and hardware parity logic. Parity-related operations are identified by scenario, and parity coefficient subsets are stored in a memory table for each different parity-related calculation scenario. To perform a particular parity-related operation, the microprocessor determines the operation's scenario and identifies the corresponding coefficient subset. The hardware parity logic is then instructed to perform the appropriate parity computation, using the identified coefficient subset. In one embodiment, parity segments are calculated by a parity segment calculation module that is embodied as an application specific integrated circuit (ASIC).

Abstract: A verification system for an interchangeable component configured to be mated with a receiving system. The system includes a key device supported by the interchangeable component. The key device includes a transmitter configured to transmit a signal comprising component identification characteristics. The system further includes a lock system having a signal receiver and a verification component. The signal receiver is configured to receive the signal from the key device transmitter and pass the signal to the verification component. The verification component is configured to use the signal to determine whether or not the component should be admitted to the receiving system, and to generate an authorization signal if the component should be admitted.

Abstract: The system and methods described herein relate to testing and verifying the fault tolerance in fault tolerant systems. Fault logic integrated into a fault tolerant system permits automated testing of fault paths in system firmware and hardware dedicated to handling fault scenarios. Advantages of the disclosed system and methods include the ability to inject errors without the need to modify system firmware or hardware. Errors can be injected in a controlled manner and asynchronously to normal system firmware execution which permits improved coverage of firmware error paths. The automated error injection capability disclosed is applicable in both the development and production of fault tolerant systems.

Abstract: The memory management technology controls, as described herein, access to and monitors availability of common memory resources. In particular, this hardware-based, memory-management technology manages memory access requests to a common memory shared by multiple requesting entities. This includes prioritizing and arbitrating such requests. It further includes minimizing latency of such requests. This abstract itself is not intended to limit the scope of this patent. The scope of the present invention is pointed out in the appending claims.

Abstract: A method and apparatus for monitoring the movement of an object traversing a circuit and outputting data with respect thereto. Lap events are recorded and used to calculate a total lap count, split time, and elapsed time for an event that includes the repetitive traversing of a circuit. Physiologic data is monitored in the case where the object is a person. A transponder or transmitter is affixed to a user and a signal having limited range is coupled to a communications and display device when the user comes into range of the device. Each such coupling is accumulated as lap event data. Calculations are made to display the lap count and timing information as well as physiologic data. In one embodiment, the device is implemented in a watertight housing and placed at the bottom of a swimming pool. The displayed information is visible to a swimmer wearing the transponder or transmitter. In another embodiment, the display is incorporated into eyewear worn by the person traversing a repetitive circuit.

Abstract: The memory management technology controls, as described herein, access to and monitors availability of common memory resources. In particular, this hardware-based, memory-management technology manages memory access requests to a common memory shared by multiple requesting entities. This includes prioritizing and arbitrating such requests. It further includes minimizing latency of such requests. This abstract itself is not intended to limit the scope of this patent. The scope of the present invention is pointed out in the appending claims.

Abstract: A redundant controller data storage system having a hot insertion system and method is described. In one aspect, the method of hot inserting a controller in a redundant controller system includes configuring a first controller to include a first memory, a task processor and a system operation processor. The first memory includes a first memory image. The redundant controller system is operated via the first controller. The system operation commands are processed via the system operation processor. A second controller including a second memory, is inserted into the redundant controller system. Background tasks are processed during the processing of system operation commands via the first controller using the task processor, including copying the first memory image to the second memory.

Abstract: A controller is presented comprising one or more initiators coupled to one or more targets via a transaction bus and a corresponding number of data busses. The initiator(s) receive transaction requests from external logic, buffer the transaction and assign it a unique identifier, which is passed to an appropriate target via the transaction bus. The targets receive and queue the unique identifier until it can process the transaction, at which time it prompts the initiator to provide it the buffered transaction via a data bus dedicated to the target.

Abstract: The memory management technology controls, as described herein, access to and monitors availability of common memory resources. In particular, this hardware-based, memory-management technology manages memory access requests to a common memory shared by multiple requesting entities. This includes prioritizing and arbitrating such requests. It further includes minimizing latency of such requests. This abstract itself is not intended to limit the scope of this patent. The scope of the present invention is pointed out in the appending claims.

Abstract: Fault tolerant data storage systems and methods of operating a fault tolerant data storage system are presented. In one aspect of the invention, a fault tolerant data storage system comprises: a plurality of coupled components individually including: an interface adapted to couple with a data connection and to selectively receive a plurality of transactions from the data connection; transaction processing circuitry coupled with the interface and configured to process transactions received from the interface; and analysis circuitry configured to detect error conditions within the transactions and to prevent entry of transactions individually including an error condition into the respective component responsive to the detection.

Abstract: A disk controller includes memory that is accessible by both a microprocessor and an operation logic. Information needed by the operation logic to perform an operation is stored in a task description block in memory by the microprocessor, and a pointer to the task description block is added to a task description block queue. The operation logic is then able to access task description blocks, based on the pointers in the queue, at will and perform the corresponding operations.

Abstract: A disk controller includes memory that is accessible by both a microprocessor and hardware parity logic. Parity-related operations are identified by scenario, and parity coefficient subsets are stored in a memory table for each different parity-related calculation scenario. To perform a particular parity-related operation, the microprocessor determines the operation's scenario and identifies the corresponding coefficient subset. The hardware parity logic is then instructed to perform the appropriate parity computation, using the identified coefficient subset. In one embodiment, parity segments are calculated by a parity segment calculation module that is embodied as an application specific integrated circuit (ASIC).

Abstract: A verification system for an interchangeable component configured to be mated with a receiving system. The system includes a key device supported by the interchangeable component. The key device includes a transmitter configured to transmit a signal comprising component identification characteristics. The system further includes a lock system having a signal receiver and a verification component. The signal receiver is configured to receive the signal from the key device transmitter and pass the signal to the verification component. The verification component is configured to use the signal to determine whether or not the component should be admitted to the receiving system, and to generate an authorization signal if the component should be admitted.