Abstract: A disk controller includes memory that is accessible by both a microprocessor and hardware parity logic. Parity-related operations are identified by scenario, and parity coefficient subsets are stored in a memory table for each different parity-related calculation scenario. To perform a particular parity-related operation, the microprocessor determines the operation's scenario and identifies the corresponding coefficient subset. The hardware parity logic is then instructed to perform the appropriate parity computation, using the identified coefficient subset. In one embodiment, parity segments are calculated by a parity segment calculation module that is embodied as an application specific integrated circuit (ASIC).

Abstract: Redundant data storage systems and methods of operating a redundant data storage system are presented. In one aspect of the invention, a redundant data storage system includes: a plurality of storage devices configured to redundantly store digital data; a plurality of transaction originating devices configured to originate a plurality of transactions to control operations of the storage devices; a plurality of parallel data buses configured to communicate data relative to the respective transaction originating devices; and a plurality of transaction processing devices coupled with the parallel data buses and configured to process the transactions in an order according to a transaction ordering protocol common to at least some of the transaction processing devices.

Abstract: In a Fiber Channel Arbitrated Loop communications architecture, dynamic loop sizing includes selectively bypassing operational device ports in the loop in order to minimize overhead associated with loop size. In redundant systems with multiple loops, the system is optimized by judicious distribution of the bypassed ports among the loops. Redundancy is at no point reduced. By bypassing unused or unneeded ports off of a loop, the round trip delay of the loop is appreciably shortened. By minimizing the round trip delay, arbitration overhead and access latency is reduced, and loop bandwidth and overall performance is improved. Dynamic load sharing balances the load between the dual loops when using dual ported devices on the loops. Dynamic load sharing is accomplished by bypassing a given subset of devices off each loop to reduce round trip delay; monitoring traffic on the loops; and controlling which devices are attached to which loop in order to balance the load across the loops.

Abstract: A disk storage control system includes dual controllers having real-time, synchronous, mirrored memory therebetween to provide immediate, accurate, and reliable failover in the event of controller failure. Non-volatile random access memory provides retention of data during a loss of power and during the manipulation of hardware for purposes of repair. A communication path is established within the mirrored memory between the controllers to monitor and coordinate their activities. The state of the mirrored memory is continuously monitored for accuracy of the mirror and failure detection. Concurrent and ready access by a host computer to the same disk storage control data set from each controller is provided without need for extra manipulation or extra direct memory access (DMA) activity to satisfy host requests. Accordingly, either controller can provide immediate and reliable failover control for the disk storage system.

Abstract: An apparatus for generating parity blocks in a RAID system includes a PRAM control unit, two parity memories each coupled to the PRAM control unit, and in several alternative embodiments, a valid contents memory for tracking the contents of the parity memories. Parity blocks are generated by performing an exclusive OR operation between all of the corresponding data words in the data blocks of the stripe. Results of the exclusive OR operations are alternately stored in the two parity memories. Alternately dedicating one parity memory for storing the results of the exclusive OR operation which will be performed and one parity memory from which the results of the previous exclusive OR operation are loaded allows computation of the parity block to be performed at a higher rate than configurations which use a single parity memory. In a first embodiment of the PRAM control unit, a flip/flop tracks which of the two parity memories contains the valid contents.

Abstract: In a disk storage system having dual controllers and mirrored memory therebetween, arbitration logic associated with each controller generates state transition signals to identify the mirrored memory access status for the controller generating the signal. Each arbitration logic also monitors the state transition signals of the other. A failure in the mirrored memory system between the dual controllers is detected by one controller sensing an incorrect state transition signal communicated from the other controller. A failure is also detected by one controller not sensing a state transition signal from the other within a specified timeout period. Memory refresh cycles are tapped to cause the arbitration logic to cycle through state transition signals thereby forcing each controller to attempt a mirrored memory access on a regular basis whereby a memory system failure may be detected.

Abstract: Boot firmware is manipulated within separately erasable/writable blocks of a flash EEPROM, and a non-volatile memory bit circuit is used to force manipulation of address space associated with the blocks to provide a powerfail durable flash upgrade for the EEPROM without the need for a separate ROM. During a firmware upgrade in the EEPROM, a block in the EEPROM is erased, other than the primary boot block, and is designated as an alternate boot block. The primary boot block firmware contents are then copied to the alternate boot block, and the non-volatile memory bit is set to cause the alternate boot block to appear in the address space of the primary boot block from a microprocessor's perspective. The primary boot block is then erased and written with new firmware information. The non-volatile memory bit is then reset back to allow the primary boot block to appear in its proper address space, and the alternate boot block is upgraded with its new firmware information.

Abstract: In a disk storage system having dual controllers and mirrored memory therebetween, a controller identification system provides a unique system identifier (ID) data (number, password, etc.) accessible by both controllers for determination of which controller is MASTER. This identifier is physically mounted in a location that will always remain with the disk array and will always remain accessible by the controllers. Typically, a read-only memory (ROM) stores the identifier. During initialization, each controller reads this system identifier and compares it to a respective controller identifier previously stored in a non-volatile memory area of each controller. If the system identifier matches the controller identifier, the controller has not been moved and, therefore, has a valid memory image and may have previously been a MASTER controller. A MASTER bit signal is then checked; and, if it is set, the controller was previously the MASTER controller and will continue as MASTER controller.