Abstract: A redundant controller data storage system having an on-line controller removal system and method is described. In one aspect, the method of on-line removal of a controller from a redundant controller system according to the present invention includes the redundant controller system having a first controller and a second controller. Partial removal of the first controller from the redundant controller system is detected. A shut-down sequence is performed on the first controller and the second controller, including completing outstanding memory accesses. The first controller is defined to have a first memory, and the first memory is placed into a self-refresh mode. Removal of the first controller from the redundant controller system is finished.

Abstract: A redundant controller data storage system having a system and method for handling controller resets is described. In one aspect, the method of handling a controller reset in a redundant controller system according to the present invention includes the redundant controller system having a first controller and a second controller. A controller reset is detected on the second controller. The first controller is notified of the controller reset via a communication link between the first controller and the second controller. A shutdown process on the first controller and the second controller is performed. The communication link between the first controller and the second controller is disabled, wherein detection of a subsequent controller reset via the second controller cannot be communicated to the first controller via the communication link.

Abstract: A disk controller includes memory that is accessible by both a microprocessor and hardware parity logic. Parity-related operations are identified by scenario, and parity coefficient subsets are stored in a memory table for each different parity-related calculation scenario. To perform a particular parity-related operation, the microprocessor determines the operation's scenario and identifies the corresponding coefficient subset. The hardware parity logic is then instructed to perform the appropriate parity computation, using the identified coefficient subset. In one embodiment, parity segments are calculated by a parity segment calculation module that is embodied as an application specific integrated circuit (ASIC).

Abstract: Systems and methods for protecting electronic devices from electrostatic discharge are provided. A preferred system includes a module configured to be received by an enclosure. The module incorporates an electronic component, such as a memory device, processor, and/or circuit assembly, for example, that is configured to electrically communicate with at least a portion of the enclosure when the module is received by the enclosure. The module also includes a first contact portion that is arranged to contact the enclosure as the module is received by the enclosure. Preferably, the first contact portion is formed, at least partially, of a dissipative material. So configured, when the first contact portion engages the enclosure, an electrostatic charge of the module may be discharged in a controlled manner. Methods also are provided.

Abstract: A verification system for an interchangeable component configured to be mated with a receiving system. The system includes a key device supported by the interchangeable component. The key device includes a transmitter configured to transmit a signal comprising component identification characteristics. The system further includes a lock system having a signal receiver and a verification component. The signal receiver is configured to receive the signal from the key device transmitter and pass the signal to the verification component. The verification component is configured to use the signal to determine whether or not the component should be admitted to the receiving system, and to generate an authorization signal if the component should be admitted.

Abstract: A controller interconnect structure within a RAID disk array enables continuous low latency/high bandwidth communications between a plurality of controller pairs within the array. Mirror buses carry high speed mirror traffic between mirrored controllers performing mirrored memory operations. Loop buses carry inter-processor communications and other traffic between controller pairs coupled together in a controller loop. Benefits of the interconnect structure include an ability to support continued controller communications and online disk array operations under various failure and repair conditions that might otherwise render a disk array inoperable. In addition, the controller interconnect structure provides for easy expansion of the number of controllers within disk arrays as arrays continue to be scaled up in size to meet increasing storage demands from user host systems.

Abstract: Fault tolerant data storage systems and methods of operating a fault tolerant data storage system are presented. In one aspect of the invention, a fault tolerant data storage system comprises: a plurality of coupled components individually including: an interface adapted to couple with a data connection and to selectively receive a plurality of transactions from the data connection; transaction processing circuitry coupled with the interface and configured to process transactions received from the interface; and analysis circuitry configured to detect error conditions within the transactions and to prevent entry of transactions individually including an error condition into the respective component responsive to the detection.

Abstract: A method and apparatus for monitoring the movement of an object traversing a circuit and outputting data with respect thereto. Lap events are recorded and used to calculate a total lap count, split time, and elapsed time for an event that includes the repetitive traversing of a circuit. Physiologic data is monitored in the case where the object is a person. A transponder or transmitter is affixed to a user and a signal having limited range is coupled to a communications and display device when the user comes into range of the device. Each such coupling is accumulated as lap event data. Calculations are made to display the lap count and timing information as well as physiologic data. In one embodiment, the device is implemented in a watertight housing and placed at the bottom of a swimming pool. The displayed information is visible to a swimmer wearing the transponder or transmitter. In another embodiment, the display is incorporated into eyewear worn by the person traversing a repetitive circuit.

Abstract: Methods and systems for fault location are described. In one described embodiment, an “in circuit” solution is provided for locating faults along a passive transmission line. Once a fault occurs, various hardware gathers information that is necessary to determine which of a number of different replaceable components has failed. This enables the subsystem to properly respond to the fault condition and thereby eliminate any guessing that could potentially lead to loss of data availability. In the particular described embodiment, signals are driven and received through a selected input/output (I/O) pad. Logic circuitry is provided and launches a wave onto the passive transmission line. Immediately following the launching of the wave, the I/O pad is monitored and can sense the reflections from the wave that has just been launched. By analyzing the reflections, and more specifically the time that it takes for the reflection to be sensed, a determination is made as to the fault location.

Abstract: The system and methods described herein relate to testing and verifying the fault tolerance in fault tolerant systems. Fault logic integrated into a fault tolerant system permits automated testing of fault paths in system firmware and hardware dedicated to handling fault scenarios. Advantages of the disclosed system and methods include the ability to inject errors without the need to modify system firmware or hardware. Errors can be injected in a controlled manner and asynchronously to normal system firmware execution which permits improved coverage of firmware error paths. The automated error injection capability disclosed is applicable in both the development and production of fault tolerant systems.

Abstract: A disk controller includes memory that is accessible by both a microprocessor and hardware parity logic. Parity-related operations are identified by scenario, and parity coefficient subsets are stored in a memory table for each different parity-related calculation scenario. To perform a particular parity-related operation, the microprocessor determines the operation's scenario and identifies the corresponding coefficient subset. The hardware parity logic is then instructed to perform the appropriate parity computation, using the identified coefficient subset. Parity segments are calculated by a parity segment calculation module that is embodied as an application specific integrated circuit (ASIC).

Abstract: Redundant data storage systems and methods of operating a redundant data storage system are presented. In one aspect of the invention, a redundant data storage system includes: a plurality of storage devices configured to redundantly store digital data; a plurality of transaction originating devices configured to originate a plurality of transactions to control operations of the storage devices; a plurality of parallel data buses configured to communicate data relative to the respective transaction originating devices; and a plurality of transaction processing devices coupled with the parallel data buses and configured to process the transactions in an order according to a transaction ordering protocol common to at least some of the transaction processing devices.

Abstract: A disk controller includes memory that is accessible by both a microprocessor and hardware parity logic. Parity-related operations are identified by scenario, and parity coefficient subsets are stored in a memory table for each different parity-related calculation scenario. To perform a particular parity-related operation, the microprocessor determines the operation's scenario and identifies the corresponding coefficient subset. The hardware parity logic is then instructed to perform the appropriate parity computation, using the identified coefficient subset. Parity segments are calculated by a parity segment calculation module that is embodied as an application specific integrated circuit (ASIC).

Abstract: In a Fiber Channel Arbitrated Loop communications architecture, dynamic loop sizing includes selectively bypassing operational device ports in the loop in order to minimize overhead associated with loop size. In redundant systems with multiple loops, the system is optimized by judicious distribution of the bypassed ports among the loops. Redundancy is at no point reduced. By bypassing unused or unneeded ports off of a loop, the round trip delay of the loop is appreciably shortened. By minimizing the round trip delay, arbitration overhead and access latency is reduced, and loop bandwidth and overall performance is improved. Dynamic load sharing balances the load between the dual loops when using dual ported devices on the loops. Dynamic load sharing is accomplished by bypassing a given subset of devices off each loop to reduce round trip delay; monitoring traffic on the loops; and controlling which devices are attached to which loop in order to balance the load across the loops.

Abstract: A disk controller includes memory that is accessible by both a microprocessor and an operation logic. Information needed by the operation logic to perform an operation is stored in a task description block in memory by the microprocessor, and a pointer to the task description block is added to a task description block queue. The operation logic is then able to access task description blocks, based on the pointers in the queue, at will and perform the corresponding operations.

Abstract: Systems and methods for protecting electronic devices from electrostatic discharge are provided. A preferred system includes a module configured to be received by an enclosure. The module incorporates an electronic component, such as a memory device, processor, and/or circuit assembly, for example, that is configured to electrically communicate with at least a portion of the enclosure when the module is received by the enclosure. The module also includes a first contact portion that is arranged to contact the enclosure as the module is received by the enclosure. Preferably, the first contact portion is formed, at least partially, of a dissipative material. So configured, when the first contact portion engages the enclosure, an electrostatic charge of the module may be discharged in a controlled manner. Methods also are provided.

Abstract: A redundant controller data storage system having a hot insertion system and method is described. In one aspect, the method of hot inserting a controller in a redundant controller system includes configuring a first controller to include a first memory, a task processor and a system operation processor. The first memory includes a first memory image. The redundant controller system is operated via the first controller. The system operation commands are processed via the system operation processor. A second controller including a second memory, is inserted into the redundant controller system. Background tasks are processed during the processing of system operation commands via the first controller using the task processor, including copying the first memory image to the second memory.

Abstract: The memory management technology controls, as described herein, access to and monitors availability of common memory resources. In particular, this hardware-based, memory-management technology manages memory access requests to a common memory shared by multiple requesting entities. This includes prioritizing and arbitrating such requests. It further includes minimizing latency of such requests. This abstract itself is not intended to limit the scope of this patent. The scope of the present invention is pointed out in the appending claims.

Abstract: A redundant controller data storage system having a system and method for handling controller resets is described. In one aspect, the method of handling a controller reset in a redundant controller system according to the present invention includes the redundant controller system having a first controller and a second controller. A controller reset is detected on the second controller. The first controller is notified of the controller reset via a communication link between the first controller and the second controller. A shutdown process on the first controller and the second controller is performed. The communication link between the first controller and the second controller is disabled, wherein detection of a subsequent controller reset via the second controller cannot be communicated to the first controller via the communication link.

Abstract: A redundant controller data storage system having an on-line controller removal system and method is described. In one aspect, the method of on-line removal of a controller from a redundant controller system according to the present invention includes the redundant controller system having a first controller and a second controller. Partial removal of the first controller from the redundant controller system is detected. A shut-down sequence is performed on the first controller and the second controller, including completing outstanding memory accesses. The first controller is defined to have a first memory, and the first memory is placed into a self-refresh mode. Removal of the first controller from the redundant controller system is finished.