Abstract: A control unit of an SRAM memory for triggering an initialisation, selected from different possible distinct initialisation types, of at least one given group of SRAM memory cells of the SRAM memory, the control unit configured to adopt a “locked” operating mode, in which it triggers an initialisation of the given group of cells according to a “default” initialisation type corresponding to a first initialisation type from the different distinct initialisation types or an erasing, and holds at the output the “hard masking” command signal in the same given state as long as a particular so-called “unlocking” signal sequence is not received on the hard masking inputs, the control unit being further configured, subsequently to the reception of the particular so-called “unlocking” signal sequence, to enable the initialisation of the given group according to different initialisation types which may be distinct from the default initialisation.

Abstract: A circuit comprises first, second, and third nodes (2002, 2004, 2006) respectively receiving a reference potential, a first voltage, and a second voltage. A first NMOS transistor has its gate connected to the second node. A second NMOS transistor has its drain and its source respectively connected to the source of the first transistor and to the second node. A third NMOS transistor has its gate and its source respectively connected to the second and first nodes. A fourth PMOS transistor has its drain connected to the drain of the third transistor and to the gate of the second transistor, and its gate connected to the source of the first transistor. A resistive element connects the first transistor to the third node, another resistive element connecting the fourth transistor to the third node.

Abstract: The present disclosure relates to a device (REFGEN) comprising: a first divider bridge (200) between a first node (202) at a supply voltage (VDDE) and a second node (204) at a reference potential (GND); a first transistor (Ten) and a second divider bridge (208) in series between the first and second nodes, the first transistor having its gate at the first bridge; a buffer circuit (BUFFa1) having an input (220) connected to a node (214) of the second bridge, and an output (218) delivering a reference voltage (VrefL); and a second transistor (To1) having its drain connected to the output of the buffer circuit, and its source connected to one of the first and second nodes. The first transistor (Ten) is OFF if the supply voltage (VDDE) is less than a threshold. The second transistor is ON if the first transistor is OFF, and vice versa.

Abstract: A method is provided for writing a data word to a resistive memory consisting of 2T2R differential cells each having first and second sets of a resistor (R) and a selection transistor (T). The method includes generating an initial codeword, programming it in 1T1R mode, checking its programming in 1T1R mode, inverting it, programming the inverted initial codeword in 1T1R mode, checking its programming in 1T1R mode, and reading, in 2T2R differential mode, that the read data correspond to said initial data. A device designed to implement this write method and to an electronic system including this device is also provided.

Abstract: An electroforming process for a resistive memory of a memory device including a memory controller, an encoder computing an inversion-invariant linear error correction code, and a write device connected directly to the encoder. An electroforming device performing electroforming through write operations to such a resistive memory and to a method for checking a write operation.

Abstract: A static random access memory device comprising a memory array provided with SRAM memory cells, each of said cells in said array comprising a first storage node and a second storage node, the device further being provided with a control circuit for controlling said cells configured to, after powering up the array, place the array into a first operating mode in which a first set of cells located in a first zone of the array into a so-called “metastable” state for which the first storage node and said second storage node are placed to equal or substantially equal potentials while a second set of cells located in a second zone of the array distinct from the first zone have their respective first node and second node to respective different potentials and corresponding to a given logic state between a low state and a high state and to a logic state complementary to said given state.

Abstract: Static random access memory device comprising a matrix in which each column is associated with an initialization circuit (100i, 100j), provided with a stage (110) for drawing a random value (110), configured to, following the reception of the initialization activation signal (RAND_ENABLE), produce, in a random manner, respectively a first potential at a first node (NA) corresponding to a given logic state and a second potential at a second output node (NB) different from the first potential and corresponding to a given logic state complementary to said given logic state, in order to initialize cells of a same column to a given state selected randomly between two states.

Abstract: The electronic circuit performs binary computation operations and comprises word, bit and source lines, and memory cells organized in rows and columns. Each cell includes one pair of memristors and one pair of switches, each memristor being connected to a switch and linked to the same source line during each computation operation, each pair of memristors storing a binary value; the switches being linked to a word line and to a pair of complementary bit lines. The circuit comprises a reading module including: a logic unit for each column, each comprising an input terminal connected to a source line to receive a column value, the logic unit toggling between values, depending on a comparison of the column value with a toggle threshold value; a modification unit for modifying, for at least one logic unit and depending on the computation operation, a difference between the column and threshold values.

Abstract: An FDSOI transistor control device includes a plurality of first wells having a first type of conductivity, each first well being associated with a group of transistors, and at least one second well having a second type of conductivity, formed under and around the first wells (21). A bias circuit is configured to apply at least one first bias voltage to the first wells and at least one second bias voltage to at least one second well. All of the transistors may have the second type of conductivity.

Abstract: A method is provided for writing a data word to a resistive memory consisting of 2T2R differential cells each having first and second sets of a resistor (R) and a selection transistor (T). The method includes generating an initial codeword, programming it in 1T1R mode, checking its programming in 1T1R mode, inverting it, programming the inverted initial codeword in 1T1R mode, checking its programming in 1T1R mode, and reading, in 2T2R differential mode, that the read data correspond to said initial data. A device designed to implement this write method and to an electronic system including this device is also provided.

Abstract: An electroforming process for a resistive memory of a memory device including a memory controller, an encoder computing an inversion-invariant linear error correction code, and a write device connected directly to the encoder. An electroforming device performing electroforming through write operations to such a resistive memory and to a method for checking a write operation.

Abstract: A static random access memory device includes a memory matrix provided with at least one set of SRAM memory cells and a circuit for initializing cells of the set, the setting circuit being able to carry out various setting types and in particular a “deterministic” setting in which the cells are established at an imposed value and to carry out a “free” setting in which the cells are established at a value that depends on their manufacturing method.

Abstract: The present invention relates to a neuromorphic circuit suitable for implementing a neural network, the neuromorphic circuit comprising: lines of words, pairs of complementary bit-lines, source lines, a set of elementary cells, an electronic circuit implementing a neurone having an output and including: a set of logic components, a counting unit, a comparison unit comprising a comparator and a comparison voltage generator, the comparator being suitable for comparing the output of the counting unit with the comparison voltage generated by the comparison voltage generator in order to output a signal dependent on the comparison and corresponding to the output of the electronic circuit which implements a neurone.

Abstract: A method of circuit conception of a computational memory circuit including a memory having memory cells, the method including: receiving an indication of the memory storage size and an indication of an instruction frequency of the instructions to be executed by the computational memory circuit; evaluating for a plurality of candidate types of memory cells, a number representing an average number of cycles of the memory of the computational memory circuit per instruction to be executed; determining, for each of the plurality of candidate types of memory cells, a minimum operating frequency of the computational memory circuit based on the number N and on the memory storage size; selecting one of the plurality of candidate types of memory cells based on the determined minimum operating frequency; and performing the circuit conception based on the selected type of candidate memory cell.

Abstract: A Memory device comprising a matrix of memory cells, the matrix being provided with at least one first column, the device also being provided with a test circuit configured to perform a test phase during a read operation to indicate whether or not the proportion of cells in said column storing the same logical data, particularly a logical ‘1’, is greater than a predetermined threshold.

Abstract: A memory device including a matrix of memory cells including FET transistors including back-bias elements, of which at least one column forms back-bias bits; a back-bias circuit outputting voltages dependent on back-bias bits; first and second coupling elements, coupling memory dots of back-bias bits with the back-bias circuit, and the back-bias circuit with the back-bias elements of the cells of the matrix; wherein the device forms a 3D circuit including first and second active layers between which several interconnection layers are stacked; the first and/or the second coupling elements include metallic portions of one of the interconnection layers.

Abstract: A memory circuit including a plurality of elementary cells arranged in a plurality of arrays, each including a plurality of rows and a plurality of columns, and wherein: the elementary cells having the same coordinates in the different arrays share a same first conductive track; and in each array, the elementary cells of a same row of the array share a same second conductive track and a same third conductive track.

Abstract: A memory circuit including a plurality of elementary cells arranged in an array of rows and of columns, and a control circuit capable of implementing an operation of vertical reading of a word from a column of the array.

Abstract: A memory circuit including a plurality of elementary cells distributed in a plurality of arrays, each including N columns, N being an integer greater than or equal to 2, wherein: each column of each array includes a first local bit line directly connected to each of the cells in the column; each column of each array includes a first general bit line coupled to the first local bit line of the column by a first coupling circuit; and the first general bit lines of the columns of same rank j of the different arrays, j being an integer in the range from 0 to M?1, are coupled together.

Abstract: The application relates to an integrated circuit with SRAM memory and provided with several superimposed levels of transistors, the integrated circuit including SRAM cells provided with a first transistor and a second transistor belonging to an upper level of transistors and each having a double gate composed of an upper electrode and a lower electrode laid out on either side of a semiconductor layer, a lower gate electrode of the first transistor being connected to a lower gate electrode of the second transistor.