Patents by Inventor Bastien Giraud

Bastien Giraud has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150287722
    Abstract: An integrated circuit includes a substrate with first and second cells having first and second FDSOI field-effect transistors. There are first and second ground planes, a buried oxide layer and first and second wells, under the ground planes. The first well and the first ground plane have the same doping and the second well and the second ground plane have the same doping. The first and second cells are adjoined and their transistors are aligned in a first direction. The wells of the first cell and the first well of the second cell are doped opposite of the second well. A control device applies a first electrical bias to the wells with the first doping and a second electrical bias to the well with the second doping. The transistors of the first cell and second cell have different threshold voltage levels.
    Type: Application
    Filed: October 11, 2013
    Publication date: October 8, 2015
    Inventors: Bastien Giraud, Philippe Flatresse, Jean-Philippe Noel, Bertrand Pelloux-Prayer
  • Patent number: 9136366
    Abstract: An integrated circuit includes a silicon substrate, a ground plane above the substrate, a buried insulator layer above the ground plane, a silicon layer above the buried insulator layer and separated from the ground plane by the buried insulator layer, and an FDSOI transistor. The transistor has a channel adapted for being formed in the silicon layer, a source and drain in and/or on the silicon layer, and a gate covering an upper face of the channel and having a lateral portion covering a lateral face of the channel and above the ground plane. A distance between the lateral portion and the ground plane is not more than three nanometers and at least five times less than a thickness of the buried insulator layer between the ground plane and the silicon layer. The ground plane is separated from the gate by the buried insulator layer.
    Type: Grant
    Filed: January 16, 2014
    Date of Patent: September 15, 2015
    Assignees: Commissariat a l'energie atomique et aux energies alternatives, STMicroelectronics SA
    Inventors: Bastien Giraud, Jean-Philippe Noel, Maud Vinet
  • Patent number: 9092590
    Abstract: An IC including first and second FDSOI UTBOX cells arranged in a row, the first having an nMOS transistor arranged plumb with and above a ground plane and an N-type well, and a pMOS transistor arranged plumb with and above a ground plane and a P-type well, the N-type well and the P-type well being arranged on either side of a row axis, wherein the second includes a diode protecting against antenna effects or a well tap cell, the second cell comprising a P-type well arranged in the alignment of the P-type well of the pMOS transistor and comprising an N-type well arranged in the alignment of the N-type well of the nMOS transistor, the second cell comprising a metal connection coupled to its P-type well and coupled to a higher-level metal connection element arranged plumb with the N-type well, the metal connection extending on either side of the axis.
    Type: Grant
    Filed: December 13, 2013
    Date of Patent: July 28, 2015
    Assignees: Commissariat a l'energie atomique et aux energies alternatives, STMicroelectronics SA
    Inventors: Bastien Giraud, Philippe Flatresse, Matthieu Le Boulaire, Jean-Philippe Noel
  • Patent number: 9093499
    Abstract: A manufacture includes an IC comprising a stacking of a semiconducting substrate, a buried insulating layer, and a semiconducting layer, a first electronic component formed in and/or on the semiconductor layer, a bias circuit to generate a first bias voltage, first and second via-type interconnections, to which the bias circuit applies a same bias voltage equal to the first bias voltage, a first insulation trench separating the first electronic component from the first and second interconnections, a first ground plane having a first type of doping, placed beneath the buried insulating layer plumb with the first electronic component, and extending beneath the first insulation trench and up into contact the first interconnection, and a first well having a second type of doping opposite that of the first type, plumb with the first ground plane, and extending beneath the first insulation trench and up into contact with the second interconnection.
    Type: Grant
    Filed: September 26, 2012
    Date of Patent: July 28, 2015
    Assignee: Commissariat à l'énergie atomique et aux énergies alternatives
    Inventors: Jean-Philippe Noel, Bastien Giraud, Olivier Thomas
  • Patent number: 9000840
    Abstract: An integrated with a block including first and second oppositely doped semiconductor wells. There are standard cells placed next to one another, each standard cell including first transistors and a clock tree cell encircled by standard cells. The clock tree cell has a third semiconductor well with the same doping type as the doping of the first well and second transistors. The clock tree cell also has a semiconductor strip extending continuously around the third well and having the opposite doping type to the doping of the third well to electrically isolate the third well from the first well.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: April 7, 2015
    Assignees: Commissariat à l'énergie atomique et aux énergies alternatives, STMicroeletronics SA, STMicroeletronics (Crolles 2) SAS
    Inventors: Yvain Thonnart, Bastien Giraud, Fady Abouzeid, Sylvain Clerc, Jean-Philippe Noel
  • Patent number: 8969967
    Abstract: An integrated circuit includes a stack having a semiconductor substrate with a first type of dopant, an UTBOX type buried insulating layer, electronic components, formed in the substrate, ground planes disposed beneath the buried insulating layer so as to be respectively plumb with corresponding components, wells with the first type of dopant, the wells being respectively beneath corresponding ground planes, and a bias circuit enabling distinct voltages to be applied to the ground planes by the wells. The wells are separated from the substrate by a deep well with a second type of dopant. The wells are separated from each other by a separating structure, which is either a lateral well having a second type of dopant or a block of insulating material.
    Type: Grant
    Filed: May 22, 2012
    Date of Patent: March 3, 2015
    Assignee: Commissariat a l'energie et aux energies alternatives
    Inventors: Jean-Philippe Noel, Bastien Giraud, Olivier Thomas
  • Patent number: 8937505
    Abstract: The invention relates to an integrated circuit comprising: a first semiconductor well (60); a plurality of standard cells (66), each standard cell comprising a first field-effect transistor in FDSOI technology comprising a first semiconductor ground plane located immediately on the first well; and a clock tree cell (30) contiguous with the standard cells, the clock tree cell comprising a second field-effect transistor in FDSOI technology, which transistor comprises a second semiconductor ground plane located immediately on the first well (60), so as to form a p-n junction with this first well. The integrated circuit comprises an electrical power supply network (51) able to apply separate electrical biases directly to the first and second ground planes.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: January 20, 2015
    Assignees: Commissariat a l'Energie Atomique et aux Energies Alternatives, STMicroelectronics SA, STMicroelectronics (Crolles 2) SAS
    Inventors: Bastien Giraud, Fady Abouzeid, Sylvain Clerc, Jean-Philippe Noel, Yvain Thonnart
  • Publication number: 20140292374
    Abstract: A method for controlling an IC having logic cells and a clock-tree cell. Each logic cell has first and second FETs, which are pMOS and nMOS respectively. The clock-tree cell includes third and fourth FETs, which are pMOS and nMOS respectively. The clock-tree cell provides a clock signal to the logic cells. A back gate potential difference (“BGPD”) of a pMOS-FET is a difference between its source potential less its back-gate potential, and vice versa for an nMOS-FET. The method includes applying first and second back gate potential difference (BGPD) to a logic cell's first and second FETs and either applying a third BGPD to a third FET, wherein the third BGPD is positive and greater than the first BGPD applied, which is applied concurrently, or applying a fourth BGEPD to a fourth FET, wherein the fourth BGPD is positive and greater than the second BGPD that is applied concurrently.
    Type: Application
    Filed: March 26, 2014
    Publication date: October 2, 2014
    Inventors: Bastien Giraud, Fady Abouzeid, Sylvain Clerc, Jean-Philippe Noel, Philippe Roche, Yvain Thonnart
  • Publication number: 20140231916
    Abstract: An integrated circuit includes a silicon substrate, a ground plane above the substrate, a buried insulator layer above the ground plane, a silicon layer above the buried insulator layer and separated from the ground plane by the buried insulator layer, and an FDSOI transistor. The transistor has a channel adapted for being formed in the silicon layer, a source and drain in and/or on the silicon layer, and a gate covering an upper face of the channel and having a lateral portion covering a lateral face of the channel and above the ground plane. A distance between the lateral portion and the ground plane is not more than three nanometers and at least five times less than a thickness of the buried insulator layer between the ground plane and the silicon layer. The ground plane is separated from the gate by the buried insulator layer.
    Type: Application
    Filed: January 16, 2014
    Publication date: August 21, 2014
    Inventors: Bastien Giraud, Jean-Philippe Noel, Maud Vinet
  • Publication number: 20140176216
    Abstract: The invention relates to an integrated circuit comprising: a block comprising: first (38) and second (40) oppositely doped semiconductor wells; standard cells (42, 43) placed next to one another, each standard cell (42) comprising first transistors (60, 62), and a clock tree cell (30) encircled by standard cells, the clock tree cell (30) comprising: a third semiconductor well (104) having the same doping type as the doping of the first well (38); second transistors (100, 102); a semiconductor strip (106) extending continuously around the third well (104), and having the opposite doping type to the doping of the third well, so as to electrically isolate the third well (104) from the first well (38).
    Type: Application
    Filed: December 19, 2013
    Publication date: June 26, 2014
    Inventors: Yvain Thonnart, Bastien Giraud, Fady Abouzeid, Sylvain Clerc, Jean-Philippe Noel
  • Publication number: 20140176228
    Abstract: The invention relates to an integrated circuit comprising: a first semiconductor well (60); a plurality of standard cells (66), each standard cell comprising a first field-effect transistor in FDSOI technology comprising a first semiconductor ground plane located immediately on the first well; and a clock tree cell (30) contiguous with the standard cells, the clock tree cell comprising a second field-effect transistor in FDSOI technology, which transistor comprises a second semiconductor ground plane located immediately on the first well (60), so as to form a p-n junction with this first well. The integrated circuit comprises an electrical power supply network (51) able to apply separate electrical biases directly to the first and second ground planes.
    Type: Application
    Filed: December 19, 2013
    Publication date: June 26, 2014
    Inventors: Bastien Giraud, Fady Abouzeid, Sylvain Clerc, Jean-Philippe Noel, Yvain Thonnart
  • Publication number: 20140173544
    Abstract: An IC including first and second FDSOI UTBOX cells arranged in a row, the first having an nMOS transistor arranged plumb with and above a ground plane and an N-type well, and a pMOS transistor arranged plumb with and above a ground plane and a P-type well, the N-type well and the P-type well being arranged on either side of a row axis, wherein the second includes a diode protecting against antenna effects or a well tap cell, the second cell comprising a P-type well arranged in the alignment of the P-type well of the pMOS transistor and comprising an N-type well arranged in the alignment of the N-type well of the nMOS transistor, the second cell comprising a metal connection coupled to its P-type well and coupled to a higher-level metal connection element arranged plumb with the N-type well, the metal connection extending on either side of the axis.
    Type: Application
    Filed: December 13, 2013
    Publication date: June 19, 2014
    Inventors: Bastien Giraud, Philippe Flatresse, Matthieu Le Boulaire, Jean-Philippe Noel
  • Publication number: 20140077300
    Abstract: An integrated circuit includes a stack having a semiconductor substrate with a first type of dopant, an UTBOX type buried insulating layer, electronic components, formed in the substrate, ground planes disposed beneath the buried insulating layer so as to be respectively plumb with corresponding components, wells with the first type of dopant, the wells being respectively beneath corresponding ground planes, and a bias circuit enabling distinct voltages to be applied to the ground planes by the wells. The wells are separated from the substrate by a deep well with a second type of dopant. The wells are separated from each other by a separating structure, which is either a lateral well having a second type of dopant or a block of insulating material.
    Type: Application
    Filed: May 22, 2012
    Publication date: March 20, 2014
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Jean-Philippe Noel, Bastien Giraud, Olivier Thomas
  • Patent number: 8482070
    Abstract: An IC has cells placed in a cell row having a UTBOX-FDSOI pMOSFET including a ground beneath the pMOS, and an n-doped well beneath it and configured to apply a potential thereto, and a UTBOX-FDSOI nMOSFET including a ground beneath the nMOS, and a p-doped well beneath the ground and configured to apply a potential thereto, and cells, each including a UTBOX-FDSOI pMOSFET including a ground beneath the pMOS, and a p-doped well beneath the ground and configured to apply an electrical potential to the ground, and a UTBOX-FDSOI nMOSFET including a ground beneath the nMOS, and an n-doped well beneath the ground and configured to apply a potential thereto. The cells are placed so that pMOS's of standard cells belonging to a row align along it and a transition cell including a another well and contiguous with first row standard cells thus ensuring continuity with wells of those cells.
    Type: Grant
    Filed: August 1, 2012
    Date of Patent: July 9, 2013
    Assignee: STMicroelectronics (Crolles 2)
    Inventors: Philippe Flatresse, Bastien Giraud, Jean-Philippe Noel, Matthieu Le Boulaire
  • Publication number: 20130089978
    Abstract: A manufacture includes an IC comprising a stacking of a semiconducting substrate, a buried insulating layer, and a semiconducting layer, a first electronic component formed in and/or on the semiconductor layer, a bias circuit to generate a first bias voltage, first and second via-type interconnections, to which the bias circuit applies a same bias voltage equal to the first bias voltage, a first insulation trench separating the first electronic component from the first and second interconnections, a first ground plane having a first type of doping, placed beneath the buried insulating layer plumb with the first electronic component, and extending beneath the first insulation trench and up into contact the first interconnection, and a first well having a second type of doping opposite that of the first type, plumb with the first ground plane, and extending beneath the first insulation trench and up into contact with the second interconnection.
    Type: Application
    Filed: September 26, 2012
    Publication date: April 11, 2013
    Applicant: Commissariat a l'energie atomique et aux energies alternatives
    Inventors: Jean-Philippe Noel, Bastien Giraud, Olivier Thomas
  • Patent number: 8320198
    Abstract: A random access memory cell including: two double-gate access transistors respectively arranged between a first bit line and a first storage node and between a second bit line and a second storage node, a word line, a first double-gate load transistor and a second double-gate load transistor, a first double-gate driver transistor and a second double-gate driver transistor, a mechanism to apply a given potential to at least one electrode of each of the load or driver transistors, and a mechanism to cause the given potential to vary.
    Type: Grant
    Filed: February 16, 2009
    Date of Patent: November 27, 2012
    Assignee: Commissariat a l'Energie Atomique et aux Energies Alternatives
    Inventors: Olivier Thomas, Bastien Giraud
  • Publication number: 20100315889
    Abstract: A random access memory cell including: two double-gate access transistors respectively arranged between a first bit line and a first storage node and between a second bit line and a second storage node, a word line, a first double-gate load transistor and a second double-gate load transistor, a first double-gate driver transistor and a second double-gate driver transistor, a mechanism to apply a given potential to at least one electrode of each of the load or driver transistors, and a mechanism to cause the given potential to vary.
    Type: Application
    Filed: February 16, 2009
    Publication date: December 16, 2010
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALT
    Inventors: Olivier Thomas, Bastien Giraud
  • Patent number: 7733688
    Abstract: The random access memory cell of SRAM type comprises an access transistor provided with a gate electrode connected to a word line. The access transistor is connected between a bit line and a gate electrode of a first load transistor itself connected to a gate electrode of a driver transistor and to a first source/drain electrode of a second load transistor. The first load transistor and the driver transistor, in series, form an inverter at the supply voltage terminals. At least the transistors not comprised in the inverter comprise two electrically independent gate electrodes. The second gate electrode of the access transistor is connected to the first gate electrode of the second load transistor and the second gate electrode of the latter is connected to the supply voltage.
    Type: Grant
    Filed: May 29, 2008
    Date of Patent: June 8, 2010
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Bastien Giraud, Amara Amara
  • Publication number: 20080298118
    Abstract: The random access memory cell of SRAM type comprises an access transistor provided with a gate electrode connected to a word line. The access transistor is connected between a bit line and a gate electrode of a first load transistor itself connected to a gate electrode of a driver transistor and to a first source/drain electrode of a second load transistor. The first load transistor and the driver transistor, in series, form an inverter at the supply voltage terminals. At least the transistors not comprised in the inverter comprise two electrically independent gate electrodes. The second gate electrode of the access transistor is connected to the first gate electrode of the second load transistor and the second gate electrode of the latter is connected to the supply voltage.
    Type: Application
    Filed: May 29, 2008
    Publication date: December 4, 2008
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE
    Inventors: Bastien Giraud, Amara Amara