Patents by Inventor Bastien Giraud
Bastien Giraud has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10741565Abstract: The application relates to an integrated circuit with SRAM memory and provided with several superimposed levels of transistors, the integrated circuit including SRAM cells provided with a first transistor and a second transistor belonging to an upper level of transistors and each having a double gate composed of an upper electrode and a lower electrode laid out on either side of a semiconductor layer, a lower gate electrode of the first transistor being connected to a lower gate electrode of the second transistor.Type: GrantFiled: April 9, 2019Date of Patent: August 11, 2020Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, STMicroelectronics (Crolles 2) SASInventors: Francois Andrieu, Remy Berthelon, Bastien Giraud
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Publication number: 20200227098Abstract: A Memory device comprising a matrix of memory cells, the matrix being provided with at least one first column, the device also being provided with a test circuit configured to perform a test phase during a read operation to indicate whether or not the proportion of cells in said column storing the same logical data, particularly a logical ‘1’, is greater than a predetermined threshold.Type: ApplicationFiled: January 9, 2020Publication date: July 16, 2020Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Jean-Philippe NOEL, Reda Boumchedda, Bastien Giraud
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Publication number: 20200185392Abstract: A 3D-RAM memory comprising: several memory cell arrays distributed in several superimposed memory layers; a word line driver; a row decoder coupled to the word line driver; wherein the row decoder and the word line driver are arranged in a layer of command electronics which is separate from the memory layers, and wherein, in each of the memory layers, each of the word lines is connected to an output of an electronic selection device arranged in the memory layer, a data input of which is connected to the word line driver, a command input of which is connected to the row decoder, and which is configured to let a signal of access to the transistors pass or not depending on the value of a received command signal.Type: ApplicationFiled: December 10, 2019Publication date: June 11, 2020Applicant: Commissariat A L'Energie Atomique et aux Energies AlternativesInventors: Adam MAKOSIEJ, Bastien GIRAUD, Jean-Philippe NOEL
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Patent number: 10559355Abstract: The invention relates to a resistive memory (5) including resistive elements, the resistance of each resistive element being capable of alternating between a high value in a first range of values and a low value in a second range of values smaller than the high value, the memory further comprising a device (14) for switching the resistance of at least one resistive element selected from among the resistive elements between the high and low values, the device including a first circuit capable of applying an increasing voltage across the selected resistive element while the selected resistive element is at the high value or at the low value, a second circuit capable of detecting the switching of the resistance of the selected resistive element, and a third circuit capable of interrupting the current flowing through the selected resistive element on detection of the switching.Type: GrantFiled: September 8, 2015Date of Patent: February 11, 2020Assignee: Commissariat a l'energie atomique et aux energies alternativesInventors: Michel Harrand, Elisa Vianello, Olivier Thomas, Bastien Giraud
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Publication number: 20190312039Abstract: The application relates to an integrated circuit with SRAM memory and provided with several superimposed levels of transistors, the integrated circuit including SRAM cells provided with a first transistor and a second transistor belonging to an upper level of transistors and each having a double gate composed of an upper electrode and a lower electrode laid out on either side of a semiconductor layer, a lower gate electrode of the first transistor being connected to a lower gate electrode of the second transistor.Type: ApplicationFiled: April 9, 2019Publication date: October 10, 2019Applicants: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, STMicroelectronics (Crolles 2) SASInventors: Francois Andrieu, Remy Berthelon, Bastien Giraud
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Publication number: 20190198094Abstract: A memory circuit including a plurality of elementary cells arranged in a plurality of arrays, each including a plurality of rows and a plurality of columns, and wherein: the elementary cells having the same coordinates in the different arrays share a same first conductive track; and in each array, the elementary cells of a same row of the array share a same second conductive track and a same third conductive track.Type: ApplicationFiled: December 21, 2018Publication date: June 27, 2019Applicant: Commissariat à l'Énergie Atomique et aux Énergies AlternativesInventors: Jean-Philippe Noel, Bastien Giraud, Adam Makosiej
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Publication number: 20190189198Abstract: A memory circuit including a plurality of elementary cells distributed in a plurality of arrays, each including N columns, N being an integer greater than or equal to 2, wherein: each column of each array includes a first local bit line directly connected to each of the cells in the column; each column of each array includes a first general bit line coupled to the first local bit line of the column by a first coupling circuit; and the first general bit lines of the columns of same rank j of the different arrays, j being an integer in the range from 0 to M?1, are coupled together.Type: ApplicationFiled: December 18, 2018Publication date: June 20, 2019Applicant: Commissariat à l'Énergie Atomique et aux Énergies AlternativesInventors: Jean-Philippe Noel, Avishek Biswas, Bastien Giraud
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Publication number: 20190189199Abstract: A memory circuit including a plurality of elementary cells arranged in an array of rows and of columns, and a control circuit capable of implementing an operation of vertical reading of a word from a column of the array.Type: ApplicationFiled: December 18, 2018Publication date: June 20, 2019Applicant: Commissariat à l'Énergie Atomique et aux Énergies AlternativesInventors: Jean-Philippe Noel, Bastien Giraud
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Patent number: 10297319Abstract: A memory circuit including cells connected in rows and in columns, each cell including a programmable resistive element and a control transistor, the memory circuit further including a control circuit capable of, during a cell programming phase: applying a first voltage to a control conductive track of the column including the cell; applying a second voltage to the first control conductive track of the row including the cell; applying a third voltage capable of turning on the cell control transistor to a second row control conductive track including the cell; and applying a fourth voltage capable of turning off the control transistors to the control conductive tracks of columns which do not include the cell.Type: GrantFiled: April 13, 2017Date of Patent: May 21, 2019Assignee: Commissariat à l'Énergie Atomique et aux Énergies AlternativesInventors: Bastien Giraud, Alexandre Levisse, Jean-Philippe Noel
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Publication number: 20180277197Abstract: A SRAM cell, including, in a stack of layers, transistors including at least first and second access transistors connected to a word line, the first access transistor coupling a first bit line and a first storage node and the second access transistor coupling a second bit line and a second storage node, and a flip-flop including a first conduction transistor coupling the first storage node to a source of a first reference potential and having its gate coupled to the second storage node and a second conduction transistor coupling the second storage node to the source of the first reference potential and having its gate coupled to the first storage node.Type: ApplicationFiled: March 27, 2018Publication date: September 27, 2018Applicant: Commissariat à l'Énergie Atomique et aux Énergies AlternativesInventors: Jean-Philippe Noel, Kaya Can Akyel, Bastien Giraud
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Patent number: 9911737Abstract: An integrated circuit includes a substrate with first and second cells having first and second FDSOI field-effect transistors. There are first and second ground planes, a buried oxide layer and first and second wells, under the ground planes. The first well and the first ground plane have the same doping and the second well and the second ground plane have the same doping. The first and second cells are adjoined and their transistors are aligned in a first direction. The wells of the first cell and the first well of the second cell are doped opposite of the second well. A control device applies a first electrical bias to the wells with the first doping and a second electrical bias to the well with the second doping. The transistors of the first cell and second cell have different threshold voltage levels.Type: GrantFiled: October 11, 2013Date of Patent: March 6, 2018Assignee: STMicroelectronics SAInventors: Bastien Giraud, Philippe Flatresse, Jean-Philippe Noel, Bertrand Pelloux-Prayer
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Publication number: 20170316825Abstract: A memory circuit including cells connected in rows and in columns, each cell including a programmable resistive element and a control transistor, the memory circuit further including a control circuit capable of, during a cell programming phase: applying a first voltage to a control conductive track of the column including the cell; applying a second voltage to the first control conductive track of the row including the cell; applying a third voltage capable of turning on the cell control transistor to a second row control conductive track including the cell; and applying a fourth voltage capable of turning off the control transistors to the control conductive tracks of columns which do not include the cell.Type: ApplicationFiled: April 13, 2017Publication date: November 2, 2017Applicant: Commissariat à l'Énergie Atomique et aux Énergies AlternativesInventors: Bastien Giraud, Alexandre Levisse, Jean-Philippe Noel
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Patent number: 9542996Abstract: A memory device includes a matrix of several columns of SRAM memory cells each including transistors forming a memory point, a read port and a write port, and such that the transistors of the read port and/or the P-type transistors include a second well with a conductivity type opposite that of a first well of the other transistors. The memory device also includes a polarization unit for the second wells, able to select and apply polarization potentials on the second wells, including a memory circuit of the polarization states of the second wells for each column or group of columns and a selection circuit applying a polarization potential on the second wells according to one of the values received as input, as a function of the stored polarization state associated with the column or group of columns.Type: GrantFiled: September 10, 2015Date of Patent: January 10, 2017Assignee: Commissariat à l'énergie atomique et aux énergies alternativesInventors: Olivier Thomas, Bastien Giraud, Adam Makosiej
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Patent number: 9508434Abstract: A non-volatile memory including a plurality of elementary cells, each cell including: a first programmable-resistance storage element connected between first and second nodes of the cell; a first access transistor coupling the second node to a third node of the cell; and a second access transistor coupling the second node to a fourth node of the cell.Type: GrantFiled: July 23, 2015Date of Patent: November 29, 2016Assignee: Commissariat à l'Energie Atomique et aux Energies AlternativesInventors: Thomas-Medhi Benoist, Haithem Ayari, Bastien Giraud, Adam Makosiej, Yves Maneglia, Santhosh Onkaraiah, Jean-Michel Portal, Olivier Thomas
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Patent number: 9479168Abstract: A method for controlling an IC having logic cells and a clock-tree cell. Each logic cell has first and second FETs, which are pMOS and nMOS respectively. The clock-tree cell includes third and fourth FETs, which are pMOS and nMOS respectively. The clock-tree cell provides a clock signal to the logic cells. A back gate potential difference (“BGPD”) of a pMOS-FET is a difference between its source potential less its back-gate potential, and vice versa for an nMOS-FET. The method includes applying first and second back gate potential difference (BGPD) to a logic cell's first and second FETs and either applying a third BGPD to a third FET, wherein the third BGPD is positive and greater than the first BGPD applied, which is applied concurrently, or applying a fourth BGEPD to a fourth FET, wherein the fourth BGPD is positive and greater than the second BGPD that is applied concurrently.Type: GrantFiled: March 26, 2014Date of Patent: October 25, 2016Assignees: Commissariat à l'énergie atomique et aux énergies alternatives, STMicroelectronics SA, STMicroelectronics (Crolles 2) SASInventors: Bastien Giraud, Fady Abouzeid, Sylvain Clerc, Jean-Philippe Noel, Philippe Roche, Yvain Thonnart
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Patent number: 9449688Abstract: The invention relates to a resistive memory including resistive elements, the resistance of each resistive element being capable of alternating between a high value and a low value, the memory further including a device for switching the resistance of at least one selected resistive element between the high and low values. The device includes a first circuit capable of circulating a first current through a first reference resistive component (RLRS), a second circuit capable of circulating a second current proportional to the first current through the selected resistive element, a third circuit capable of detecting the switching of the resistance of the selected resistive element from the comparison of the voltage across the first reference resistive component with the voltage across the selected resistive element, and a fourth circuit capable of interrupting the second current on detection of the switching.Type: GrantFiled: September 8, 2015Date of Patent: September 20, 2016Assignee: Commissariat a l'energie atomique et aux energies alternativesInventors: Olivier Thomas, Bastien Giraud, Michel Harrand, Elisa Vianello
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Publication number: 20160078924Abstract: A memory device includes a matrix of several columns of SRAM memory cells each including transistors forming a memory point, a read port and a write port, and such that the transistors of the read port and/or the P-type transistors include a second well with a conductivity type opposite that of a first well of the other transistors. The memory device also includes a polarization unit for the second wells, able to select and apply polarization potentials on the second wells, including a memory circuit of the polarization states of the second wells for each column or group of columns and a selection circuit applying a polarization potential on the second wells according to one of the values received as input, as a function of the stored polarization state associated with the column or group of columns.Type: ApplicationFiled: September 10, 2015Publication date: March 17, 2016Applicant: Commissariat a L'Energie Atomique et aux Energies AlternativesInventors: Olivier THOMAS, Bastien GIRAUD, Adam MAKOSIEJ
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Publication number: 20160071589Abstract: The invention relates to a resistive memory including resistive elements, the resistance of each resistive element being capable of alternating between a high value and a low value, the memory further including a device for switching the resistance of at least one selected resistive element between the high and low values. The device includes a first circuit capable of circulating a first current through a first reference resistive component (RLRS), a second circuit capable of circulating a second current proportional to the first current through the selected resistive element, a third circuit capable of detecting the switching of the resistance of the selected resistive element from the comparison of the voltage across the first reference resistive component with the voltage across the selected resistive element, and a fourth circuit capable of interrupting the second current on detection of the switching.Type: ApplicationFiled: September 8, 2015Publication date: March 10, 2016Inventors: Olivier Thomas, Bastien Giraud, Michel Harrand, Elisa Vianello
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Publication number: 20160071588Abstract: The invention relates to a resistive memory (5) including resistive elements, the resistance of each resistive element being capable of alternating between a high value in a first range of values and a low value in a second range of values smaller than the high value, the memory further comprising a device (14) for switching the resistance of at least one resistive element selected from among the resistive elements between the high and low values, the device including a first circuit capable of applying an increasing voltage across the selected resistive element while the selected resistive element is at the high value or at the low value, a second circuit capable of detecting the switching of the resistance of the selected resistive element, and a third circuit capable of interrupting the current flowing through the selected resistive element on detection of the switching.Type: ApplicationFiled: September 8, 2015Publication date: March 10, 2016Inventors: Michel Harrand, Elisa Vianello, Olivier Thomas, Bastien Giraud
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Publication number: 20160027509Abstract: A non-volatile memory including a plurality of elementary cells, each cell including: a first programmable-resistance storage element connected between first and second nodes of the cell; a first access transistor coupling the second node to a third node of the cell; and a second access transistor coupling the second node to a fourth node of the cell.Type: ApplicationFiled: July 23, 2015Publication date: January 28, 2016Inventors: Thomas-Medhi BENOIST, Haithem AYARI, Bastien GIRAUD, Adam MAKOSIEJ, Yves MANEGLIA, Santhosh ONKARAIAH, Jean-Michel PORTAL, Olivier THOMAS