Patents by Inventor Behnam Moradi
Behnam Moradi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8729621Abstract: Disclosed is a method of forming memory devices employing halogen ion implantation and diffusion processes. In one illustrative embodiment, the method includes forming a plurality of word line structures above a semiconducting substrate, each of the word line structures comprising a gate insulation layer, performing an LDD ion implantation process to form LDD doped regions in the substrate between the word line structures, performing a halogen ion implantation process to implant atoms of halogen into the semiconducting substrate between the word line structures, and performing at least one anneal process to cause at least some of the atoms of halogen to diffuse into the gate insulation layers on adjacent word line structures.Type: GrantFiled: October 8, 2013Date of Patent: May 20, 2014Assignee: Micron Technology, Inc.Inventors: Kirk D. Prall, Behnam Moradi, Seiichi Aritome, Di Li, Chris Larsen
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Publication number: 20140035021Abstract: Disclosed is a method of forming memory devices employing halogen ion implantation and diffusion processes. In one illustrative embodiment, the method includes forming a plurality of word line structures above a semiconducting substrate, each of the word line structures comprising a gate insulation layer, performing an LDD ion implantation process to form LDD doped regions in the substrate between the word line structures, performing a halogen ion implantation process to implant atoms of halogen into the semiconducting substrate between the word line structures, and performing at least one anneal process to cause at least some of the atoms of halogen to diffuse into the gate insulation layers on adjacent word line structures.Type: ApplicationFiled: October 8, 2013Publication date: February 6, 2014Applicant: Micron Technology, Inc.Inventors: Kirk D. Prall, Behnam Moradi, Seiichi Aritome, Di Li, Chris Larsen
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Patent number: 8580645Abstract: Disclosed is a method of forming memory devices employing halogen ion implantation and diffusion processes. In one illustrative embodiment, the method includes forming a plurality of word line structures above a semiconducting substrate, each of the word line structures comprising a gate insulation layer, performing an LDD ion implantation process to form LDD doped regions in the substrate between the word line structures, performing a halogen ion implantation process to implant atoms of halogen into the semiconducting substrate between the word line structures, and performing at least one anneal process to cause at least some of the atoms of halogen to diffuse into the gate insulation layers on adjacent word line structures.Type: GrantFiled: March 6, 2013Date of Patent: November 12, 2013Assignee: Micron Technology, Inc.Inventors: Kirk D. Prall, Behnam Moradi, Seiichi Aritome, Di Li, Chris Larsen
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Patent number: 8415223Abstract: Disclosed is a method of forming memory devices employing halogen ion implantation and diffusion processes. In one illustrative embodiment, the method includes forming a plurality of word line structures above a semiconducting substrate, each of the word line structures comprising a gate insulation layer, performing an LDD ion implantation process to form LDD doped regions in the substrate between the word line structures, performing a halogen ion implantation process to implant atoms of halogen into the semiconducting substrate between the word line structures, and performing at least one anneal process to cause at least some of the atoms of halogen to diffuse into the gate insulation layers on adjacent word line structures.Type: GrantFiled: February 3, 2012Date of Patent: April 9, 2013Assignee: Micron Technology, Inc.Inventors: Kirk D. Prall, Behnam Moradi, Seiichi Aritome, Di Li, Chris Larsen
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Publication number: 20120132979Abstract: Disclosed is a method of forming memory devices employing halogen ion implantation and diffusion processes. In one illustrative embodiment, the method includes forming a plurality of word line structures above a semiconducting substrate, each of the word line structures comprising a gate insulation layer, performing an LDD ion implantation process to form LDD doped regions in the substrate between the word line structures, performing a halogen ion implantation process to implant atoms of halogen into the semiconducting substrate between the word line structures, and performing at least one anneal process to cause at least some of the atoms of halogen to diffuse into the gate insulation layers on adjacent word line structures.Type: ApplicationFiled: February 3, 2012Publication date: May 31, 2012Applicant: MICRON TECHNOLOGY, INC.Inventors: Kirk Prall, Behnam Moradi, Seiichi Aritome, Di Li, Chris Larsen
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Patent number: 8129781Abstract: Disclosed is a method of forming memory devices employing halogen ion implantation and diffusion processes. In one illustrative embodiment, the method includes forming a plurality of word line structures above a semiconducting substrate, each of the word line structures comprising a gate insulation layer, performing an LDD ion implantation process to form LDD doped regions in the substrate between the word line structures, performing a halogen ion implantation process to implant atoms of halogen into the semiconducting substrate between the word line structures, and performing at least one anneal process to cause at least some of the atoms of halogen to diffuse into the gate insulation layers on adjacent word line structures.Type: GrantFiled: September 28, 2010Date of Patent: March 6, 2012Assignee: Micron Technology, Inc.Inventors: Kirk D Prall, Behnam Moradi, Seiichi Aritome, Di Li, Chris Larsen
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Publication number: 20110013463Abstract: Disclosed is a method of forming memory devices employing halogen ion implantation and diffusion processes. In one illustrative embodiment, the method includes forming a plurality of word line structures above a semiconducting substrate, each of the word line structures comprising a gate insulation layer, performing an LDD ion implantation process to form LDD doped regions in the substrate between the word line structures, performing a halogen ion implantation process to implant atoms of halogen into the semiconducting substrate between the word line structures, and performing at least one anneal process to cause at least some of the atoms of halogen to diffuse into the gate insulation layers on adjacent word line structures.Type: ApplicationFiled: September 28, 2010Publication date: January 20, 2011Applicant: Micron Technology, Inc.Inventors: Kirk Prall, Behnam Moradi, Seiichi Aritome, Di Li, Chris Larsen
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Patent number: 7824994Abstract: Disclosed is a method of forming memory devices employing halogen ion implantation and diffusion processes. In one illustrative embodiment, the method includes forming a plurality of word line structures above a semiconducting substrate, each of the word line structures comprising a gate insulation layer, performing an LDD ion implantation process to form LDD doped regions in the substrate between the word line structures, performing a halogen ion implantation process to implant atoms of halogen into the semiconducting substrate between the word line structures, and performing at least one anneal process to cause at least some of the atoms of halogen to diffuse into the gate insulation layers on adjacent word line structures.Type: GrantFiled: November 14, 2008Date of Patent: November 2, 2010Assignee: Micron Technology, Inc.Inventors: Kirk Prall, Behnam Moradi, Seiichi Aritome, Di Li, Chris Larsen
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Publication number: 20090068812Abstract: Disclosed is a method of forming memory devices employing halogen ion implantation and diffusion processes. In one illustrative embodiment, the method includes forming a plurality of word line structures above a semiconducting substrate, each of the word line structures comprising a gate insulation layer, performing an LDD ion implantation process to form LDD doped regions in the substrate between the word line structures, performing a halogen ion implantation process to implant atoms of halogen into the semiconducting substrate between the word line structures, and performing at least one anneal process to cause at least some of the atoms of halogen to diffuse into the gate insulation layers on adjacent word line structures.Type: ApplicationFiled: November 14, 2008Publication date: March 12, 2009Inventors: Kirk Prall, Behnam Moradi, Seiichi Aritome, Di Li, Chris Larsen
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Patent number: 7492086Abstract: According to one aspect of the invention, a field emission display is provided comprising: an anode; a phosphor screen located on the anode; a cathode; an evacuated space between the anode and the cathode; an emitter located on the cathode opposite the phosphor; wherein the emitter comprises an electropositive element both in a body of the emitter and on a surface of the emitter. According to another aspect of the invention, a process for manufacturing a FED is provided comprising the steps of forming an emitter comprising an electropositive element in the body of the tip; positioning the emitter in opposing relation to a phosphor display screen; creating an evacuated space between the emitter tip and the phosphor display screen; and causing the electropositive element to migrate to an emission surface of the emitter.Type: GrantFiled: January 21, 2000Date of Patent: February 17, 2009Assignee: Micron Technology, Inc.Inventors: David A. Cathey, Surjit S. Chadha, Behnam Moradi
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Patent number: 7485528Abstract: Disclosed is a method of forming memory devices employing halogen ion implantation and diffusion processes. In one illustrative embodiment, the method includes forming a plurality of word line structures above a semiconducting substrate, each of the word line structures comprising a gate insulation layer, performing an LDD ion implantation process to form LDD doped regions in the substrate between the word line structures, performing a halogen ion implantation process to implant atoms of halogen into the semiconducting substrate between the word line structures, and performing at least one anneal process to cause at least some of the atoms of halogen to diffuse into the gate insulation layers on adjacent word line structures.Type: GrantFiled: July 14, 2006Date of Patent: February 3, 2009Assignee: Micron Technology, Inc.Inventors: Kirk Prall, Behnam Moradi, Seiichi Aritome, Di Li, Chris Larsen
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Publication number: 20080014698Abstract: Disclosed is a method of forming memory devices employing halogen ion implantation and diffusion processes. In one illustrative embodiment, the method includes forming a plurality of word line structures above a semiconducting substrate, each of the word line structures comprising a gate insulation layer, performing an LDD ion implantation process to form LDD doped regions in the substrate between the word line structures, performing a halogen ion implantation process to implant atoms of halogen into the semiconducting substrate between the word line structures, and performing at least one anneal process to cause at least some of the atoms of halogen to diffuse into the gate insulation layers on adjacent word line structures.Type: ApplicationFiled: July 14, 2006Publication date: January 17, 2008Inventors: Kirk Prall, Behnam Moradi, Seiichi Aritome, Di Li, Chris Larsen
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Publication number: 20060278913Abstract: A plurality of memory cell stacks are formed over a substrate. The substrate does not have diffusion regions between each memory cell stack to link the memory cells. The cells are formed close enough such that the memory cells are linked serially by the electric fields generated by each floating gate in the channel regions. In one embodiment, an n-layer is implanted at the top of the substrate to increase conductivity between cells. The select transistors can be linked to the serial string by diffusion regions or by interaction of the electric fields between the select transistor channel and the memory cell channel.Type: ApplicationFiled: June 8, 2005Publication date: December 14, 2006Inventors: Andrei Mihnea, Behnam Moradi, Paul Rudeck, Aritome Seiichi, Di Li
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Patent number: 6930446Abstract: A method is provided for manufacturing a field emission device, the method including operating the field emission device in a pressure of at most about 10?8 Torr for a selected period of time to evacuate outgassed materials and sealing the field emission device.Type: GrantFiled: August 31, 1999Date of Patent: August 16, 2005Assignee: Micron Technology, Inc.Inventor: Behnam Moradi
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Patent number: 6831403Abstract: Improved field emission display includes a buffer layer of copper, aluminum, silicon nitride or doped or undoped amorphous, poly, or microcrystalline silicon located between a chromium gate electrode and associated dielectric layer in a cathode assembly. The buffer layer substantially reduces or eliminates the occurrence of an adverse chemical reaction between the chromium gate electrode and dielectric layer.Type: GrantFiled: December 20, 2002Date of Patent: December 14, 2004Assignee: Micron Technology, Inc.Inventors: Behnam Moradi, Kanwal K. Raina, Michael J. Westphal
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Patent number: 6791113Abstract: The invention encompasses a method of forming a dielectric material. A nitrogen-comprising layer is formed on at least some of the surface of a rugged polysilicon substrate to form a first portion of a dielectric material. After the nitrogen-comprising layer is formed, at least some of the substrate is subjected to dry oxidation with one or both of NO and N2O to form a second portion of the dielectric material. The invention also encompasses a method of forming a capacitor. A layer of rugged silicon is formed over a substrate, and a nitrogen-comprising layer is formed on the layer of rugged silicon. Some of the rugged silicon is exposed through the nitrogen-comprising layer. After the nitrogen-comprising layer is formed, at least some of the exposed rugged silicon is subjected to dry oxidation conditions with one or both of NO and N2O. Subsequently, a conductive material layer is formed over the nitrogen-comprising layer. Additionally, the invention encompasses a capacitor structure.Type: GrantFiled: April 15, 2003Date of Patent: September 14, 2004Assignee: Micron Technology, Inc.Inventors: Behnam Moradi, Er-Xuan Ping, Lingyi A. Zheng, John Packard
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Publication number: 20040104658Abstract: A structure and method are provided to inhibit degradation to the electron beam of a field emitter device by coating the field emitter tip with a substance or a compound. The substance or compound acts in the presence of outgassing to inhibit such degradation. In one embodiment, the substance or compound coating the field emitter tip is stable in the presence of outgassing. In another embodiment, the substance or compound decomposes at least one matter in the outgassing. In yet another embodiment, the substance or compound neutralizes at least one matter in the outgassing. In a further embodiment, the substance or compound brings about a catalysis in the presence of outgassing.Type: ApplicationFiled: November 20, 2003Publication date: June 3, 2004Applicant: Micron Technology, Inc.Inventors: Behnam Moradi, Tian Zhang, John Lee
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Patent number: 6692323Abstract: A structure and method are provided to inhibit degradation to the electron beam of a field emitter device by coating the field emitter tip with a substance or a compound. The substance or compound acts in the presence of outgassing to inhibit such degradation. In one embodiment, the substance or compound coating the field emitter tip is stable in the presence of outgassing. In another embodiment, the substance or compound decomposes at least one matter in the outgassing. In yet another embodiment, the substance or compound neutralizes at least one matter in the outgassing. In a further embodiment, the substance or compound brings about a catalysis in the presence of outgassing.Type: GrantFiled: January 14, 2000Date of Patent: February 17, 2004Assignee: Micron Technology, Inc.Inventors: Behnam Moradi, Tian Zhang, John Lee
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Publication number: 20030203581Abstract: The invention encompasses a method of forming a dielectric material. A nitrogen-comprising layer is formed on at least some of the surface of a rugged polysilicon substrate to form a first portion of a dielectric material. After the nitrogen-comprising layer is formed, at least some of the substrate is subjected to dry oxidation with one or both of NO and N2O to form a second portion of the dielectric material. The invention also encompasses a method of forming a capacitor. A layer of rugged silicon is formed over a substrate, and a nitrogen-comprising layer is formed on the layer of rugged silicon. Some of the rugged silicon is exposed through the nitrogen-comprising layer. After the nitrogen-comprising layer is formed, at least some of the exposed rugged silicon is subjected to dry oxidation conditions with one or both of NO and N2O. Subsequently, a conductive material layer is formed over the nitrogen-comprising layer. Additionally, the invention encompasses a capacitor structure.Type: ApplicationFiled: April 15, 2003Publication date: October 30, 2003Inventors: Behnam Moradi, Er-Xuan Ping, Lingyi A. Zheng, John Packard
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Patent number: 6607965Abstract: The invention encompasses a method of forming a dielectric material. A nitrogen-comprising layer is formed on at least some of the surface of a rugged polysilicon substrate to form a first portion of a dielectric material. After the nitrogen-comprising layer is formed, at least some of the substrate is subjected to dry oxidation with one or both of NO and N2O to form a second portion of the dielectric material. The invention also encompasses a method of forming a capacitor. A layer of rugged silicon is formed over a substrate, and a nitrogen-comprising layer is formed on the layer of rugged silicon. Some of the rugged silicon is exposed through the nitrogen-comprising layer. After the nitrogen-comprising layer is formed, at least some of the exposed rugged silicon is subjected to dry oxidation conditions with one or both of NO and N2O. Subsequently, a conductive material layer is formed over the nitrogen-comprising layer.Type: GrantFiled: November 29, 2001Date of Patent: August 19, 2003Assignee: Micron Technology, Inc.Inventors: Behnam Moradi, Er-Xuan Ping, Lingyi A. Zheng, John Packard