Patents by Inventor Behnam Moradi
Behnam Moradi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6583441Abstract: The invention encompasses a method of forming a dielectric material. A nitrogen-comprising layer is formed on at least some of the surface of a rugged polysilicon substrate to form a first portion of a dielectric material. After the nitrogen-comprising layer is formed, at least some of the substrate is subjected to dry oxidation with one or both of NO and N2O to form a second portion of the dielectric material. The invention also encompasses a method of forming a capacitor. A layer of rugged silicon is formed over a substrate, and a nitrogen-comprising layer is formed on the layer of rugged silicon. Some of the rugged silicon is exposed through the nitrogen-comprising layer. After the nitrogen-comprising layer is formed, at least some of the exposed rugged silicon is subjected to dry oxidation conditions with one or both of NO and N2O. Subsequently, a conductive material layer is formed over the nitrogen-comprising layer. Additionally, the invention encompasses a capacitor structure.Type: GrantFiled: November 29, 2001Date of Patent: June 24, 2003Assignee: Micron Technology, Inc.Inventors: Behnam Moradi, Er-Xuan Ping, Lingyi A. Zheng, John Packard
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Publication number: 20030094892Abstract: Improved field emission display includes a buffer layer of copper, aluminum, silicon nitride or doped or undoped amorphous, poly, or microcrystalline silicon located between a chromium gate electrode and associated dielectric layer in a cathode assembly. The buffer layer substantially reduces or eliminates the occurrence of an adverse chemical reaction between the chromium gate electrode and dielectric layer.Type: ApplicationFiled: December 20, 2002Publication date: May 22, 2003Applicant: Micron Technology, Inc.Inventors: Behnam Moradi, Kanwal K. Raina, Michael J. Westphal
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Patent number: 6562684Abstract: The invention encompasses a method of forming a dielectric material. A nitrogen-comprising layer is formed on at least some of the surface of a rugged polysilicon substrate to form a first portion of a dielectric material. After the nitrogen-comprising layer is formed, at least some of the substrate is subjected to dry oxidation with one or both of NO and N2O to form a second portion of the dielectric material. The invention also encompasses a method of forming a capacitor. A layer of rugged silicon is formed over a substrate, and a nitrogen-comprising layer is formed on the layer of rugged silicon. Some of the rugged silicon is exposed through the nitrogen-comprising layer. After the nitrogen-comprising layer is formed, at least some of the exposed rugged silicon is subjected to dry oxidation conditions with one or both of NO and N2O. Subsequently, a conductive material layer is formed over the nitrogen-comprising layer. Additionally, the invention encompasses a capacitor structure.Type: GrantFiled: August 30, 2000Date of Patent: May 13, 2003Assignee: Micron Technology, Inc.Inventors: Behnam Moradi, Er-Xuan Ping, Lingyi A. Zheng, John Packard
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Patent number: 6518699Abstract: An emitter substructure and methods for manufacturing the substructure are described. A substrate has a p-region formed at a surface of the substrate. A n-tank is formed such that the p-region surrounds a periphery of the n-tank. An emitter is formed on and electrically coupled to the n-tank. A dielectric layer is formed on the substrate that includes an opening surrounding the emitter. An extraction grid is formed on the dielectric layer. The extraction grid includes an opening surrounding and in close proximity to a tip of the emitter. An insulating region is formed at a lower boundary of the n-tank. The insulating region electrically isolates the emitter and the n-tank along at least a portion of the lower boundary beneath the opening. The insulating region thus functions to displace a depletion region associated with a boundary between the p-region and the n-tank from an area that can be illuminated by photons traveling through the extraction grid or openings in the extraction grid.Type: GrantFiled: July 17, 2001Date of Patent: February 11, 2003Assignee: Micron Technology, Inc.Inventors: John K. Lee, Behnam Moradi
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Patent number: 6515414Abstract: According to one aspect of the invention, a field emission display is provided comprising: an anode; a phosphor screen located on the anode; a cathode; an evacuated space between the anode and the cathode; an emitter located on the cathode opposite the phosphor; wherein the emitter comprises an electropositive element both in a body of the emitter and on a surface of the emitter. According to another aspect of the invention a process for manufacturing an FED is provided comprising the steps of: forming an emitter comprising an electropositive element in the body of the tip; positioning the emitter in opposing relation to a phosphor display screen; creating an evacuated space between the emitter tip and the phosphor display screen; and causing the electropositive element to migrate to the an emission surface of the emitter.Type: GrantFiled: May 1, 2000Date of Patent: February 4, 2003Assignee: Micron Technology, Inc.Inventors: David A. Cathey, Surjit S. Chadha, Behnam Moradi
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Patent number: 6509686Abstract: Improved field emission display includes a buffer layer of copper, aluminum, silicon nitride or doped or undoped amorphous, poly, or microcrystalline silicon located between a chromium gate electrode and associated dielectric layer in a cathode assembly. The buffer layer substantially reduces or eliminates the occurrence of an adverse chemical reaction between the chromium gate electrode and dielectric layer.Type: GrantFiled: September 16, 1999Date of Patent: January 21, 2003Assignee: Micron Technology, Inc.Inventors: Behnam Moradi, Kanwal K. Raina, Michael J. Westphal
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Patent number: 6507329Abstract: A semiconductor device for use in field emission displays includes a substrate formed from a semiconductor material, glass, soda lime, or plastic. A first layer of a conductive material is formed on the substrate. A second layer of microcrystalline silicon is formed on the first layer. This layer has characteristics that do not fluctuate in response to conditions that vary during the operation of the field emission display, particularly the varying light intensity from the emitted electrons or from the ambient. One or more cold-cathode emitters are formed on the second layer.Type: GrantFiled: January 30, 2001Date of Patent: January 14, 2003Assignee: Micron Technology, Inc.Inventors: David A. Cathey, Jr., Kevin W. Tjaden, Behnam Moradi, John K. Lee, James J. Alwan
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Publication number: 20030001152Abstract: An emitter substructure and methods for manufacturing the substructure are described. A substrate has a p-region formed at a surface of the substrate. A n-tank is formed such that the p-region surrounds a periphery of the n-tank. An emitter is formed on and electrically coupled to the n-tank. A dielectric layer is formed on the substrate that includes an opening surrounding the emitter. An extraction grid is formed on the dielectric layer. The extraction grid includes an opening surrounding and in close proximity to a tip of the emitter. An insulating region is formed at a lower boundary of the n-tank. The insulating region electrically isolates the emitter and the n-tank along at least a portion of the lower boundary beneath the opening. The insulating region thus functions to displace a depletion region associated with a boundary between the p-region and the n-tank from an area that can be illuminated by photons traveling through the extraction grid or openings in the extraction grid.Type: ApplicationFiled: July 17, 2001Publication date: January 2, 2003Inventors: John K. Lee, Behnam Moradi
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Patent number: 6471561Abstract: A field emission display apparatus includes a plurality of emitters formed on a substrate. Each of the emitters includes a titanium silicide nitride outer layer so that the emitters are less susceptible to degradation. A dielectric layer is formed on the substrate and the emitters, and an opening is formed in the dielectric layer surrounding each of the emitters. A conductive extraction grid is formed on the dielectric layer substantially in a plane defined by the emitters, and includes an opening surrounding each of the emitters. A cathodoluminescent faceplate having a planar surface is disposed parallel to the substrate.Type: GrantFiled: July 25, 2001Date of Patent: October 29, 2002Assignee: Micron Technology, Inc.Inventors: Tianhong Zhang, John K. Lee, Behnam Moradi
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Patent number: 6436788Abstract: An emitter substructure and methods for manufacturing the substructure are described. A substrate has a p-region formed at a surface of the substrate. A n-tank is formed such that the p-region surrounds a periphery of the n-tank. An emitter is formed on and electrically coupled to the n-tank. A dielectric layer is formed on the substrate that includes an opening surrounding the emitter. An extraction grid is formed on the dielectric layer. The extraction grid includes an opening surrounding and in close proximity to a tip of the emitter. An insulating region is formed at a lower boundary of the n-tank. The insulating region electrically isolates the emitter and the n-tank along at least a portion of the lower boundary beneath the opening. The insulating region thus functions to displace a depletion region associated with a boundary between the p-region and the n-tank from an area that can be illuminated by photons traveling through the extraction grid or openings in the extraction grid.Type: GrantFiled: July 30, 1998Date of Patent: August 20, 2002Assignee: Micron Technology, Inc.Inventors: John K. Lee, Behnam Moradi
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Patent number: 6417617Abstract: A field emission display apparatus includes a plurality of emitters formed on a substrate. Each of the emitters includes a titanium silicide nitride outer layer so that the emitters are less susceptible to degradation. A dielectric layer is formed on the substrate and the emitters, and an opening is formed in the dielectric layer surrounding each of the emitters. A conductive extraction grid is formed on the dielectric layer substantially in a plane defined by the emitters, and includes an opening surrounding each of the emitters. A cathodoluminescent faceplate having a planar surface is disposed parallel to the substrate.Type: GrantFiled: July 24, 2001Date of Patent: July 9, 2002Assignee: Micron Technology, Inc.Inventors: Tianhong Zhang, John K. Lee, Behnam Moradi
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Publication number: 20020076938Abstract: The invention encompasses a method of forming a dielectric material. A nitrogen-comprising layer is formed on at least some of the surface of a rugged polysilicon substrate to form a first portion of a dielectric material. After the nitrogen-comprising layer is formed, at least some of the substrate is subjected to dry oxidation with one or both of NO and N2O to form a second portion of the dielectric material. The invention also encompasses a method of forming a capacitor. A layer of rugged silicon is formed over a substrate, and a nitrogen-comprising layer is formed on the layer of rugged silicon. Some of the rugged silicon is exposed through the nitrogen-comprising layer. After the nitrogen-comprising layer is formed, at least some of the exposed rugged silicon is subjected to dry oxidation conditions with one or both of NO and N2O. Subsequently, a conductive material layer is formed over the nitrogen-comprising layer. Additionally, the invention encompasses a capacitor structure.Type: ApplicationFiled: November 29, 2001Publication date: June 20, 2002Inventors: Behnam Moradi, Er-Xuan Ping, Lingyi A. Zheng, John Packard
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Publication number: 20020066920Abstract: The invention encompasses a method of forming a dielectric material. A nitrogen-comprising layer is formed on at least some of the surface of a rugged polysilicon substrate to form a first portion of a dielectric material. After the nitrogen-comprising layer is formed, at least some of the substrate is subjected to dry oxidation with one or both of NO and N2O to form a second portion of the dielectric material. The invention also encompasses a method of forming a capacitor. A layer of rugged silicon is formed over a substrate, and a nitrogen-comprising layer is formed on the layer of rugged silicon. Some of the rugged silicon is exposed through the nitrogen-comprising layer. After the nitrogen-comprising layer is formed, at least some of the exposed rugged silicon is subjected to dry oxidation conditions with one or both of NO and N2O. Subsequently, a conductive material layer is formed over the nitrogen-comprising layer. Additionally, the invention encompasses a capacitor structure.Type: ApplicationFiled: November 29, 2001Publication date: June 6, 2002Inventors: Behnam Moradi, Er-Xuan Ping, Lingyi A. Zheng, John Packard
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Patent number: 6361392Abstract: A display apparatus includes a substrate and a plurality of emitters formed on the substrate. The apparatus also includes a dielectric layer formed on the substrate. The dielectric layer includes a plurality of openings each formed about one of the plurality of emitters. The dielectric layer and extraction grid together have a thickness, measured perpendicular to the substrate, similar to a height of the emitters above the substrate. The apparatus also includes an extraction grid formed on the dielectric layer. The extraction grid is formed substantially in a plane of tips of the plurality of emitters and includes openings each formed about and in close proximity to a tip of one of the plurality of emitters. The extraction grid includes germanium so that photons incident on exposed portions of the extraction grid are absorbed and are not transmitted to depletion regions associated with the emitters. This reduces distortion in operation of the display.Type: GrantFiled: May 18, 2001Date of Patent: March 26, 2002Assignee: Micron Technology, Inc.Inventors: Behnam Moradi, Tianhong Zhang
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Patent number: 6362038Abstract: CMOS devices and process for fabricating low voltage, high voltage, or both low voltage and high voltage CMOS devices are disclosed. According to the process, p-channel stops and source/drain regions of PMOS devices are implanted into a substrate in a single step. Further, gates for both NMOS and PMOS devices are doped with n-type dopant and NMOS gates are self-aligned.Type: GrantFiled: May 1, 2000Date of Patent: March 26, 2002Assignee: Micron Technology, Inc.Inventors: John K. Lee, Behnam Moradi, Michael J. Westphal
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Patent number: 6353285Abstract: An emitter substructure and methods for manufacturing the substructure are described. A substrate has a p-region formed at a surface of the substrate. A n-tank is formed such that the p-region surrounds a periphery of the n-tank. An emitter is formed on and electrically coupled to the n-tank. A dielectric layer is formed on the substrate that includes an opening surrounding the emitter. An extraction grid is formed on the dielectric layer. The extraction grid includes an opening surrounding and in close proximity to a tip of the emitter. An insulating region is formed at a lower boundary of the n-tank. The insulating region electrically isolates the emitter and the n-tank along at least a portion of the lower boundary beneath the opening. The insulating region thus functions to displace a depletion region associated with a boundary between the p-region and the n-tank from an area that can be illuminated by photons traveling through the extraction grid or openings in the extraction grid.Type: GrantFiled: July 24, 2000Date of Patent: March 5, 2002Assignee: Micron Technology, Inc.Inventors: John K. Lee, Behnam Moradi
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Publication number: 20020011778Abstract: A field emission display apparatus includes a plurality of emitters formed on a substrate. Each of the emitters includes a titanium silicide nitride outer layer so that the emitters are less susceptible to degradation. A dielectric layer is formed on the substrate and the emitters, and an opening is formed in the dielectric layer surrounding each of the emitters. A conductive extraction grid is formed on the dielectric layer substantially in a plane defined by the emitters, and includes an opening surrounding each of the emitters. A cathodoluminescent faceplate having a planar surface is disposed parallel to the substrate.Type: ApplicationFiled: July 25, 2001Publication date: January 31, 2002Inventors: Tianhong Zhang, John K. Lee, Behnam Moradi
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Publication number: 20010045794Abstract: A cap layer is placed on a substrate of inexpensive glass prior to subsequent processing to form emitter tips. The cap layer substantially reduces shrinkage of the substrate, significantly improves uniform formation of silicon tips, and substantially eliminates delamination of silicon layers from the substrate.Type: ApplicationFiled: July 20, 2001Publication date: November 29, 2001Inventors: James J. Alwan, Behnam Moradi, Kevin Tjaden
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Patent number: 6323587Abstract: A field emission display apparatus includes a plurality of emitters formed on a substrate. Each of the emitters includes a titanium silicide nitride outer layer so that the emitters are less susceptible to degradation. A dielectric layer is formed on the substrate and the emitters, and an opening is formed in the dielectric layer surrounding each of the emitters. A conductive extraction grid is formed on the dielectric layer substantially in a plane defined by the emitters, and includes an opening surrounding each of the emitters. A cathodoluminescent faceplate having a planar surface is disposed parallel to the substrate.Type: GrantFiled: August 6, 1998Date of Patent: November 27, 2001Assignee: Micron Technology, Inc.Inventors: Tianhong Zhang, John K. Lee, Behnam Moradi
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Publication number: 20010040429Abstract: A field emission display apparatus includes a plurality of emitters formed on a substrate. Each of the emitters includes a titanium silicide nitride outer layer so that the emitters are less susceptible to degradation. A dielectric layer is formed on the substrate and the emitters, and an opening is formed in the dielectric layer surrounding each of the emitters. A conductive extraction grid is formed on the dielectric layer substantially in a plane defined by the emitters, and includes an opening surrounding each of the emitters. A cathodoluminescent faceplate having a planar surface is disposed parallel to the substrate.Type: ApplicationFiled: July 24, 2001Publication date: November 15, 2001Inventors: Tianhong Zhang, John K. Lee, Behnam Moradi