Patents by Inventor Belgacem Haba

Belgacem Haba has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190293838
    Abstract: Direct-bonded lamination for improved image clarity in optical devices is provided. An example process planarizes and plasma-activates optical surfaces to be laminated together, then forms direct bonds between the two surfaces without an adhesive or adhesive layer. This process provides improved optics with higher image brightness, less light scattering, better resolution, and higher image fidelity. The direct bonds also provide a refractory interface tolerant of much higher temperatures than conventional optical adhesives. The example process can be used to produce many types of improved optical components, such as improved laminated lenses, mirrors, beam splitters, collimators, prism systems, optical conduits, and mirrored waveguides for smartglasses and head-up displays (HUDs), which provide better image quality and elimination of the dark visual lines that are apparent to a human viewer when conventional adhesives are used in conventional lamination.
    Type: Application
    Filed: October 31, 2018
    Publication date: September 26, 2019
    Inventors: Belgacem HABA, Rajesh KATKAR, Ilyas MOHAMMED
  • Publication number: 20190280428
    Abstract: Configurable smart object systems with magnetic contacts and magnetic assembly are provided. Example systems implement machine learning based on neural networks that draw low power for use in smart phones, watches, drones, automobiles, and medical devices, for example. Example assemblies can be configured from pluggable, interchangeable modules that have compatible ports with magnetic electrical contacts for interconnecting and integrating functionally dissimilar sensor systems. The magnetic electrical contacts physically couple the interfaces together or to a motherboard socket while providing an electrical coupling across the coupled magnetic contacts. The magnetic electrical contacts may arrayed in a reversible configuration so that a module or plug connection is reversible. A controller may dynamically assign power, ground, and data channels to the magnetic electrical contacts on the fly as the system is configured or reconfigured.
    Type: Application
    Filed: March 7, 2019
    Publication date: September 12, 2019
    Applicant: Xcelsis Corporation
    Inventors: Belgacem HABA, Ilyas MOHAMMED, Gabriel Z. GUEVARA, Min TAO
  • Publication number: 20190280421
    Abstract: Configurable smart object systems with grid or frame-based connectors are provided. Example systems implement machine learning based on neural networks that draw low power for use in smart phones, watches, drones, automobiles, and medical devices, for example. Example assemblies can be configured from pluggable, interchangeable modules that have compatible ports with magnetic electrical contacts for interconnecting and integrating functionally dissimilar sensor systems. An example system has a grid of frames attachable to a motherboard, panel, appliance, or machine, capable of securing and connecting multiple modules of the smart object system to the motherboard, panel, appliance, or machine. Each frame has at least a magnet or at least a clip for physically securing the single module within each frame. Each frame also has at least an electrical contact for electrically connecting each single module to the motherboard, panel, appliance, or machine through each respective frame.
    Type: Application
    Filed: March 7, 2019
    Publication date: September 12, 2019
    Applicant: Xcelsis Corporation
    Inventors: Belgacem HABA, Ilyas MOHAMMED, Gabriel Z. GUEVARA, Min TAO
  • Publication number: 20190280408
    Abstract: Configurable smart object systems with grid or frame-based connectors are provided. Example systems implement machine learning based on neural networks that draw low power for use in smart phones, watches, drones, automobiles, and medical devices, for example. Example assemblies can be configured from pluggable, interchangeable modules that have compatible ports with magnetic electrical contacts for interconnecting and integrating functionally dissimilar sensor systems. An example system has a clip attachable to a substrate for securing a smart object module to the substrate, and a housing of the clip with a geometry for aligning electrical contacts of the smart object module with electrical contacts of the substrate. The clip may have a compliant layer to provide spring, resilience, or pressure to securing the smart object module to the substrate. The clip may also integrate features of a secure digital (SD) port and a universal serial bus (USB) port.
    Type: Application
    Filed: March 7, 2019
    Publication date: September 12, 2019
    Applicant: Xcelsis Corporation
    Inventors: Belgacem HABA, Ilyas MOHAMMED, Gabriel Z. GUEVARA, Min TAO
  • Publication number: 20190272802
    Abstract: A virtual reality/augmented reality (VR/AR) headset system (including the capability for one or both of virtual reality and augmented reality) includes a remote optical engine. The remote disposition of the optical engine removes many or all of the components of the VR/AR headset system that add weight, heat, and other characteristics that can add to user discomfort in using the system from the headset. An electronic image is received and/or generated remotely at the optical engine, and is transmitted optically from the remote location to the headset to be viewed by the user. One or more optical waveguides may be used to transmit the electronic image to one or more passive displays of the headset, from the remote optical engine.
    Type: Application
    Filed: March 5, 2019
    Publication date: September 5, 2019
    Applicant: Invensas Corporation
    Inventors: Belgacem Haba, Ilyas Mohammed, Rajesh Katkar
  • Publication number: 20190273016
    Abstract: Apparatus and method relating generally to electronics are disclosed. In one such an apparatus, a film assembly has an upper surface and a lower surface opposite the upper surface. A dielectric film of the film assembly has a structured profile along the upper surface or the lower surface for having alternating ridges and grooves in a corrugated section in an at rest state of the film assembly. Conductive traces of the film assembly conform to the upper surface or the lower surface in or on the dielectric film in the corrugated section.
    Type: Application
    Filed: September 20, 2018
    Publication date: September 5, 2019
    Applicant: Invensas Corporation
    Inventors: Belgacem Haba, Ilyas Mohammed, Gabriel Z. Guevara, Min Tao
  • Patent number: 10403599
    Abstract: Embedded organic interposers for high bandwidth are provided. Example embedded organic interposers provide thick conductors with more dielectric space, and more routing layers of such conductors than conventional interposers, in order to provide high bandwidth transmission capacity over longer spans. The embedded organic interposers provide high bandwidth transmission paths between components such as HBM, HBM2, and HBM3 memory stacks, and other components. To provide the thick conductors and more routing layers for greater transmission capacity, extra space is achieved by embedding the organic interposers in the core of the package. Example embedded organic interposers lower a resistive-capacitive (RC) load of the routing layers to provide improved signal transmission of 1-2 GHz up to 20-60 GHz bandwidth for each 15 mm length, for example. The embedded organic interposers are not limited to use with memory modules.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: September 3, 2019
    Assignee: Invensas Corporation
    Inventors: Javier A. Delacruz, Belgacem Haba
  • Publication number: 20190237437
    Abstract: A microelectronic assembly including an insulating layer having a plurality of nanoscale conductors disposed in a nanoscale pitch array therein and a pair of microelectronic elements is provided. The nanoscale conductors can form electrical interconnections between contacts of the microelectronic elements while the insulating layer can mechanically couple the microelectronic elements together.
    Type: Application
    Filed: April 9, 2019
    Publication date: August 1, 2019
    Applicant: Invensas Corporation
    Inventors: Liang Wang, Bongsub Lee, Belgacem Haba, Sangil Lee
  • Publication number: 20190221510
    Abstract: A microelectronic assembly including first and second laminated microelectronic elements is provided. A patterned bonding layer is disposed on a face of each of the first and second laminated microelectronic elements. The patterned bonding layers are mechanically and electrically bonded to form the microelectronic assembly.
    Type: Application
    Filed: March 21, 2019
    Publication date: July 18, 2019
    Applicant: Invensas Corporation
    Inventors: Javier A. Delacruz, Belgacem Haba, Wael Zohni, Liang Wang, Akash Agrawal
  • Patent number: 10354942
    Abstract: A method of fabricating a semiconductor assembly can include providing a semiconductor element having a front surface, a rear surface, and a plurality of conductive pads, forming at least one hole extending at least through a respective one of the conductive pads by processing applied to the respective conductive pad from above the front surface, forming an opening extending from the rear surface at least partially through a thickness of the semiconductor element, such that the at least one hole and the opening meet at a location between the front and rear surfaces, and forming at least one conductive element exposed at the rear surface for electrical connection to an external device, the at least one conductive element extending within the at least one hole and at least into the opening, the conductive element being electrically connected with the respective conductive pad.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: July 16, 2019
    Assignee: Tessera, Inc.
    Inventors: Vage Oganesian, Belgacem Haba, Ilyas Mohammed, Craig Mitchell, Piyush Savalia
  • Patent number: 10354976
    Abstract: Dies-on-package devices and methods therefor are disclosed. In a dies-on-package device, a first IC die is surface mount coupled to an upper surface of a package substrate. Conductive lines are coupled to the upper surface of the package substrate in a fan-out region with respect to the first IC die. A molding layer is formed over the upper surface of the package substrate, around sidewall surfaces of the first IC die, and around bases and shafts of the conductive lines. A plurality of second IC dies is located at a same level above an upper surface of the molding layer respectively surface mount coupled to sets of upper portions of the conductive lines. The plurality of second IC dies are respectively coupled to the sets of the conductive lines in middle third portions respectively of the plurality of second IC dies for corresponding fan-in regions thereof.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: July 16, 2019
    Assignee: Invensas Corporation
    Inventors: Min Tao, Hoki Kim, Ashok S. Prabhu, Zhuowen Sun, Wael Zohni, Belgacem Haba
  • Publication number: 20190214353
    Abstract: Vertical capacitors for microelectronics are provided. An example thin capacitor layer can provide one or numerous capacitors to a semiconductor chip or integrated circuit. In an implementation, a thin capacitor layer of 50-100 ?m thickness may have 5000 vertically disposed capacitor plates per linear centimeter, while occupying only a thin slice of the package. Electrodes for each capacitor plate are accessible at multiple surfaces. Electrode density for very fine pitch interconnects can be in the range of 2-200 ?m separation between electrodes. A redistribution layer (RDL) may be fabricated on one or both sides of the thin capacitor layer to provide fan-out ball grid arrays that occupy insignificant space. RDLs or through-vias can connect together sets of the interior vertical capacitor plates within a given thin capacitor layer to form various capacitors from the plates to meet the needs of particular chips, dies, integrated circuits, and packages.
    Type: Application
    Filed: December 12, 2018
    Publication date: July 11, 2019
    Applicant: Invensas Corporation
    Inventors: Belgacem Haba, Javier A. Delacruz
  • Patent number: 10347582
    Abstract: Embedded vialess bridges are provided. In an implementation, discrete pieces containing numerous conduction lines or wires in a 3-dimensional bridge piece are embedded where needed in a main substrate to provide dense arrays of signal, power, and electrical ground wires below the surface of the main substrate. Vertical conductive risers to reach the surface plane of the main substrate are also included in the discrete piece, for connecting to dies on the surface of the substrate and thereby interconnecting the dies to each other through the dense array of wires in the discrete piece. The discrete piece to be embedded may have parallel planes of conductors at regular intervals within itself, and thus may present a working surface homogeneously covered with the ends of vertical conductors available to connect surface components to each other and to ground and power at many places along the embedded piece.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: July 9, 2019
    Assignee: Invensas Corporation
    Inventor: Belgacem Haba
  • Publication number: 20190198407
    Abstract: An integrated device package is disclosed. The integrated device package can include an integrated device die, an element, a cavity, and an electrical interconnect. The element can have an antenna structure. The element can be attached to a surface of the integrated device. The cavity can be disposed between the integrated device die and the antenna structure. The electrical interconnect can connect the integrated device die and the antenna structure.
    Type: Application
    Filed: December 6, 2018
    Publication date: June 27, 2019
    Inventors: Shaowu Huang, Javier A. DeLaCruz, Liang Wang, Rajesh Katkar, Belgacem Haba
  • Patent number: 10319673
    Abstract: An interconnection component includes a first support portion, a second support portion, a redistribution layer and a passive device, wherein at least one of the first and second support portions is comprised of a semiconductor material. The first support portion includes first and second opposed major surfaces and a plurality of first conductive vias extending through the first support portion substantially perpendicular to major surfaces. The second support portion includes first and second opposed major surfaces and a plurality of second conductive vias extending through the second support portion substantially perpendicular to the first and second major surfaces of the second support. The redistribution layer can be disposed between the second surfaces of the first and second support portions. The passive device can be positioned at least partially within the redistribution layer and electrically connected with one or more of the first conductive vias and the second conductive vias.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: June 11, 2019
    Assignee: Invensas Corporation
    Inventors: Belgacem Haba, Kishor Desai
  • Patent number: 10304803
    Abstract: A microelectronic assembly including an insulating layer having a plurality of nanoscale conductors disposed in a nanoscale pitch array therein and a pair of microelectronic elements is provided. The nanoscale conductors can form electrical interconnections between contacts of the microelectronic elements while the insulating layer can mechanically couple the microelectronic elements together.
    Type: Grant
    Filed: May 5, 2016
    Date of Patent: May 28, 2019
    Assignee: Invensas Corporation
    Inventors: Liang Wang, Bongsub Lee, Belgacem Haba, Sangil Lee
  • Patent number: 10297570
    Abstract: An adhesive with self-connecting interconnects is provided. The adhesive layer provides automatic 3D joining of microelectronic components with a conductively self-adjusting anisotropic matrix. In an implementation, the adhesive matrix automatically makes electrical connections between two surfaces that have opposing electrical contacts, and bonds the two surfaces together. Conductive members in the adhesive matrix are aligned to automatically establish electrical connections between at least partially aligned contacts on each of the two surfaces while providing nonconductive adhesion between parts of the two surfaces lacking aligned contacts. An example method includes forming an adhesive matrix between two surfaces to be joined, including conductive members anisotropically aligned in an adhesive medium, then pressing the two surfaces together to automatically connect corresponding electrical contacts that are at least partially aligned on the two surfaces.
    Type: Grant
    Filed: January 3, 2018
    Date of Patent: May 21, 2019
    Assignee: Invensas Corporation
    Inventor: Belgacem Haba
  • Patent number: 10297582
    Abstract: A method for making an interposer includes forming a plurality of wire bonds bonded to one or more first surfaces of a first element. A dielectric encapsulation is formed contacting an edge surface of the wire bonds which separates adjacent wire bonds from one another. Further processing comprises removing at least portions of the first element, wherein the interposer has first and second opposite sides separated from one another by at least the encapsulation, and the interposer having first contacts and second contacts at the first and second opposite sides, respectively, for electrical connection with first and second components, respectively, the first contacts being electrically connected with the second contacts through the wire bonds.
    Type: Grant
    Filed: November 25, 2015
    Date of Patent: May 21, 2019
    Assignee: Invensas Corporation
    Inventors: Terrence Caskey, Ilyas Mohammed, Cyprian Emeka Uzoh, Charles G. Woychik, Michael Newman, Pezhman Monadgemi, Reynaldo Co, Ellis Chau, Belgacem Haba
  • Patent number: 10290612
    Abstract: A three-dimensional stacking technique performed in a wafer-to-wafer fashion reducing the machine movement in production. The Wafers are processed with metallic traces and stacked before dicing into separate die stacks. The traces of each layer of the stacks are interconnected via electroless plating.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: May 14, 2019
    Assignee: Invensas Corporation
    Inventors: Belgacem Haba, Ilyas Mohammed, Javier A. Delacruz
  • Patent number: 10290589
    Abstract: A foldable microelectronic assembly and a method for forming the same are provided. One or more packages comprising encapsulated microelectronic elements are formed, along with a compliant layer. The packages and the compliant layer are coupled to a redistribution layer. The compliant layer and the redistribution layer are bent such that the redistribution layer is non-planar.
    Type: Grant
    Filed: November 8, 2016
    Date of Patent: May 14, 2019
    Assignee: Invensas Corporation
    Inventors: Belgacem Haba, Ilyas Mohammed