Patents by Inventor Belgacem Haba

Belgacem Haba has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10813214
    Abstract: A method for making an interconnection component includes forming a mask layer that covers a first opening in a sheet-like element that includes a first opening extending between the first and second surfaces of the element. The element consists essentially of a material having a coefficient of thermal expansion of less than 10 parts per million per degree Celsius. The first opening includes a central opening and a plurality of peripheral openings open to the central opening that extends in an axial direction of the central opening. A conductive seed layer can cover an interior surface of the first opening. The method further includes forming a first mask opening in at least a portion of the mask layer overlying the first opening to expose portions of the conductive seed layer within the peripheral openings; and forming electrical conductors on exposed portions of the conductive seed layer.
    Type: Grant
    Filed: June 13, 2018
    Date of Patent: October 20, 2020
    Assignee: Invensas Corporation
    Inventors: Cyprian Emeka Uzoh, Craig Mitchell, Belgacem Haba, Ilyas Mohammed
  • Patent number: 10811388
    Abstract: Capacitive couplings in a direct-bonded interface for microelectronic devices are provided. In an implementation, a microelectronic device includes a first die and a second die direct-bonded together at a bonding interface, a conductive interconnect between the first die and the second die formed at the bonding interface by a metal-to-metal direct bond, and a capacitive interconnect between the first die and the second die formed at the bonding interface. A direct bonding process creates a direct bond between dielectric surfaces of two dies, a direct bond between respective conductive interconnects of the two dies, and a capacitive coupling between the two dies at the bonding interface. In an implementation, a capacitive coupling of each signal line at the bonding interface comprises a dielectric material forming a capacitor at the bonding interface for each signal line.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: October 20, 2020
    Assignee: Invensas Corporation
    Inventors: Belgacem Haba, Arkalgud R. Sitaram
  • Publication number: 20200328164
    Abstract: A bonded structure is disclosed. The bonded structure can include a semiconductor element comprising active circuitry. The bonded structure can include a protective element directly bonded to the semiconductor element without an adhesive along a bonding interface. The protective element can include an obstructive material disposed over at least a portion of the active circuitry. The obstructive material can be configured to obstruct external access to the active circuitry. The bonded structure can include a disruption structure configured to disrupt functionality of the at least a portion of the active circuitry upon debonding of the protective element from the semiconductor element.
    Type: Application
    Filed: April 9, 2020
    Publication date: October 15, 2020
    Inventors: Javier A. DeLaCruz, Belgacem Haba, Rajesh Katkar
  • Publication number: 20200328162
    Abstract: A bonded structure is disclosed. The bonded structure can include a semiconductor element comprising active circuitry and a first bonding layer. The bonded structure can include a protective element directly bonded to the semiconductor element without an adhesive along a bonding interface. The protective element can include an obstructive material disposed over the active circuitry and a second bonding layer on the obstructive material. The second bonding layer can be directly bonded to the first bonding layer without an adhesive. The obstructive material can be configured to obstruct external access to the active circuitry.
    Type: Application
    Filed: April 9, 2020
    Publication date: October 15, 2020
    Inventors: Belgacem Haba, Javier A. DeLaCruz, Rajesh Katkar, Arkalgud Sitaram
  • Patent number: 10802285
    Abstract: A virtual reality/augmented reality (VR/AR) headset system (including the capability for one or both of virtual reality and augmented reality) includes a remote optical engine. The remote disposition of the optical engine removes many or all of the components of the VR/AR headset system that add weight, heat, and other characteristics that can add to user discomfort in using the system from the headset. An electronic image is received and/or generated remotely at the optical engine, and is transmitted optically from the remote location to the headset to be viewed by the user. One or more optical waveguides may be used to transmit the electronic image to one or more passive displays of the headset, from the remote optical engine.
    Type: Grant
    Filed: March 5, 2019
    Date of Patent: October 13, 2020
    Assignee: Invensas Corporation
    Inventors: Belgacem Haba, Ilyas Mohammed, Rajesh Katkar
  • Publication number: 20200321275
    Abstract: Techniques are disclosed herein for creating over and under interconnects. Using techniques described herein, over and under interconnects are created on an IC. Instead of creating signaling interconnects and power/ground interconnects on a same side of a chip assembly, the signaling interconnects can be placed on an opposing side of the chip assembly as compared to the power interconnects.
    Type: Application
    Filed: April 1, 2020
    Publication date: October 8, 2020
    Inventors: Belgacem Haba, Stephen Morein, Ilyas Mohammed, Rajesh Katkar, Javier A. Delacruz
  • Patent number: 10790222
    Abstract: A microelectronic assembly including first and second laminated microelectronic elements is provided. A patterned bonding layer is disposed on a face of each of the first and second laminated microelectronic elements. The patterned bonding layers are mechanically and electrically bonded to form the microelectronic assembly.
    Type: Grant
    Filed: March 21, 2019
    Date of Patent: September 29, 2020
    Assignee: Invensas Corporation
    Inventors: Javier A. Delacruz, Belgacem Haba, Wael Zohni, Liang Wang, Akash Agrawal
  • Patent number: 10784191
    Abstract: A stacked and electrically interconnected structure is disclosed. The structure can comprise a first element and a second element directly bonded to the first element along a bonding interface without an intervening adhesive. A filter circuit can be integrally formed between the first and second elements along the bonding interface.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: September 22, 2020
    Assignee: Invensas Bonding Technologies, Inc.
    Inventors: Shaowu Huang, Belgacem Haba, Javier A. DeLaCruz
  • Patent number: 10784282
    Abstract: Aspects of the disclosure relate to forming a completed stack of layers. Forming the completed stack of layers may include forming a first stack of layers on a first substrate and forming a second stack of layers on a second substrate. The first stack of layers may be bonded to the second stack of layers. The first or second substrate may be removed. Prior to bonding the first stack of layers and the second stack of layer, one or more holes may be etched in the first stack of layers. After removing the second substrate, one or more holes may be etched in the second stack of layers, wherein each of the one or more holes in the second stack of layers extend into a corresponding hole in the one or more holes in the first stack of layers.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: September 22, 2020
    Assignee: Xcelsis Corporation
    Inventors: Rajesh Katkar, Xu Chang, Belgacem Haba
  • Publication number: 20200294908
    Abstract: In various embodiments, a passive electronic component is disclosed. The passive electronic component can have a first surface and a second surface opposite the first surface. The passive electronic component can include a nonconductive material and a capacitor embedded within the nonconductive material. The capacitor can have a first electrode, a second electrode, and a dielectric material disposed between the first and second electrodes. The first electrode can comprise a first conductive layer and a plurality of conductive fibers extending from and electrically connected to the first conductive layer. A first conductive via can extend through the passive electronic component from the first surface to the second surface, with the first conductive via electrically connected to the first electrode.
    Type: Application
    Filed: March 11, 2019
    Publication date: September 17, 2020
    Inventors: Belgacem Haba, Javier A. DeLaCruz
  • Publication number: 20200279821
    Abstract: A nanowire bonding interconnect for fine-pitch microelectronics is provided. Vertical nanowires created on conductive pads provide a debris-tolerant bonding layer for making direct metal bonds between opposing pads or vias. Nanowires may be grown from a nanoporous medium with a height between 200-1000 nanometers and a height-to-diameter aspect ratio that enables the nanowires to partially collapse against the opposing conductive pads, creating contact pressure for nanowires to direct-bond to opposing pads. Nanowires may have diameters less than 200 nanometers and spacing less than 1 ?m from each other to enable contact or direct-bonding between pads and vias with diameters under 5 ?m at very fine pitch. The nanowire bonding interconnects may be used with or without tinning, solders, or adhesives.
    Type: Application
    Filed: January 29, 2020
    Publication date: September 3, 2020
    Applicant: Invensas Corporation
    Inventors: Belgacem Haba, Ilyas Mohammed
  • Patent number: 10750614
    Abstract: Deformable electrical contacts with conformable target pads for microelectronic assemblies and other applications are provided. A plurality of deformable electrical contacts on a first substrate may be joined to a plurality of conformable pads on a second substrate during die level or wafer level assembly of microelectronics, for example. Each deformable contact deforms to a degree that is related to the amount of joining pressure between the first substrate and the second substrate. The deformation process also wipes each respective conformable pad with the deformable electrical contact to create a fresh metal-to-metal contact for good conduction. Each conformable pad collapses as pressured by a compressible material to assume the approximate deformed shape of the electrical contact, providing a large conduction surface area, while also compensating for horizontal misalignment.
    Type: Grant
    Filed: May 16, 2018
    Date of Patent: August 18, 2020
    Assignee: Invensas Corporation
    Inventors: Belgacem Haba, Gabriel Z. Guevara
  • Patent number: 10734759
    Abstract: Configurable smart object systems with magnetic contacts and magnetic assembly are provided. Example systems implement machine learning based on neural networks that draw low power for use in smart phones, watches, drones, automobiles, and medical devices, for example. Example assemblies can be configured from pluggable, interchangeable modules that have compatible ports with magnetic electrical contacts for interconnecting and integrating functionally dissimilar sensor systems. The magnetic electrical contacts physically couple the interfaces together or to a motherboard socket while providing an electrical coupling across the coupled magnetic contacts. The magnetic electrical contacts may arrayed in a reversible configuration so that a module or plug connection is reversible. A controller may dynamically assign power, ground, and data channels to the magnetic electrical contacts on the fly as the system is configured or reconfigured.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: August 4, 2020
    Assignee: Xcelsis Corporation
    Inventors: Belgacem Haba, Ilyas Mohammed, Gabriel Z. Guevara, Min Tao
  • Publication number: 20200227367
    Abstract: A bonded structure can include a first reconstituted element comprising a first element and having a first side comprising a first bonding surface and a second side opposite the first side. The first reconstituted element can comprise a first protective material disposed about a first sidewall surface of the first element. The bonded structure can comprise a second reconstituted element comprising a second element and having a first side comprising a second bonding surface and a second side opposite the first side. The first reconstituted element can comprise a second protective material disposed about a second sidewall surface of the second element. The second bonding surface of the first side of the second reconstituted element can be directly bonded to the first bonding surface of the first side of the first reconstituted element without an intervening adhesive along a bonding interface.
    Type: Application
    Filed: January 13, 2020
    Publication date: July 16, 2020
    Inventors: Belgacem Haba, Rajesh Katkar, Ilyas Mohammed, Javier A. DeLaCruz
  • Publication number: 20200219852
    Abstract: Representative implementations of devices and techniques provide correction for a defective die in a wafer-to-wafer stack or a die stack. A correction die is coupled to a die of the stack with the defective die. The correction die electrically replaces the defective die. Optionally, a dummy die can be coupled to other die stacks of a wafer-to-wafer stack to adjust a height of the stacks.
    Type: Application
    Filed: March 19, 2020
    Publication date: July 9, 2020
    Applicant: Invensas Corporatoin
    Inventor: Belgacem Haba
  • Publication number: 20200212013
    Abstract: A three-dimensional stacking technique performed in a wafer-to-wafer fashion reducing the machine movement in production. The wafers are processed with metallic traces and stacked before dicing into separate die stacks. The traces of each layer of the stacks are interconnected via electroless plating.
    Type: Application
    Filed: March 10, 2020
    Publication date: July 2, 2020
    Applicant: Invensas Corporation
    Inventors: Belgacem Haba, Ilyas Mohammed, Javier A. Delacruz
  • Publication number: 20200203316
    Abstract: Aspects of the disclosure relate to forming stacked NAND with multiple memory sections. Forming the stacked NAND with multiple memory sections may include forming a first memory section on a sacrificial substrate. A logic section may be formed on a substrate. The logic section may be bonded to the first memory section. The sacrificial substrate may be removed from the first memory section and a second memory section having a second sacrificial substrate may be formed and bonded to the first memory section.
    Type: Application
    Filed: July 26, 2019
    Publication date: June 25, 2020
    Applicant: Xcelsis Corporation
    Inventors: Stephen Morein, Javier A. Delacruz, Xu Chang, Belgacem Haba, Rajesh Katkar
  • Publication number: 20200203368
    Abstract: Aspects of the disclosure relate to forming a completed stack of layers. Forming the completed stack of layers may include forming a first stack of layers on a first substrate and forming a second stack of layers on a second substrate. The first stack of layers may be bonded to the second stack of layers. The first or second substrate may be removed. Prior to bonding the first stack of layers and the second stack of layer, one or more holes may be etched in the first stack of layers. After removing the second substrate, one or more holes may be etched in the second stack of layers, wherein each of the one or more holes in the second stack of layers extend into a corresponding hole in the one or more holes in the first stack of layers.
    Type: Application
    Filed: July 9, 2019
    Publication date: June 25, 2020
    Applicant: Xcelsis Corporation
    Inventors: Rajesh Katkar, Xu Chang, Belgacem Haba
  • Patent number: 10692842
    Abstract: A microelectronic assembly (300) or system (1500) includes at least one microelectronic package (100) having a microelectronic element (130) mounted face up above a first surface (108) of a substrate (102), one or more columns (138, 140) of contacts (132) extending in a first direction (142) along the microelectronic element front face. Columns (104A, 105B, 107A, 107B) of terminals (105 107) exposed at a second surface (110) of the substrate extend in the first direction. First terminals (105) exposed at surface (110) in a central region (112) thereof having width (152) not more than three and one-half times a minimum pitch (150) of the columns of terminals can be configured to carry address information usable to determine an addressable memory location. An axial plane of the microelectronic element can intersect the central region.
    Type: Grant
    Filed: October 1, 2018
    Date of Patent: June 23, 2020
    Assignee: Invensas Corporation
    Inventors: Richard Dewitt Crisp, Wael Zohni, Belgacem Haba, Frank Lambrecht
  • Publication number: 20200168579
    Abstract: Apparatuses relating to a microelectronic package are disclosed. In one such apparatus, a substrate has first contacts on an upper surface thereof. A microelectronic die has a lower surface facing the upper surface of the substrate and having second contacts on an upper surface of the microelectronic die. Wire bonds have bases joined to the first contacts and have edge surfaces between the bases and corresponding end surfaces. A first portion of the wire bonds are interconnected between a first portion of the first contacts and the second contacts. The end surfaces of a second portion of the wire bonds are above the upper surface of the microelectronic die. A dielectric layer is above the upper surface of the substrate and between the wire bonds. The second portion of the wire bonds have uppermost portions thereof bent over to be parallel with an upper surface of the dielectric layer.
    Type: Application
    Filed: January 31, 2020
    Publication date: May 28, 2020
    Applicant: Tessera, Inc.
    Inventors: Hiroaki SATO, Teck-Gyu KANG, Belgacem HABA, Philip R. OSBORN, Wei-Shun WANG, Ellis CHAU, Ilyas MOHAMMED, Norihito MASUDA, Kazuo SAKUMA, Kiyoaki HASHIMOTO, Kurosawa INETARO, Tomoyuki KIKUCHI