Patents by Inventor Belgacem Haba

Belgacem Haba has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220020729
    Abstract: Dies and/or wafers are stacked and bonded in various arrangements including stacks, and may be covered with a molding to facilitate handling, packaging, and the like. In various examples, the molding may cover more or less of a stack, to facilitate connectivity with the devices of the stack, to enhance thermal management, and so forth.
    Type: Application
    Filed: September 24, 2021
    Publication date: January 20, 2022
    Inventors: Guilian GAO, Cyprian Emeka UZOH, Jeremy Alfred THEIL, Belgacem HABA, Rajesh KATKAR
  • Publication number: 20220005827
    Abstract: Techniques for manufacturing memory devices, such as 3-dimensional NAND (3D-NAND) memory devices, may include splitting gate planes (e.g., the planes that include the word lines) into strips, thereby splitting the memory cells and increasing a density of memory cells for a respective memory device. The techniques described herein are applicable to various types of 3D-NAND or other memory devices.
    Type: Application
    Filed: June 29, 2021
    Publication date: January 6, 2022
    Inventors: Xu Chang, Belgacem Haba, Rajesh Katkar, David Edward Fisch, Javier A. Delacruz
  • Publication number: 20210407941
    Abstract: In one embodiment, an integrated device package is disclosed. The integrated device package can comprise a carrier an a molding compound over a portion of an upper surface of the carrier. The integrated device package can comprise an integrated device die mounted to the carrier and at least partially embedded in the molding compound, the integrated device die comprising active circuitry. The integrated device package can comprise a stress compensation element mounted to the carrier and at least partially embedded in the molding compound, the stress compensation element spaced apart from the integrated device die, the stress compensation element comprising a dummy stress compensation element devoid of active circuitry. At least one of the stress compensation element and the integrated device die can be directly bonded to the carrier without an adhesive.
    Type: Application
    Filed: June 30, 2020
    Publication date: December 30, 2021
    Inventor: Belgacem Haba
  • Publication number: 20210351159
    Abstract: Techniques and mechanisms for coupling chiplets to microchips utilizing active bridges. The active bridges include circuits that provide various functions and capabilities that previously may have been located on the microchips and/or the chiplets. Furthermore, the active bridges may be coupled to the microchips and the chiplets via “native interconnects” utilizing direct bonding techniques. Utilizing the active bridges and the direct bonding techniques of the active bridges to the microchips and the chiplets, the pitch for the interconnects can be greatly reduced going from a pitch in the millimeters to a fine pitch that may be in a range of less than one micron to approximately five microns.
    Type: Application
    Filed: May 7, 2020
    Publication date: November 11, 2021
    Inventors: Javier A. Delacruz, Belgacem Haba, Rajesh Katkar
  • Patent number: 11171117
    Abstract: Representative techniques and devices including process steps may be employed to form a common interconnection of a multi-die or multi-wafer stack. Each device of the stack includes a conductive pad disposed at a predetermined relative position on a surface of the device. The devices are stacked to vertically align the conductive pads. A through-silicon via is formed that electrically couples the conductive pads of each device of the stack.
    Type: Grant
    Filed: June 12, 2019
    Date of Patent: November 9, 2021
    Assignee: Invensas Bonding Technologies, Inc.
    Inventors: Guilian Gao, Belgacem Haba
  • Patent number: 11158606
    Abstract: Dies and/or wafers are stacked and bonded in various arrangements including stacks, and may be covered with a molding to facilitate handling, packaging, and the like. In various examples, the molding may cover more or less of a stack, to facilitate connectivity with the devices of the stack, to enhance thermal management, and so forth.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: October 26, 2021
    Assignee: Invensas Bonding Technologies, Inc.
    Inventors: Guilian Gao, Cyprian Emeka Uzoh, Jeremy Alfred Theil, Belgacem Haba, Rajesh Katkar
  • Publication number: 20210327851
    Abstract: Embedded organic interposers for high bandwidth are provided. Example embedded organic interposers provide thick conductors with more dielectric space, and more routing layers of such conductors than conventional interposers, in order to provide high bandwidth transmission capacity over longer spans. The embedded organic interposers provide high bandwidth transmission paths between components such as HBM, HBM2, and HBM3 memory stacks, and other components. To provide the thick conductors and more routing layers for greater transmission capacity, extra space is achieved by embedding the organic interposers in the core of the package. Example embedded organic interposers lower a resistive-capacitive (RC) load of the routing layers to provide an improved data transfer rate of 1 gigabits per second over at least a 6 mm span, for example. The embedded interposers are not limited to use with memory modules.
    Type: Application
    Filed: June 29, 2021
    Publication date: October 21, 2021
    Inventors: Javier A. Delacruz, Belgacem Haba
  • Publication number: 20210265460
    Abstract: A component includes a substrate and electrically conductive layers formed in contact with the substrate. The substrate can consist essentially of a material having a coefficient of thermal expansion of less than 10 ppm/° C. The substrate can have a surface and an opening extending downwardly therefrom. The electrically conductive layers can include at least first and second pairs of electrically conductive plates and first and second electrodes. The first and second pairs of plates can be connectable with respective first and second electric potentials. The first and second pairs of plates can extend along an inner surface of the opening, each of the plates being separated from at least one adjacent plate by a dielectric layer. The first and second electrodes can be exposed at the surface of the substrate and can be coupled to the respective first and second pairs of plates.
    Type: Application
    Filed: May 10, 2021
    Publication date: August 26, 2021
    Applicant: Tessera, Inc.
    Inventors: Vage Oganesian, Belgacem Haba, Ilyas Mohammed, Piyush Savalia
  • Publication number: 20210249383
    Abstract: An integrated circuit and a method for designing an IC wherein the base or host chip is bonded to smaller chiplets via DBI technology. The bonding of chip to chiplet creates an uneven or multi-level surface of the overall chip requiring a releveling for future bonding. The uneven surface is built up with plating of bumps and subsequently releveled with various methods including planarization.
    Type: Application
    Filed: April 26, 2021
    Publication date: August 12, 2021
    Inventors: Javier A. Delacruz, Belgacem Haba, Cyprian Emeka Uzoh, Rajesh Katkar, Ilyas Mohammed
  • Publication number: 20210225811
    Abstract: A three-dimensional stacking technique performed in a wafer-to-wafer fashion reducing the machine movement in production. The wafers are processed with metallic traces and stacked before dicing into separate die stacks. The traces of each layer of the stacks are interconnected via electroless plating.
    Type: Application
    Filed: March 30, 2021
    Publication date: July 22, 2021
    Applicant: Invensas Corporation
    Inventors: Belgacem Haba, Ilyas Mohammed, Javier A. Delacruz
  • Patent number: 11063017
    Abstract: Embedded organic interposers for high bandwidth are provided. Example embedded organic interposers provide thick conductors with more dielectric space, and more routing layers of such conductors than conventional interposers, in order to provide high bandwidth transmission capacity over longer spans. The embedded organic interposers provide high bandwidth transmission paths between components such as HBM, HBM2, and HBM3 memory stacks, and other components. To provide the thick conductors and more routing layers for greater transmission capacity, extra space is achieved by embedding the organic interposers in the core of the package. Example embedded organic interposers lower a resistive-capacitive (RC) load of the routing layers to provide an improved data transfer rate of 1 gigabits per second over at least a 6 mm span, for example. The embedded interposers are not limited to use with memory modules.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: July 13, 2021
    Assignee: Invensas Corporation
    Inventors: Javier A. Delacruz, Belgacem Haba
  • Publication number: 20210193625
    Abstract: An element that is configured to bond to another element is disclosed. A first element that can include a first plurality of contact pads on a first surface. The first plurality of contact pads includes a first contact pad and a second contact pad that are spaced apart from one another. The first and second contact pads are electrically connected to one another for redundancy. The first element can be prepared for direct bonding. The first element can be bonded to a second element to form a bonded structure. The second element has a second plurality of contact pads on a second surface. At least one of the second plurality of contact pads is bonded and electrically connected to at least one of the first plurality of contact pads.
    Type: Application
    Filed: December 21, 2020
    Publication date: June 24, 2021
    Inventors: Rajesh Katkar, Belgacem Haba
  • Publication number: 20210193624
    Abstract: A memory structure is provided, including a NAND block comprising a plurality of oxide layers, the plurality of layers forming a staircase structure at a first edge of the NAND block, a plurality of vias disposed on the staircase structure of NAND block, two or more of plurality of vias terminating along a same plane, a plurality of first bonding interconnects disposed on the plurality of vias, a plurality of bitlines extending across the NAND block, and a plurality of second bonding interconnects disposed along the bitlines. The memory structure may be stacked on another of the memory structure to form a stacked memory device.
    Type: Application
    Filed: December 15, 2020
    Publication date: June 24, 2021
    Inventors: Javier A. Delacruz, Belgacem Haba, Rajesh Katkar, Pearl Po-Yee Cheng
  • Publication number: 20210193603
    Abstract: A bonded structure is disclosed. The bonded structure can include a first element that has a first plurality of contact pads. The first plurality of contact pads includes a first contact pad and a second redundant contact pad. The bonded structure can also include a second element directly bonded to the first element without an intervening adhesive. The second element has a second plurality of contact pads. The second plurality of contact pads includes a third contact pad and a fourth redundant contact pad. The first contact pad is configured to connect to the third contact pad. The second contact pad is configured to connect to the fourth contact pad. The bonded structure can include circuitry that has a first state in which an electrical signal is transferred to the first contact pad and a second state in which the electrical signal is transferred to the second contact pad.
    Type: Application
    Filed: December 17, 2020
    Publication date: June 24, 2021
    Inventors: Javier A. DeLACruz, Belgacem Haba, Jung Ko
  • Publication number: 20210181511
    Abstract: Apparatus and method relating generally to electronics are disclosed. In one such an apparatus, a film assembly has an upper surface and a lower surface opposite the upper surface. A dielectric film of the film assembly has a structured profile along the upper surface or the lower surface for having alternating ridges and grooves in a corrugated section in an at rest state of the film assembly. Conductive traces of the film assembly conform to the upper surface or the lower surface in or on the dielectric film in the corrugated section.
    Type: Application
    Filed: February 22, 2021
    Publication date: June 17, 2021
    Applicant: Invensas Corporation
    Inventors: Belgacem Haba, Ilyas Mohammed, Gabriel Z. Guevara, Min Tao
  • Publication number: 20210181510
    Abstract: A bonded optical device is disclosed. The bonded optical device can include a first optical element, a second optical element, and an optical pathway. The first optical element has a first array of optical emitters configured to emit light of a first color. The first optical element is bonded to at least one processor element, the at least one processor element including active circuitry configured to control operation of the first optical element. The second optical element has a second array of optical emitters configured to emit light of a second color different from the first color. The second optical element is bonded to the at least one processor element. The optical pathway is optically coupled with the first and second optical elements. The optical pathway is configured to transmit a superposition of light from the first and second optical emitters to an optical output to be viewed by users.
    Type: Application
    Filed: December 16, 2020
    Publication date: June 17, 2021
    Inventors: Rajesh Katkar, Belgacem Haba
  • Publication number: 20210175206
    Abstract: An integrated circuit and a method for designing an IC wherein the base or host chip is bonded to smaller chiplets via DBI technology. The bonding of chip to chiplet creates an uneven or multi-level surface of the overall chip requiring a releveling for future bonding. The uneven surface is built up with plating of bumps and subsequently releveled with various methods including planarization.
    Type: Application
    Filed: November 20, 2020
    Publication date: June 10, 2021
    Applicant: Xcelsis Corporation
    Inventors: Javier A. Delacruz, Belgacem Haba, Cyprian Emeka Uzoh, Rajesh Katkar, Ilyas Mohammed
  • Patent number: 11024220
    Abstract: Apparatus and method relating generally to an LED display is disclosed. In such an apparatus, a driver die has a plurality of driver circuits. A plurality of light-emitting diodes, each having a thickness of 10 microns or less and discrete with respect to one another, are respectively interconnected to the plurality of driver circuits. The plurality of light-emitting diodes includes a first portion for a first color, a second portion for a second color, and a third portion for a third color respectively obtained from a first, a second, and a third optical wafer. The first, the second, and the third color are different from one another.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: June 1, 2021
    Assignee: Invensas Corporation
    Inventors: Liang Wang, Rajesh Katkar, Javier A. Delacruz, Ilyas Mohammed, Belgacem Haba
  • Patent number: 11004930
    Abstract: A component includes a substrate and a capacitor formed in contact with the substrate. The substrate can consist essentially of a material having a coefficient of thermal expansion of less than 10 ppm/° C. The substrate can have a surface and an opening extending downwardly therefrom. The capacitor can include at least first and second pairs of electrically conductive plates and first and second electrodes. The first and second pairs of plates can be connectable with respective first and second electric potentials. The first and second pairs of plates can extend along an inner surface of the opening, each of the plates being separated from at least one adjacent plate by a dielectric layer. The first and second electrodes can be exposed at the surface of the substrate and can be coupled to the respective first and second pairs of plates.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: May 11, 2021
    Assignee: Tessera, Inc.
    Inventors: Vage Oganesian, Belgacem Haba, Ilyas Mohammed, Piyush Savalia
  • Publication number: 20210134689
    Abstract: An integrated device package is disclosed. The integrated device package can include an integrated device die, an element, a cavity, and an electrical interconnect. The element can have an antenna structure. The element can be attached to a surface of the integrated device. The cavity can be disposed between the integrated device die and the antenna structure. The electrical interconnect can connect the integrated device die and the antenna structure.
    Type: Application
    Filed: January 11, 2021
    Publication date: May 6, 2021
    Inventors: Shaowu Huang, Javier A. DeLaCruz, Liang Wang, Rajesh Katkar, Belgacem Haba