Patents by Inventor Belgacem Haba

Belgacem Haba has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12266640
    Abstract: Dies and/or wafers are stacked and bonded in various arrangements including stacks, and may be covered with a molding to facilitate handling, packaging, and the like. In various examples, the molding may cover more or less of a stack, to facilitate connectivity with the devices of the stack, to enhance thermal management, and so forth.
    Type: Grant
    Filed: November 17, 2023
    Date of Patent: April 1, 2025
    Assignee: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
    Inventors: Guilian Gao, Cyprian Emeka Uzoh, Jeremy Alfred Theil, Belgacem Haba, Rajesh Katkar
  • Patent number: 12266545
    Abstract: A multi-component device package comprising an integrated cooling assembly and methods for manufacturing said multi-component device package. A multi-component device package may comprise a plurality of semiconductor devices encapsulated in a mold material. A portion of the mold material may be removed to expose the backside of at least one semiconductor device of the plurality of semiconductor devices. A first dielectric layer may be formed on the exposed backside of the at least one semiconductor device. A cold plate comprising a base plate may be prepared and then the base plate may be directly bonded to the exposed backside of the at least one semiconductor device.
    Type: Grant
    Filed: September 20, 2024
    Date of Patent: April 1, 2025
    Assignee: Adeia Semiconductor Bonding Technologies Inc.
    Inventors: Laura Mirkarimi, Gaius Gillman Fountain, Jr., Belgacem Haba
  • Publication number: 20250105094
    Abstract: A device package comprising an integrated cooling assembly. The integrated cooling assembly comprising a semiconductor device and a manifold attached to the semiconductor device. The manifold comprises a top portion, a spacer extending downwardly from the top portion to a backside of the semiconductor device, and a vibrational membrane disposed between portions of the manifold. The top portion, the spacer, and the backside of the semiconductor device collectively define a coolant chamber volume therebetween.
    Type: Application
    Filed: September 27, 2023
    Publication date: March 27, 2025
    Inventors: Belgacem Haba, Rajesh Katkar
  • Patent number: 12261099
    Abstract: In some implementations, a device package may include a package substrate, a package cover disposed on the package substrate, and an integrated cooling assembly disposed between the package substrate and the package cover. The integrated cooling assembly may include a semiconductor device and a cold plate having a first side attached to the semiconductor device and a second side opposite the first side. An adhesive layer may be disposed between the package cover and the second side of the cold plate, and one or more surfaces of second side of the cold plate may be spaced apart from the package cover to define a coolant channel therebetween. The adhesive layer may seal the package cover to the cold plate around a perimeter of the coolant channel.
    Type: Grant
    Filed: December 22, 2023
    Date of Patent: March 25, 2025
    Assignee: Adeia Semiconductor Bonding Technologies Inc.
    Inventors: Guilian Gao, Belgacem Haba, Laura Mirkarimi
  • Publication number: 20250096168
    Abstract: A nanowire bonding interconnect for fine-pitch microelectronics is provided. Vertical nanowires created on conductive pads provide a debris-tolerant bonding layer for making direct metal bonds between opposing pads or vias. Nanowires may be grown from a nanoporous medium with a height between 200-1000 nanometers and a height-to-diameter aspect ratio that enables the nanowires to partially collapse against the opposing conductive pads, creating contact pressure for nanowires to direct-bond to opposing pads. Nanowires may have diameters less than 200 nanometers and spacing less than 1 ?m from each other to enable contact or direct-bonding between pads and vias with diameters under 5 ?m at very fine pitch. The nanowire bonding interconnects may be used with or without tinning, solders, or adhesives.
    Type: Application
    Filed: December 3, 2024
    Publication date: March 20, 2025
    Inventors: Belgacem Haba, Ilyas Mohammed
  • Patent number: 12237306
    Abstract: Representative implementations of devices and techniques provide correction for a defective die in a wafer-to-wafer stack or a die stack. A correction die is coupled to a die of the stack with the defective die. The correction die electrically replaces the defective die. Optionally, a dummy die can be coupled to other die stacks of a wafer-to-wafer stack to adjust a height of the stacks.
    Type: Grant
    Filed: February 9, 2023
    Date of Patent: February 25, 2025
    Assignee: Adeia Semiconductor Technologies LLC
    Inventor: Belgacem Haba
  • Publication number: 20250054854
    Abstract: A device including a first integrated device die and a semiconductor device. The first integrated device die can include a die insulating layer and a die conductive feature at least partially embedded in the die insulating layer. The semiconductor device can include a first insulating layer on the first surface, a device conductive feature at least partially embedded in the first insulating layer, and a first heavily doped semiconductor material electrically connected to the device conductive feature. The die conductive feature can be connected to power or ground through at least the first heavily doped semiconductor material.
    Type: Application
    Filed: June 17, 2024
    Publication date: February 13, 2025
    Inventors: Rajesh Katkar, Cyprian Emeka Uzoh, Belgacem Haba
  • Publication number: 20250054837
    Abstract: A cooling structure having a first side and a second side opposite the first side can be formed through a method comprising, forming an inlet and an outlet in a first substrate, forming at least one channel on the second side of the first substrate, wherein the at least one channel is in fluid communication with the inlet and outlet, forming a plurality of nozzles on the first side of a second substrate, and forming a plurality of channels on the second side of the second substrate opposite the first side of the second substrate. The plurality of channels is aligned with the plurality of nozzles, and the second side of the first substrate is bonded to the first side of the second substrate.
    Type: Application
    Filed: October 23, 2024
    Publication date: February 13, 2025
    Inventors: Thomas Workman, Ron Zhang, Kyong-Mo Bang, Belgacem Haba, Gaius Gillman Fountain, JR.
  • Publication number: 20250046625
    Abstract: Various embodiments of fanout packages are disclosed. A method of forming a microelectronic assembly is disclosed. The method can include bonding a first surface of at least one microelectronic substrate to a surface of a carrier using a direct bonding technique without an intervening adhesive, the microelectronic substrate having a plurality of conductive interconnections on at least one surface of the microelectronic substrate. The method can include applying a molding material to an area of the surface of the carrier surrounding the microelectronic substrate to form a reconstituted substrate. The method can include processing the microelectronic substrate. The method can include singulating the reconstituted substrate at the area of the surface of the carrier and at the molding material to form the microelectronic assembly.
    Type: Application
    Filed: June 4, 2024
    Publication date: February 6, 2025
    Inventor: Belgacem Haba
  • Publication number: 20250044598
    Abstract: A bonded optical device is disclosed. The bonded optical device can include a first optical element, a second optical element, and an optical pathway. The first optical element has a first array of optical emitters configured to emit light of a first color. The first optical element is bonded to at least one processor element, the at least one processor element including active circuitry configured to control operation of the first optical element. The second optical element has a second array of optical emitters configured to emit light of a second color different from the first color. The second optical element is bonded to the at least one processor element. The optical pathway is optically coupled with the first and second optical elements. The optical pathway is configured to transmit a superposition of light from the first and second optical emitters to an optical output to be viewed by users.
    Type: Application
    Filed: August 29, 2024
    Publication date: February 6, 2025
    Inventors: Rajesh Katkar, Belgacem Haba
  • Publication number: 20250048633
    Abstract: Aspects of the disclosure relate to forming a completed stack of layers. Forming the completed stack of layers may include forming a first stack of layers on a first substrate and forming a second stack of layers on a second substrate. The first stack of layers may be bonded to the second stack of layers. The first or second substrate may be removed. Prior to bonding the first stack of layers and the second stack of layer, one or more holes may be etched in the first stack of layers. After removing the second substrate, one or more holes may be etched in the second stack of layers, wherein each of the one or more holes in the second stack of layers extend into a corresponding hole in the one or more holes in the first stack of layers.
    Type: Application
    Filed: June 10, 2024
    Publication date: February 6, 2025
    Inventors: Rajesh Katkar, Xu Chang, Belgacem Haba
  • Patent number: 12218107
    Abstract: An element that is configured to bond to another element is disclosed. A first element that can include a first plurality of contact pads on a first surface. The first plurality of contact pads includes a first contact pad and a second contact pad that are spaced apart from one another. The first and second contact pads are electrically connected to one another for redundancy. The first element can be prepared for direct bonding. The first element can be bonded to a second element to form a bonded structure. The second element has a second plurality of contact pads on a second surface. At least one of the second plurality of contact pads is bonded and electrically connected to at least one of the first plurality of contact pads.
    Type: Grant
    Filed: December 11, 2023
    Date of Patent: February 4, 2025
    Assignee: Adeia Semiconductor Bonding Technologies Inc.
    Inventors: Rajesh Katkar, Belgacem Haba
  • Publication number: 20250038104
    Abstract: A component comprises a substrate comprising a first side and a second side opposite to the first side. A first dielectric layer is formed on the first side, and a plurality of electrically conductive pads extend through the first dielectric layer. A second dielectric layer is formed on the second side, and a plurality of electrically conductive pads extend through the second dielectric layer. A plurality of capacitors are each formed in an opening that extends at least partially from the first side towards the second side of the substrate. Each of the capacitors comprises at least three electrodes. At least one of the plurality of capacitors is coupled on the first side to an electrically conductive pad of the first dielectric layer and is coupled on the second side to an electrically conductive pad of the second dielectric layer.
    Type: Application
    Filed: June 28, 2024
    Publication date: January 30, 2025
    Inventors: Rajesh Katkar, Belgacem Haba
  • Patent number: 12205926
    Abstract: Representative techniques and devices including process steps may be employed to mitigate the potential for delamination of bonded microelectronic substrates due to metal expansion at a bonding interface. For example, a through-silicon via (TSV) may be disposed through at least one of the microelectronic substrates. The TSV is exposed at the bonding interface of the substrate and functions as a contact surface for direct bonding.
    Type: Grant
    Filed: August 17, 2023
    Date of Patent: January 21, 2025
    Assignee: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
    Inventors: Guilian Gao, Bongsub Lee, Gaius Gillman Fountain, Jr., Cyprian Emeka Uzoh, Belgacem Haba, Laura Wills Mirkarimi, Rajesh Katkar
  • Patent number: 12199011
    Abstract: A device package may include a package substrate, a package cover disposed on the package substrate, and an integrated cooling assembly disposed between the package substrate and the package cover. The package cover generally has an inlet opening and an outlet opening disposed there through. The integrated cooling assembly includes a semiconductor device and a cold plate attached to the semiconductor device. The device package may include a material layer between the package cover and the cold plate. The cold plate may include a patterned first side and an opposite second side. The patterned first side may include a base surface and sidewalls extending downward from the base surface, where the base surface is spaced apart from the semiconductor device to collectively define a coolant channel. Here, the coolant channel is in fluid communication with the inlet opening and the outlet opening through openings disposed through respective portions of the material layer.
    Type: Grant
    Filed: December 28, 2023
    Date of Patent: January 14, 2025
    Assignee: Adeia Semiconductor Bonding Technologies Inc.
    Inventors: Belgacem Haba, Gaius Gillman Fountain, Jr.
  • Patent number: 12191267
    Abstract: A nanowire bonding interconnect for fine-pitch microelectronics is provided. Vertical nanowires created on conductive pads provide a debris-tolerant bonding layer for making direct metal bonds between opposing pads or vias. Nanowires may be grown from a nanoporous medium with a height between 200-1000 nanometers and a height-to-diameter aspect ratio that enables the nanowires to partially collapse against the opposing conductive pads, creating contact pressure for nanowires to direct-bond to opposing pads. Nanowires may have diameters less than 200 nanometers and spacing less than 1 ?m from each other to enable contact or direct-bonding between pads and vias with diameters under 5 ?m at very fine pitch. The nanowire bonding interconnects may be used with or without tinning, solders, or adhesives.
    Type: Grant
    Filed: July 11, 2022
    Date of Patent: January 7, 2025
    Assignee: Adeia Semiconductor Technologies, LLC
    Inventors: Belgacem Haba, Ilyas Mohammed
  • Patent number: 12191233
    Abstract: Embodiments herein provide for fluidic cooling assemblies embedded within a device package and related manufacturing methods. In one embodiment, the cooling assembly includes a cold plate body attached to a singulated device and a manifold lid attached to the cold plate body. The cold plate body has a first side adjacent to the singulated device and an opposite second side, and the manifold lid is attached to the second side. In some embodiments, the first side of the cold plate body and the backside of the singulated device each comprise a dielectric material surface, the cold plate body is attached to the singulated device by direct dielectric bonds formed between the dielectric material surfaces, the cold plate body, and the manifold lid define one or more cavities, and the one or more cavities form at least a portion of a fluid flow path from an inlet to an outlet of the manifold lid.
    Type: Grant
    Filed: July 28, 2022
    Date of Patent: January 7, 2025
    Assignee: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
    Inventors: Belgacem Haba, Thomas Workman, Cyprian Emeka Uzoh, Guilian Gao, Rajesh Katkar
  • Patent number: 12191235
    Abstract: The present disclosure provides for integrated cooling systems including an integrated cooling assembly. The integrated cooling assembly includes a semiconductor device having an active side and a backside opposite the active side. The integrated cooling assembly includes a plurality of stacked and bonded layers that collectively form a cold plate, the cold plate comprising (i) a first side and a second side opposite the first side, the first side having a base surface, a support feature that extends downwardly from the base surface, and sidewalls that extend downwardly from the base surface and surround base surface and the support feature, and (ii) a first interconnect vertically disposed through the support feature, where the first interconnect is electrically coupled to the semiconductor device through direct hybrid bonds formed between the cold plate and the semiconductor device.
    Type: Grant
    Filed: November 17, 2023
    Date of Patent: January 7, 2025
    Assignee: Adeia Semiconductor Bonding Technologies Inc.
    Inventors: Belgacem Haba, Rajesh Katkar
  • Patent number: 12191234
    Abstract: A device package comprising an integrated cooling assembly. The integrated cooling assembly comprises a semiconductor device and a cold plate attached to the semiconductor device. The cold plate comprises a top portion and a bottom portion horizontally adjacent to the top portion. The top portion comprises upper cavity dividers extending downwardly to define upper cavity volumes. The bottom portion comprises lower cavity dividers extending upwardly to define lower cavity volumes. The upper cavity dividers and the lower cavity dividers alternate across a horizontal length of the cold plate.
    Type: Grant
    Filed: August 17, 2023
    Date of Patent: January 7, 2025
    Assignee: Adeia Semiconductor Bonding Technologies Inc.
    Inventors: Gaius Gillman Fountain, Jr., Belgacem Haba, Kyong-Mo Bang
  • Patent number: RE50272
    Abstract: A virtual reality/augmented reality (VR/AR) headset system (including the capability for one or both of virtual reality and augmented reality) includes a remote optical engine. The remote disposition of the optical engine removes many or all of the components of the VR/AR headset system that add weight, heat, and other characteristics that can add to user discomfort in using the system from the headset. An electronic image is received and/or generated remotely at the optical engine, and is transmitted optically from the remote location to the headset to be viewed by the user. One or more optical waveguides may be used to transmit the electronic image to one or more passive displays of the headset, from the remote optical engine.
    Type: Grant
    Filed: July 23, 2021
    Date of Patent: January 14, 2025
    Assignee: Adeia Semiconductor Technologies LLC
    Inventors: Belgacem Haba, Ilyas Mohammed, Rajesh Katkar