Abstract: The present disclosure provides for integrated cooling systems including an integrated cooling assembly. The integrated cooling assembly includes a semiconductor device having an active side and a backside opposite the active side. The integrated cooling assembly includes a plurality of stacked and bonded layers that collectively form a cold plate, the cold plate comprising (i) a first side and a second side opposite the first side, the first side having a base surface, a support feature that extends downwardly from the base surface, and sidewalls that extend downwardly from the base surface and surround base surface and the support feature, and (ii) a first interconnect vertically disposed through the support feature, where the first interconnect is electrically coupled to the semiconductor device through direct hybrid bonds formed between the cold plate and the semiconductor device.

Abstract: A bonded structure can comprise a first element and a second element. The first element has a first dielectric layer including a first bonding surface and at least one first side surface of the first element. The second element has a second dielectric layer including a second bonding surface and at least one second side surface of the second element. The second bonding surface of the second element is directly bonded to the first bonding surface of the first element without an adhesive.

Abstract: The present disclosure provides for integrated cooling systems including an integrated cooling assembly. The integrated cooling assembly includes a semiconductor device having an active side and a backside opposite the active side. The integrated cooling assembly includes a plurality of stacked and bonded layers that collectively form a cold plate, the cold plate comprising (i) a first side and a second side opposite the first side, the first side having a base surface, a support feature that extends downwardly from the base surface, and sidewalls that extend downwardly from the base surface and surround base surface and the support feature, and (ii) a first interconnect vertically disposed through the support feature, where the first interconnect is electrically coupled to the semiconductor device through direct hybrid bonds formed between the cold plate and the semiconductor device.

Abstract: A device package comprising an integrated cooling assembly. The integrated cooling assembly comprises a semiconductor device and a cold plate attached to the semiconductor device. The cold plate comprises a top portion and a bottom portion horizontally adjacent to the top portion. The top portion comprises upper cavity dividers extending downwardly to define upper cavity volumes. The bottom portion comprises lower cavity dividers extending upwardly to define lower cavity volumes. The upper cavity dividers and the lower cavity dividers alternate across a horizontal length of the cold plate.

Abstract: Apparatus and method relating generally to electronics are disclosed. In one such an apparatus, a film assembly has an upper surface and a lower surface opposite the upper surface. A dielectric film of the film assembly has a structured profile along the upper surface or the lower surface for having alternating ridges and grooves in a corrugated section in an at rest state of the film assembly. Conductive traces of the film assembly conform to the upper surface or the lower surface in or on the dielectric film in the corrugated section.

Abstract: An optical apparatus is provided comprising: first and second optical waveguides disposed in a substrate such that light reflected by a beam splitting optical element of the first waveguide passes between beam splitting elements of the second waveguide.

Abstract: Techniques are disclosed herein for creating over and under interconnects. Using techniques described herein, over and under interconnects are created on an IC. Instead of creating signaling interconnects and power/ground interconnects on a same side of a chip assembly, the signaling interconnects can be placed on an opposing side of the chip assembly as compared to the power interconnects.

Abstract: Integrated circuits and method of making including a plurality of transistors, each of the transistors including a source, a drain, and a channel located between the source and the drain. The integrated circuit also includes a plurality of buried power rails including a plurality of VSS power rails and a plurality of VDD power rails, at least one VSS pad and at least one VDD pad, a plurality of vias electrically connecting the at least one VSS pad to at least two of the plurality of VSS power rails, and a plurality of vias electrically connecting the at least one VDD pad to at least two of the plurality of buried VDD power rails.

Abstract: In some embodiments, a structure comprises an active element having a frontside and a backside opposite the frontside, the active element having active circuitry nearer the frontside than the backside and a power redistribution element having a frontside hybrid bonded to the backside of the active element, the power redistribution element comprising a first plurality of contact pads on the frontside of the power redistribution element and a second plurality of contact pads on a backside of the power redistribution element opposite the frontside of the power redistribution element, a pitch of the first plurality of contact pads is smaller than a pitch of the second plurality of contact pads, the power redistribution element configured to supply at least one of power and ground to the active element.

Abstract: Embodiments herein provide for device packages comprising an integrated cooling assembly and methods of cooling packaged devices. The integrated cooling assembly comprising a semiconductor device, a manifold attached to the semiconductor device, and a sonic transducer attached to the manifold. The manifold comprises a top portion and a waveguide extending downwardly from the top portion. The sonic transducer is attached to the top portion. The top portion, the waveguide, and a backside of the semiconductor device collectively define a coolant chamber volume therebetween.

Abstract: Integrated circuits and method of making including a plurality of transistors, each of the transistors including a source, a drain, and a channel located between the source and the drain. The integrated circuit also includes a plurality of buried power rails including a plurality of VSS power rails and a plurality of VDD power rails, at least one VSS pad and at least one VDD pad, a plurality of vias electrically connecting the at least one VSS pad to at least two of the plurality of VSS power rails, and a plurality of vias electrically connecting the at least one VDD pad to at least two of the plurality of buried VDD power rails.

Abstract: The present disclosure provides for integrated cooling systems including backside power delivery and methods of manufacturing the same. An integrated cooling assembly may include a device and a cold plate. The cold plate has a first side and an opposite second side, the first side having a recessed surface, sidewalls around the recessed surface that extend downwardly therefrom to define a cavity, and a plurality of support features disposed in the cavity. The first side of the cold plate is attached to a backside of the device to define a coolant channel therebetween. The cold plate includes a substrate, a dielectric layer disposed on a first surface of the substrate, a first conductive layer disposed between the first surface and the dielectric layer, a second conductive layer disposed on a second surface of the substrate, and thru-substrate interconnects connecting the first conductive layer to the second conductive layer.

Abstract: An element includes a substrate and a surface layer on the substrate. The surface layer includes at least one first region comprising an optically transparent and electrically insulative first material and at least one second region at least partially embedded in the at least one first region. The at least one second region comprises an optically transparent and electrically conductive second material.

Abstract: It is highly desirable in electronic systems to conserve space on printed circuit boards (PCB). This disclosure describes voltage regulation in electronic systems, and more specifically to integrating voltage regulators and associated passive components into semiconductor packages with at least a portion of the circuits whose voltage(s) they are regulating.

Abstract: A bonded structure is disclosed. The bonded structure can include a carrier. The bonded structure can include a first memory unit disposed on the carrier having a first memory channel and a first plurality of memory dies directly hybrid bonded to one another. The bonded structure can also include a second memory unit having a second memory channel different from the first memory channel and a second plurality of memory dies directly hybrid bonded to one another. The second memory unit can be stacked on top of the first memory unit. The bonded structure can include a serializer-deserializer disposed in or on the carrier and electrically connected to the first and second memory channels of the first and second memory units. The serializer-deserializer can have an external channel configured to electrically connect the bonded structure to a processor.

Abstract: A bonded structure can comprise a first element and a second element. The first element has a first dielectric layer including a first bonding surface and at least one first side surface of the first element. The second element has a second dielectric layer including a second bonding surface and at least one second side surface of the second element. The second bonding surface of the second element is directly bonded to the first bonding surface of the first element without an adhesive.

Abstract: A cooling structure having a first side and a second side opposite the first side can be formed through a method comprising, forming an inlet and an outlet in a first substrate, forming at least one channel on the second side of the first substrate, wherein the at least one channel is in fluid communication with the inlet and outlet, forming a plurality of nozzles on the first side of a second substrate, and forming a plurality of channels on the second side of the second substrate opposite the first side of the second substrate. The plurality of channels is aligned with the plurality of nozzles, and the second side of the first substrate is bonded to the first side of the second substrate.

Abstract: In various embodiments, a bonded structure is disclosed. The bonded structure can include an element and a passive electronic component having a first surface bonded to the element and a second surface opposite the first surface. The passive electronic component can comprise a first anode terminal bonded to a corresponding second anode terminal of the element and a first cathode terminal bonded to a corresponding second cathode terminal of the element. The first anode terminal and the first cathode terminal can be disposed on the first surface of the passive electronic component.

Abstract: Techniques and mechanisms for coupling chiplets to microchips utilizing active bridges. The active bridges include circuits that provide various functions and capabilities that previously may have been located on the microchips and/or the chiplets. Furthermore, the active bridges may be coupled to the microchips and the chiplets via “native interconnects” utilizing direct bonding techniques. Utilizing the active bridges and the direct bonding techniques of the active bridges to the microchips and the chiplets, the pitch for the interconnects can be greatly reduced going from a pitch in the millimeters to a fine pitch that may be in a range of less than one micron to approximately five microns.

Abstract: The technology relates to a system on chip (SoC). The SoC may include a plurality of network layers which may assist electrical communications either horizontally or vertically among components from different device layers. In one embodiment, a system on chip (SoC) includes a plurality of network layers, each network layer including one or more routers, and more than one device layers, each of the plurality of network layers respectively bonded to one of the device layers. In another embodiment, a method for forming a system on chip (SoC) includes forming a plurality of network layers in an interconnect, wherein each network layer is bonded to an active surface of a respective device layer in a plurality of device layer.