Abstract: A bonded structure is disclosed. The bonded structure can include an interconnect structure. The bonded structure can also include a first die directly bonded to the interconnect structure. The bonded structure can also include a second die mounted to the interconnect structure. The second die is spaced apart from the first die laterally along an upper surface of the interconnect structure. The second die is electrically connected with the first die at least partially through the interconnect structure. The bonded structure can further include a dielectric layer that is disposed over the upper surface of the interconnect structure between the first die and the second die.

Abstract: The technology relates to a system on chip (SoC). The SoC may include a plurality of network layers which may assist electrical communications either horizontally or vertically among components from different device layers. In one embodiment, a system on chip (SoC) includes a plurality of network layers, each network layer including one or more routers, and more than one device layers, each of the plurality of network layers respectively bonded to one of the device layers. In another embodiment, a method for forming a system on chip (SoC) includes forming a plurality of network layers in an interconnect, wherein each network layer is bonded to an active surface of a respective device layer in a plurality of device layer.

Abstract: The technology relates to a system on chip (SoC). The SoC may include a network on layer including one or more routers and an application specific integrated circuit (ASIC) layer bonded to the network layer, the ASIC layer including one or more components. In some instances, the network layer and the ASIC layer each include an active surface and a second surface opposite the active surface. The active surface of the ASIC layer and the second surface of the network may each include one or more contacts, and the network layer may be bonded to the ASIC layer via bonds formed between the one or more contacts on the second surface of the network layer and the one or more contacts on the active surface of the ASIC layer.

Abstract: Techniques and arrangements for performing exposure operations on a wafer utilizing both a stepper apparatus and an aligner apparatus. The exposure operations are performed with respect to large composite base dies, e.g., interposers, defined within the wafer, where the interposers will become a part of microelectronic devices by coupling with active dies or microchips. The composite base dies may be coupled to the active dies via “native interconnects” utilizing direct bonding techniques. The stepper apparatus may be used to perform exposure operations on active regions of the composite base dies to provide a fine pitch for the native interconnects, while the aligner apparatus may be used to perform exposure operations on inactive regions of the composite base dies to provide a coarse pitch for interfaces with passive regions of the composite base dies.

Abstract: Direct-bonded lamination for improved image clarity in optical devices is provided. An example process planarizes and plasma-activates optical surfaces to be laminated together, then forms direct bonds between the two surfaces without an adhesive or adhesive layer. This process provides improved optics with higher image brightness, less light scattering, better resolution, and higher image fidelity. The direct bonds also provide a refractory interface tolerant of much higher temperatures than conventional optical adhesives. The example process can be used to produce many types of improved optical components, such as improved laminated lenses, mirrors, beam splitters, collimators, prism systems, optical conduits, and mirrored waveguides for smartglasses and head-up displays (HUDs), which provide better image quality and elimination of the dark visual lines that are apparent to a human viewer when conventional adhesives are used in conventional lamination.

Abstract: Configurable smart object systems with methods of making modules and contactors are provided. Example systems implement machine learning based on neural networks that draw low power for use in smart phones, watches, drones, automobiles, and medical devices. Example assemblies can be configured from pluggable, interchangeable modules that have compatible ports for interconnecting and integrating functionally dissimilar sensor systems. An example method includes mounting an element of a configurable machine learning assembly on a substrate, creating at least one fold in the substrate, folding the substrate at the fold into a housing of a module of the configurable machine learning assembly, and adding a molding material to the housing to at least partially fill the module of the configurable machine learning assembly. The example module construction may also form contactors on folded edges of the module for making physical and electrical contact with other modules of the smart object machine learning assembly.

Abstract: Configurable smart object systems with grid or frame-based connectors are provided. Example systems implement machine learning based on neural networks that draw low power for use in smart phones, watches, drones, automobiles, and medical devices, for example. Example assemblies can be configured from pluggable, interchangeable modules that have compatible ports with magnetic electrical contacts for interconnecting and integrating functionally dissimilar sensor systems. An example system has a clip attachable to a substrate for securing a smart object module to the substrate, and a housing of the clip with a geometry for aligning electrical contacts of the smart object module with electrical contacts of the substrate. The clip may have a compliant layer to provide spring, resilience, or pressure to securing the smart object module to the substrate. The clip may also integrate features of a secure digital (SD) port and a universal serial bus (USB) port.

Abstract: Representative techniques and devices including process steps may be employed to form a common interconnection of a multi-die or multi-wafer stack. Each device of the stack includes a conductive pad disposed at a predetermined relative position on a surface of the device. The devices are stacked to vertically align the conductive pads. A through-silicon via is formed that electrically couples the conductive pads of each device of the stack.

Abstract: Dies and/or wafers are stacked and bonded in various arrangements including stacks, and may be covered with a molding to facilitate handling, packaging, and the like. In various examples, the molding may cover more or less of a stack, to facilitate connectivity with the devices of the stack, to enhance thermal management, and so forth.

Abstract: Techniques for manufacturing memory devices, such as 3-dimensional NAND (3D-NAND) memory devices, may include splitting gate planes (e.g., the planes that include the word lines) into strips, thereby splitting the memory cells and increasing a density of memory cells for a respective memory device. The techniques described herein are applicable to various types of 3D-NAND or other memory devices.

Abstract: In one embodiment, an integrated device package is disclosed. The integrated device package can comprise a carrier an a molding compound over a portion of an upper surface of the carrier. The integrated device package can comprise an integrated device die mounted to the carrier and at least partially embedded in the molding compound, the integrated device die comprising active circuitry. The integrated device package can comprise a stress compensation element mounted to the carrier and at least partially embedded in the molding compound, the stress compensation element spaced apart from the integrated device die, the stress compensation element comprising a dummy stress compensation element devoid of active circuitry. At least one of the stress compensation element and the integrated device die can be directly bonded to the carrier without an adhesive.

Abstract: Techniques and mechanisms for coupling chiplets to microchips utilizing active bridges. The active bridges include circuits that provide various functions and capabilities that previously may have been located on the microchips and/or the chiplets. Furthermore, the active bridges may be coupled to the microchips and the chiplets via “native interconnects” utilizing direct bonding techniques. Utilizing the active bridges and the direct bonding techniques of the active bridges to the microchips and the chiplets, the pitch for the interconnects can be greatly reduced going from a pitch in the millimeters to a fine pitch that may be in a range of less than one micron to approximately five microns.

Abstract: Representative techniques and devices including process steps may be employed to form a common interconnection of a multi-die or multi-wafer stack. Each device of the stack includes a conductive pad disposed at a predetermined relative position on a surface of the device. The devices are stacked to vertically align the conductive pads. A through-silicon via is formed that electrically couples the conductive pads of each device of the stack.

Abstract: Dies and/or wafers are stacked and bonded in various arrangements including stacks, and may be covered with a molding to facilitate handling, packaging, and the like. In various examples, the molding may cover more or less of a stack, to facilitate connectivity with the devices of the stack, to enhance thermal management, and so forth.

Abstract: Embedded organic interposers for high bandwidth are provided. Example embedded organic interposers provide thick conductors with more dielectric space, and more routing layers of such conductors than conventional interposers, in order to provide high bandwidth transmission capacity over longer spans. The embedded organic interposers provide high bandwidth transmission paths between components such as HBM, HBM2, and HBM3 memory stacks, and other components. To provide the thick conductors and more routing layers for greater transmission capacity, extra space is achieved by embedding the organic interposers in the core of the package. Example embedded organic interposers lower a resistive-capacitive (RC) load of the routing layers to provide an improved data transfer rate of 1 gigabits per second over at least a 6 mm span, for example. The embedded interposers are not limited to use with memory modules.

Abstract: A component includes a substrate and electrically conductive layers formed in contact with the substrate. The substrate can consist essentially of a material having a coefficient of thermal expansion of less than 10 ppm/° C. The substrate can have a surface and an opening extending downwardly therefrom. The electrically conductive layers can include at least first and second pairs of electrically conductive plates and first and second electrodes. The first and second pairs of plates can be connectable with respective first and second electric potentials. The first and second pairs of plates can extend along an inner surface of the opening, each of the plates being separated from at least one adjacent plate by a dielectric layer. The first and second electrodes can be exposed at the surface of the substrate and can be coupled to the respective first and second pairs of plates.

Abstract: An integrated circuit and a method for designing an IC wherein the base or host chip is bonded to smaller chiplets via DBI technology. The bonding of chip to chiplet creates an uneven or multi-level surface of the overall chip requiring a releveling for future bonding. The uneven surface is built up with plating of bumps and subsequently releveled with various methods including planarization.

Abstract: A three-dimensional stacking technique performed in a wafer-to-wafer fashion reducing the machine movement in production. The wafers are processed with metallic traces and stacked before dicing into separate die stacks. The traces of each layer of the stacks are interconnected via electroless plating.

Abstract: Embedded organic interposers for high bandwidth are provided. Example embedded organic interposers provide thick conductors with more dielectric space, and more routing layers of such conductors than conventional interposers, in order to provide high bandwidth transmission capacity over longer spans. The embedded organic interposers provide high bandwidth transmission paths between components such as HBM, HBM2, and HBM3 memory stacks, and other components. To provide the thick conductors and more routing layers for greater transmission capacity, extra space is achieved by embedding the organic interposers in the core of the package. Example embedded organic interposers lower a resistive-capacitive (RC) load of the routing layers to provide an improved data transfer rate of 1 gigabits per second over at least a 6 mm span, for example. The embedded interposers are not limited to use with memory modules.

Abstract: An element that is configured to bond to another element is disclosed. A first element that can include a first plurality of contact pads on a first surface. The first plurality of contact pads includes a first contact pad and a second contact pad that are spaced apart from one another. The first and second contact pads are electrically connected to one another for redundancy. The first element can be prepared for direct bonding. The first element can be bonded to a second element to form a bonded structure. The second element has a second plurality of contact pads on a second surface. At least one of the second plurality of contact pads is bonded and electrically connected to at least one of the first plurality of contact pads.