Patents by Inventor Bendik Kleveland

Bendik Kleveland has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9361196
    Abstract: A memory device with a background built-in self-repair module (BBISRM) includes a main memory, an arbiter, and a redundant memory to repair a target memory under test (TMUT). The memory device also includes a background built-in self-test module (BBISTM) to identify portions of memory needing background built-in self-repair (BBISR). The BBISRM or the BBISTM can operate simultaneously while the memory device is operational for performing external accesses during field operation. The BBISR can detect and correct a single data bit error in the data stored in the TMUT. The arbiter configured to receive a read or write access memory request including a memory address, to determine if the memory address of the read or write access memory request matches the memory address mapped to the selected portion of the redundant memory, and to read or write data from the selected portion of the redundant memory, respectively.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: June 7, 2016
    Assignee: MoSys, Inc.
    Inventors: Bendik Kleveland, Dipak K Sikdar, Rajesh Chopra, Jay Patel
  • Patent number: 9037928
    Abstract: A memory device with background built-in self-testing (BBIST) includes a plurality of memory blocks; a memory buffer to offload data from one of the plurality of memory blocks temporarily; and a memory block stress controller to control a stress test applied to the one of the memory blocks when the data is temporarily offloaded on the memory buffer. The stress test tests for errors in the one of the plurality of the memory blocks.
    Type: Grant
    Filed: January 2, 2013
    Date of Patent: May 19, 2015
    Assignee: MoSys, Inc.
    Inventors: Bendik Kleveland, Dipak K Sikdar, Rajesh Chopra, Jay Patel
  • Publication number: 20140317460
    Abstract: A memory device with a background built-in self-repair module (BBISRM) includes a main memory, an arbiter, and a redundant memory to repair a target memory under test (TMUT). The memory device also includes a background built-in self-test module (BBISTM) to identify portions of memory needing background built-in self-repair (BBISR). The BBISRM or the BBISTM can operate simultaneously while the memory device is operational for performing external accesses during field operation. The BBISR can detect and correct a single data bit error in the data stored in the TMUT. The arbiter configured to receive a read or write access memory request including a memory address, to determine if the memory address of the read or write access memory request matches the memory address mapped to the selected portion of the redundant memory, and to read or write data from the selected portion of the redundant memory, respectively.
    Type: Application
    Filed: June 30, 2014
    Publication date: October 23, 2014
    Applicant: MOSYS, INC.
    Inventors: Bendik Kleveland, Dipak K. Sikdar, Rajesh Chopra, Jay Patel
  • Publication number: 20130173970
    Abstract: A memory device with background built-in self-testing (BBIST) includes a plurality of memory blocks; a memory buffer to offload data from one of the plurality of memory blocks temporarily; and a memory block stress controller to control a stress test applied to the one of the memory blocks when the data is temporarily offloaded on the memory buffer. The stress test tests for errors in the one of the plurality of the memory blocks.
    Type: Application
    Filed: January 2, 2013
    Publication date: July 4, 2013
    Applicant: MOSYS, INC.
    Inventors: Bendik Kleveland, Dipak K. Sikdar, Rajesh Chopra, Jay Patel
  • Patent number: 8219778
    Abstract: The embodiments that are described herein provide random access to individual data storage locations of a group of buffers, which may be scattered in the memory. These embodiments provide a virtual memory interface that applies virtual addresses in a flat memory linear addressing space as indices into the physical memory addresses that are ordered into a sequence in accordance with the group of buffers. In this way, these embodiments enable a device (e.g., a processor) to directly and sequentially access all of the scattered physical memory locations of a fragmented data item, such as a packet, without having to perform any memory segmentation or paging processes. In some embodiments, these accesses include both read and write accesses to the scattered data storage locations.
    Type: Grant
    Filed: February 27, 2008
    Date of Patent: July 10, 2012
    Assignee: Microchip Technology Incorporated
    Inventors: Michael Palladino, Carl Gyllenhammer, Bendik Kleveland
  • Patent number: 7978448
    Abstract: A hybrid circuit (42) for use with communications transceivers. The hybrid circuit (42) combines the function of an ESD protection circuit (12) with the function of a TX/RX switch (10). The input node of the hybrid circuit (42) is connecting between the source of an ESD event (60) and a device to be protected (44). The hybrid circuit (42) includes an ESD protection element (50), which is triggered by a triggering transistor (52). The gate of the triggering transistor (52) is connected to a driver (54) for turning the triggering transistor (52) on during transmission and for turning the triggering transistor (52) off during reception.
    Type: Grant
    Filed: August 20, 2007
    Date of Patent: July 12, 2011
    Assignee: Microchip Technology Incorporated
    Inventors: Yuen Hui Chee, Thomas H. Lee, Bendik Kleveland
  • Patent number: 7759916
    Abstract: A voltage regulator device and accompanying methods are provided for providing efficient voltage regulation to an electronic device. Efficient regulator 400 receives an input voltage on VIN from a battery or some other power supply at node VIN and supplies a stable regulated voltage to load device 404 at node VOUT. Load device 404 pulls different amounts of current and requires different degrees of tolerance on the voltage at VOUT depending upon its operating conditions. Data collection and control circuit 401 is capable of enabling and disabling regulator 402 and regulator 403. Data collection and control circuit 401 is also capable of measuring certain performance parameters associated with load device 404 and the operating conditions of load device 404. Data collection and control circuit 401 enables regulator 402 if said operating conditions are such that when data collection and control circuit 401 enables regulator 403 the performance parameters associated with load 404 are below a predefined standard.
    Type: Grant
    Filed: May 12, 2008
    Date of Patent: July 20, 2010
    Assignee: Microchip Technology Incorporated
    Inventor: Bendik Kleveland
  • Patent number: 7728679
    Abstract: A calibration circuit (20, 50) and method (60) for calibrating the bias current of a VCO (10, 40) to minimize phase noise. The calibration circuit (20, 50) monitors the average voltage at the common-mode node of the VCO (10, 40) while varying the bias current over a predetermined range. The calibration circuit (20, 50) identifies the bias current associated with the minimum average common-mode voltage and utilizes this bias current for calibrating the biasing transistor of the VCO (10, 40).
    Type: Grant
    Filed: July 10, 2008
    Date of Patent: June 1, 2010
    Assignee: Microchip Technology, Inc.
    Inventors: Stanley Wang, Bendik Kleveland, Thomas H. Lee
  • Publication number: 20090278517
    Abstract: A voltage regulator device and accompanying methods are provided for providing efficient voltage regulation to an electronic device. Efficient regulator 400 receives an input voltage on VIN from a battery or some other power supply at node VIN and supplies a stable regulated voltage to load device 404 at node VOUT. Load device 404 pulls different amounts of current and requires different degrees of tolerance on the voltage at VOUT depending upon its operating conditions. Data collection and control circuit 401 is capable of enabling and disabling regulator 402 and regulator 403. Data collection and control circuit 401 is also capable of measuring certain performance parameters associated with load device 404 and the operating conditions of load device 404. Data collection and control circuit 401 enables regulator 402 if said operating conditions are such that when data collection and control circuit 401 enables regulator 403 the performance parameters associated with load 404 are below a predefined standard.
    Type: Application
    Filed: May 12, 2008
    Publication date: November 12, 2009
    Applicant: ZEROG WIRELESS, INC.
    Inventor: Bendik Kleveland
  • Patent number: 7603244
    Abstract: A calibration circuit (20, 50) and method (60) for calibrating the bias current of a VCO (10, 40) to minimize phase noise. The calibration circuit (20, 50) monitors the average voltage at the common-mode node of the VCO (10, 40) while varying the bias current over a predetermined range. The calibration circuit (20, 50) identifies the bias current associated with the minimum average common-mode voltage and utilizes this bias current for calibrating the biasing transistor of the VCO (10, 40).
    Type: Grant
    Filed: July 10, 2008
    Date of Patent: October 13, 2009
    Assignee: ZeroG Wireless, Inc.
    Inventors: Stanley Wang, Bendik Kleveland, Thomas H. Lee
  • Publication number: 20090216964
    Abstract: The embodiments that are described herein provide random access to individual data storage locations of a group of buffers, which may be scattered in the memory. These embodiments provide a virtual memory interface that applies virtual addresses in a flat memory linear addressing space as indices into the physical memory addresses that are ordered into a sequence in accordance with the group of buffers. In this way, these embodiments enable a device (e.g., a processor) to directly and sequentially access all of the scattered physical memory locations of a fragmented data item, such as a packet, without having to perform any memory segmentation or paging processes. In some embodiments, these accesses include both read and write accesses to the scattered data storage locations.
    Type: Application
    Filed: February 27, 2008
    Publication date: August 27, 2009
    Inventors: Michael Palladino, Carl Gyllenhammer, Bendik Kleveland
  • Publication number: 20090207824
    Abstract: A wireless (such as Wi-Fi or similar) access point is included in or attached to a device, such as a cellular phone, WiMAX device, other mobile device, etc. One or more wireless units wirelessly access a communication network (and in some cases the Internet) through the wireless access point device. Additionally, such a wireless access point device can receive a transmission from a wireless tag that has been attached to an object to be monitored and can forward information from the wireless tag to a target device along with location information.
    Type: Application
    Filed: February 20, 2009
    Publication date: August 20, 2009
    Applicant: ZeroG Wireless, Inc.
    Inventors: Thomas H. Lee, Michael Palladino, Bendik Kleveland, Vinay Malekal
  • Publication number: 20090197557
    Abstract: A differential diversity antenna is provided. In one embodiment, a differential diversity antenna is used in a wireless system comprising receiver circuitry. (and, in another embodiment, transmission circuitry). The differential diversity antenna comprises a plurality of antenna components that are aligned non-collinearly to achieve diversity. In another embodiment, the differential diversity antenna is used with a second differential diversity antenna. Other embodiments are disclosed, and each of the embodiments can be used alone or together in combination.
    Type: Application
    Filed: February 4, 2008
    Publication date: August 6, 2009
    Inventors: Thomas H. Lee, Bendik Kleveland
  • Publication number: 20090195946
    Abstract: In one embodiment of the present invention, an electrostatic discharge protection circuit provides efficient electrostatic discharge protection to an RFIC. The circuit includes several parts such as an inductor coupled from a first rail to an internal node. A power amplifier transistor having a transconductance control node is coupled to internal circuitry, a first terminal coupled to a second rail, and a second terminal coupled to an internal node. The circuit also comprises a pad coupled to an internal node, and this pad is capable of being coupled to off chip systems such as an antenna. The power amplifier transistor serves as the active device for an RF power amplifier. The inductor serves as one of either a bias inductor or a tank inductor for the RF power amplifier. Additionally the inductor acts as a low impedance path to the first rail to protect the power amplifier transistor during an ESD pulse.
    Type: Application
    Filed: February 5, 2008
    Publication date: August 6, 2009
    Applicant: ZEROG WIRELESS, INC.
    Inventor: Bendik Kleveland
  • Patent number: 7570035
    Abstract: A voltage regulator circuit and method are provided for regulating a voltage accurately in response to rapid variations in the regulator's load. The voltage regulator utilizes a hybrid loop; an embodiment of such utilization is exemplified by circuit 300. Amplifier 301 controls the current flowing through pass element 303 from an unregulated input voltage node Vin to a regulated voltage output node Vout. The regulated output voltage is provided to load 311 so that the voltage across the load stays constant regardless of variations in the current it pulls. The value of the regulated voltage is set by feedback network 302 and the input voltage at node Vref. The regulator feedback loop formed by amplifier 301, pass element 303, and feedback network 302 regulate the voltage at Vout in response to low frequency perturbations in load 311. In response to high frequency perturbations, a sensing network triggers control circuitry 310. Such a sensing network is exemplified in this embodiment by comparators 308 and 309.
    Type: Grant
    Filed: August 1, 2007
    Date of Patent: August 4, 2009
    Assignee: ZeroG Wireless, Inc.
    Inventor: Bendik Kleveland
  • Patent number: 7564707
    Abstract: An apparatus includes a semiconductor substrate, elongated diffused well regions, and elongated conductors. The semiconductor substrate has a first electrical conductivity type. The elongated diffused well regions are in the semiconductor substrate. The diffused well regions have a second electrical conductivity type opposite the first electrical conductivity type. Each of the elongated electrical conductors crosses the diffused well regions at respective locations of one-time programmable memory cells. Each of the memory cells includes a antifuse structure between the respective diffused well region and the respective electrical conductor. Each of the memory cells has a first state in which the antifuse structure has a first electrical resistance and a second state in which the antifuse structure has a second electrical resistance lower than the first electrical resistance.
    Type: Grant
    Filed: August 22, 2007
    Date of Patent: July 21, 2009
    Assignee: ZeroG Wireless, Inc.
    Inventor: Bendik Kleveland
  • Publication number: 20090052220
    Abstract: An apparatus includes a semiconductor substrate, elongated diffused well regions, and elongated conductors. The semiconductor substrate has a first electrical conductivity type. The elongated diffused well regions are in the semiconductor substrate. The diffused well regions have a second electrical conductivity type opposite the first electrical conductivity type. Each of the elongated electrical conductors crosses the diffused well regions at respective locations of one-time programmable memory cells. Each of the memory cells includes a antifuse structure between the respective diffused well region and the respective electrical conductor. Each of the memory cells has a first state in which the antifuse structure has a first electrical resistance and a second state in which the antifuse structure has a second electrical resistance lower than the first electrical resistance.
    Type: Application
    Filed: August 22, 2007
    Publication date: February 26, 2009
    Inventor: Bendik Kleveland
  • Publication number: 20090052099
    Abstract: A hybrid circuit (42) for use with communications transceivers. The hybrid circuit (42) combines the function of an ESD protection circuit (12) with the function of a TX/RX switch (10). The input node of the hybrid circuit (42) is connecting between the source of an ESD event (60) and a device to be protected (44). The hybrid circuit (42) includes an ESD protection element (50), which is triggered by a triggering transistor (52). The gate of the triggering transistor (52) is connected to a driver (54) for turning the triggering transistor (52) on during transmission and for turning the triggering transistor (52) off during reception.
    Type: Application
    Filed: August 20, 2007
    Publication date: February 26, 2009
    Applicant: ZeroG Wireless, Inc.
    Inventors: Yuen Hui Chee, Thomas H. Lee, Bendik Kleveland
  • Publication number: 20090033298
    Abstract: A voltage regulator circuit and method are provided for regulating a voltage accurately in response to rapid variations in the regulator's load. The voltage regulator utilizes a hybrid loop; an embodiment of such utilization is exemplified by circuit 300. Amplifier 301 controls the current flowing through pass element 303 from an unregulated input voltage node Vin to a regulated voltage output node Vout. The regulated output voltage is provided to load 311 so that the voltage across the load stays constant regardless of variations in the current it pulls. The value of the regulated voltage is set by feedback network 302 and the input voltage at node Vref. The regulator feedback loop formed by amplifier 301, pass element 303, and feedback network 302 regulate the voltage at Vout in response to low frequency perturbations in load 311. In response to high frequency perturbations, a sensing network triggers control circuitry 310. Such a sensing network is exemplified in this embodiment by comparators 308 and 309.
    Type: Application
    Filed: August 1, 2007
    Publication date: February 5, 2009
    Applicant: ZeroG Wireless, Inc.
    Inventor: Bendik Kleveland
  • Patent number: 7482888
    Abstract: A startup circuit 200 and method 700 is provided for quickly starting up a resonator based oscillator. Tunable oscillator 201 provides an impetus signal to oscillator 205 through capacitor 202. The impetus signal has a frequency that is an estimate of the resonant frequency of resonator 205. The circuit measures the frequency of oscillator 204 and the frequency of tunable oscillator 201. The circuit then adjusts the frequency of tunable oscillator 201 such that the frequency of the tunable oscillator is substantially equal to the resonant frequency of the resonator 205 and stores a data state necessary for the tunable oscillator 201 to generate a signal with this target frequency in the future. During an ensuing startup cycle the stored data state causes the impetus signal delivered by tunable oscillator 202 to be substantially equal to the target frequency of oscillator 204 which improves startup performance.
    Type: Grant
    Filed: July 12, 2007
    Date of Patent: January 27, 2009
    Assignee: ZeroG Wireless, Inc.
    Inventor: Bendik Kleveland