Abstract: The preferred embodiments described herein provide a method and system for increasing programming bandwidth in a non-volatile memory device. In one preferred embodiment, a memory device is provided with a plurality of bits to be stored in a respective plurality of memory cells along a wordline. Some of the bits represent a programmed state, and others represent an un-programmed state. The duration of the programming pulse applied to the wordline is determined by the number of bits that represent the programmed state. In another preferred embodiment, the plurality of bits to be stored in the memory device comprises a first set of bits representing a modification to the stored data and a second set of bits representing an un-programmed state. Other preferred embodiments are provided, and each of the preferred embodiments can be used alone or in combination with one another.

Abstract: A three-dimensional memory array includes a plurality of rail-stacks on each of several levels forming alternating levels of X-lines and Y-lines for the array. Memory cells are formed at the intersection of each X-line and Y-line. The memory cells of each memory plane are all oriented in the same direction relative to the substrate, forming a serial chain diode stack. In certain embodiments, row and column circuits for the array are arranged to interchange function depending upon the directionality of memory cells in the selected memory plane. High-voltage drivers for the X-lines and Y-lines are each capable of passing a write current in either direction depending on the direction of the selected memory cell. A preferred bias arrangement reverse biases only unselected memory cells within the selected memory plane, totaling approximately N2 memory cells, rather than approximately 3N2 memory cells as with prior arrays.

Abstract: An integrated voltage source includes a charge pump having multiple charge pump stages connected in series. A first one of the these charge pump stages is connected to the high voltage output of the charge pump, and the remaining charge pump stages are coupled to this first charge pump stage in a manner such that substantially all the charge pumped by all of the additional charge pump stages is also pumped by the first charge pump stage. In one mode of operation, the first charge pump stage and at least one additional charge pump stage are enabled. In another mode of operation, the first charge pump stage and at least two additional charge pump stages are enabled. A control circuit determines the mode of operation and, therefore, the number of charge pump stages that are enabled.

Abstract: The preferred embodiments described herein provide a memory device and method for sensing while programming a non-volatile memory cell. In one preferred embodiment, a memory device is provided with a memory cell and a detection circuit. While the memory cell is being programmed, the detection circuit determines whether the memory cell is in a programmed state. If the memory cell is in a programmed state, the programming of the memory cell is terminated. As compared with prior programming approaches, this preferred embodiment reduces programming time and power while increasing programming bandwidth (the number of memory cells that can be programmed per unit time). In another preferred embodiment, a plurality of memory cells along a wordline are programmed simultaneously. Other preferred embodiments are provided, and each of the preferred embodiments can be used alone or in combination with one another.

Abstract: The preferred embodiments described herein provide a method and system for increasing programming bandwidth in a non-volatile memory device. In one preferred embodiment, a memory device is provided with a plurality of bits to be stored in a respective plurality of memory cells along a wordline. Some of the bits represent a programmed state, and others represent an un-programmed state. The duration of the programming pulse applied to the wordline is determined by the number of bits that represent the programmed state. In another preferred embodiment, the plurality of bits to be stored in the memory device comprises a first set of bits representing a modification to the stored data and a second set of bits representing an un-programmed state. Other preferred embodiments are provided, and each of the preferred embodiments can be used alone or in combination with one another.

Abstract: An integrated voltage source includes a charge pump having multiple charge pump stages connected in series. A first one of the these charge pump stages is connected to the high voltage output of the charge pump, and the remaining charge pump stages are coupled to this first charge pump stage in a manner such that substantially all the charge pumped by all of the additional charge pump stages is also pumped by the first charge pump stage. In one mode of operation, the first charge pump stage and at least one additional charge pump stage are enabled. In another mode of operation, the first charge pump stage and at least two additional charge pump stages are enabled. A control circuit determines the mode of operation and, therefore, the number of charge pump stages that are enabled.

Abstract: An integrated circuit current source includes an oscillator, a capacitor, a capacitor charging circuit and a capacitor discharging circuit, all formed on an integrated circuit substrate. The capacitor, capacitor charging circuit, and capacitor discharging circuit form a switched capacitor circuit having a resistance that varies inversely with the frequency of oscillation of the oscillator. This switched capacitor circuit is included in a bias signal generator that generates a bias signal at a level that varies in accordance with frequency of the oscillating signal. This bias signal is used to control frequency of the oscillator to provide a stable frequency of oscillation and a stable output current.

Abstract: A distributed electrostatic discharge (ESD) protection circuit for high frequency integrated circuits. A transmission line from an integrated circuit (IC) pad or package pin couples a plurality of ESD elements. The ESD elements, such as diodes, are distributed along the transmission line and coupled from the transmission line to ground or a power supply. The effective impedance of the transmission line and ESD elements is defined to match the impedance of an external line. Distributed ESD protection circuits provide a high frequency signal path that can be used well into the GHz frequency range and also provide effective ESD protection.

Abstract: A method and an apparatus for adjusting the slew rate and impedance of a buffer in an integrated circuitry. In one embodiment, an integrated circuit buffer includes a pre-driver circuit, which includes a slew rate compensation circuit, coupled to a driver circuit, which includes an impedance compensation circuit. The slew rate compensation circuit includes parallel connected p-channel transistors to power and parallel connected n-channel transistors to ground to provide a variable resistance to virtual rails for inverter circuits that are included in the pre-driver circuit. The slew rate compensation circuit is digitally controlled with slew rate control signals. The impedance compensation circuit includes parallel connected p-channel transistors to power and parallel connected n-channel transistors to ground from an output node of the buffer. The parallel connected transistors of the impedance compensation circuit are digitally controlled with impedance control signals.

Abstract: A bus termination method and apparatus, specifically, a terminator circuit, a driver/terminator circuit, and appropriate control logic. The terminator circuit and the driver/terminator circuit provide termination of an interface node to one of a first and a second voltage potential selected according to a previous logic value sampled on the input node at a time determined by a clock signal. The driver/terminator circuit also drives data values on the interface node. The terminator circuit and the driver/terminator circuit can be used in bus agents in a computer system. In one computer system configuration, a driving bus agent drives a signal line which is terminated by a predetermined terminating bus agent. Each bus agent compares its device identification to a bus master identification to determine whether to drive, terminate, or tristate the bus.