Patents by Inventor Benjamin Chu-Kung

Benjamin Chu-Kung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140084239
    Abstract: Non-planar semiconductor devices having channel regions with low band-gap cladding layers are described. For example, a semiconductor device includes a vertical arrangement of a plurality of nanowires disposed above a substrate. Each nanowire includes an inner region having a first band gap and an outer cladding layer surrounding the inner region. The cladding layer has a second, lower band gap. A gate stack is disposed on and completely surrounds the channel region of each of the nanowires. The gate stack includes a gate dielectric layer disposed on and surrounding the cladding layer and a gate electrode disposed on the gate dielectric layer. Source and drain regions are disposed on either side of the channel regions of the nanowires.
    Type: Application
    Filed: September 27, 2012
    Publication date: March 27, 2014
    Inventors: Marko Radosavljevic, Gilbert Dewey, Benjamin Chu-Kung, Dipanjan Basu, Sanaz K. Gardner, Satyarth Suri, Ravi Pillarisetty, Niloy Mukherjee, Han Wui Then, Robert S. Chau
  • Publication number: 20140061589
    Abstract: A quantum well transistor has a germanium quantum well channel region. A silicon-containing etch stop layer provides easy placement of a gate dielectric close to the channel. A group III-V barrier layer adds strain to the channel. Graded silicon germanium layers above and below the channel region improve performance. Multiple gate dielectric materials allow use of a high-k value gate dielectric.
    Type: Application
    Filed: October 18, 2013
    Publication date: March 6, 2014
    Inventors: Ravi Pillarisetty, Been-Yin Jin, Benjamin Chu-Kung, Matthew V. Metz, Jack T. Kavalieros, Marko Radosavljevic, Roza Kotlyar, Willy Rachmady, Niloy Mukherjee, Gilbert Dewey, Robert S. Chau
  • Publication number: 20140054548
    Abstract: Techniques are disclosed for forming a non-planar germanium quantum well structure. In particular, the quantum well structure can be implemented with group IV or III-V semiconductor materials and includes a germanium fin structure. In one example case, a non-planar quantum well device is provided, which includes a quantum well structure having a substrate (e.g. SiGe or GaAs buffer on silicon), a IV or III-V material barrier layer (e.g., SiGe or GaAs or AlGaAs), a doping layer (e.g., delta/modulation doped), and an undoped germanium quantum well layer. An undoped germanium fin structure is formed in the quantum well structure, and a top barrier layer deposited over the fin structure. A gate metal can be deposited across the fin structure. Drain/source regions can be formed at respective ends of the fin structure.
    Type: Application
    Filed: November 1, 2013
    Publication date: February 27, 2014
    Inventors: Ravi Pillarisetty, Jack T. Kavalieros, Willy Rachmady, Uday Shah, Benjamin Chu-Kung, Marko Radosavljevic, Niloy Mukherjee, Gilbert Dewey, Been-Yih Jin, Robert S. Chau
  • Publication number: 20140001519
    Abstract: A fin is formed over a first barrier layer over a substrate. The first barrier layer has a band gap greater than the band gap of the fin. In one embodiment, a gate dielectric layer is deposited on the top surface and opposing sidewalls of the fin and is adjacent to a second barrier layer deposited on the first barrier layer underneath the fin. In one embodiment, the gate dielectric layer is deposited on the top surface and the opposing sidewalls of the fin and an isolating layer is formed adjacent to the first barrier layer underneath the fin. In one embodiment, the gate dielectric layer is deposited on the top surface and the opposing sidewalls of the fin, and an isolating layer is formed adjacent to the second barrier layer deposited between the fin and the first barrier layer.
    Type: Application
    Filed: June 29, 2012
    Publication date: January 2, 2014
    Inventors: Gilbert Dewey, Marko Radosavljevic, Ravi Pillarisetty, Benjamin Chu-Kung, Niloy Mukherjee
  • Publication number: 20130334499
    Abstract: A method is provided. The method includes forming a plurality of nanowires on a top surface of a substrate and forming an oxide layer adjacent to a bottom surface of each of the plurality of nanowires, wherein the oxide layer is to isolate each of the plurality of nanowires from the substrate.
    Type: Application
    Filed: August 2, 2013
    Publication date: December 19, 2013
    Inventors: Benjamin Chu-Kung, Uday Shah, Ravi Pillarisetty, Been-Yin Jin, Marko Radosavljevic, Willy Rachmady
  • Publication number: 20130313520
    Abstract: Embodiments of an apparatus and methods of providing a quantum well device for improved parallel conduction are generally described herein. Other embodiments may be described and claimed.
    Type: Application
    Filed: August 1, 2013
    Publication date: November 28, 2013
    Inventors: Ravi Pillarisetty, Mantu Hudait, Been-Yih Jin, Benjamin Chu-Kung, Robert Chau
  • Patent number: 8592803
    Abstract: A quantum well transistor has a germanium quantum well channel region. A silicon-containing etch stop layer provides easy placement of a gate dielectric close to the channel. A group III-V barrier layer adds strain to the channel. Graded silicon germanium layers above and below the channel region improve performance. Multiple gate dielectric materials allow use of a high-k value gate dielectric.
    Type: Grant
    Filed: April 9, 2012
    Date of Patent: November 26, 2013
    Assignee: Intel Corporation
    Inventors: Ravi Pillarisetty, Been-Yin Jin, Benjamin Chu-Kung, Matthew V. Metz, Jack T. Kavalieros, Marko Radosavljevic, Roza Kotlyar, Willy Rachmady, Niloy Mukherjee, Gilbert Dewey, Robert S. Chau
  • Publication number: 20130307513
    Abstract: Transistors suitable for high voltage and high frequency operation. A nanowire is disposed vertically or horizontally on a substrate. A longitudinal length of the nanowire is defined into a channel region of a first semiconductor material, a source region electrically coupled with a first end of the channel region, a drain region electrically coupled with a second end of the channel region, and an extrinsic drain region disposed between the channel region and drain region. The extrinsic drain region has a wider bandgap than that of the first semiconductor. A gate stack including a gate conductor and a gate insulator coaxially wraps completely around the channel region, drain and source contacts similarly coaxially wrap completely around the drain and source regions.
    Type: Application
    Filed: December 19, 2011
    Publication date: November 21, 2013
    Inventors: Han Wui Then, Robert Chau, Benjamin Chu-Kung, Gilbert Dewey, Jack Kavalieros, Matthew Metz, Niloy Mukherjee, Ravi Pillarisetty, Marko Radosavljevic
  • Publication number: 20130292698
    Abstract: III-N transistors with recessed gates. An epitaxial stack includes a doped III-N source/drain layer and a III-N etch stop layer disposed between a the source/drain layer and a III-N channel layer. An etch process, e.g., utilizing photochemical oxidation, selectively etches the source/drain layer over the etch stop layer. A gate electrode is disposed over the etch stop layer to form a recessed-gate III-N HEMT. At least a portion of the etch stop layer may be oxidized with a gate electrode over the oxidized etch stop layer for a recessed gate III-N MOS-HEMT including a III-N oxide. A high-k dielectric may be formed over the oxidized etch stop layer with a gate electrode over the high-k dielectric to form a recessed gate III-N MOS-HEMT having a composite gate dielectric stack.
    Type: Application
    Filed: December 23, 2011
    Publication date: November 7, 2013
    Inventors: Han Wui Then, Marko Radosavljevic, Uday Shah, Niloy Mukherjee, Ravi Pillarisetty, Benjamin Chu-Kung, Jack T. Kavalieros, Robert S. Chau
  • Patent number: 8575596
    Abstract: Techniques are disclosed for forming a non-planar germanium quantum well structure. In particular, the quantum well structure can be implemented with group IV or III-V semiconductor materials and includes a germanium fin structure. In one example case, a non-planar quantum well device is provided, which includes a quantum well structure having a substrate (e.g. SiGe or GaAs buffer on silicon), a IV or III-V material barrier layer (e.g., SiGe or GaAs or AlGaAs), a doping layer (e.g., delta/modulation doped), and an undoped germanium quantum well layer. An undoped germanium fin structure is formed in the quantum well structure, and a top barrier layer deposited over the fin structure. A gate metal can be deposited across the fin structure. Drain/source regions can be formed at respective ends of the fin structure.
    Type: Grant
    Filed: October 9, 2012
    Date of Patent: November 5, 2013
    Assignee: Intel Corporation
    Inventors: Ravi Pillarisetty, Jack T. Kavalieros, Willy Rachmady, Uday Shah, Benjamin Chu-Kung, Marko Radosavljevic, Niloy Mukherjee, Gilbert Dewey, Been Y. Jin, Robert S. Chau
  • Publication number: 20130277683
    Abstract: Transistors for high voltage and high frequency operation. A non-planar, polar crystalline semiconductor body having a top surface disposed between first and second opposite sidewalls includes a channel region with a first crystalline semiconductor layer disposed over the first and second sidewalls. The first crystalline semiconductor layer is to provide a two dimensional electron gas (2DEG) within the channel region. A gate structure is disposed over the first crystalline semiconductor layer along at least the second sidewall to modulate the 2DEG. First and second sidewalls of the non-planar polar crystalline semiconductor body may have differing polarity, with the channel proximate to a first of the sidewalls. The gate structure may be along a second of the sidewalls to gate a back barrier. The polar crystalline semiconductor body may be a group III-nitride formed on a silicon substrate with the (10 10) plane on a (110) plane of the silicon.
    Type: Application
    Filed: December 19, 2011
    Publication date: October 24, 2013
    Inventors: Han Wui Then, Robert Chau, Benjamin Chu-Kung, Gilbert Dewey, Jack Kavalieros, Matthew Metz, Niloy Mukherjee, Ravi Pillarisetty, Marko Radosavljevic
  • Publication number: 20130277714
    Abstract: Transistor structures having channel regions comprising alternating layers of compressively and tensilely strained epitaxial materials are provided. The alternating epitaxial layers can form channel regions in single and multigate transistor structures. In alternate embodiments, one of the two alternating layers is selectively etched away to form nanoribbons or nanowires of the remaining material. The resulting strained nanoribbons or nanowires form the channel regions of transistor structures. Also provided are computing devices comprising transistors comprising channel regions comprised of alternating compressively and tensilely strained epitaxial layers and computing devices comprising transistors comprising channel regions comprised of strained nanoribbons or nanowires.
    Type: Application
    Filed: December 9, 2011
    Publication date: October 24, 2013
    Inventors: Van H. Le, Benjamin Chu-Kung, Harold Hal W. Kennel, Willy Rachmady, Ravi Pillarisetty, Jack T. Kavalieros
  • Publication number: 20130279145
    Abstract: A group III-N nanowire is disposed on a substrate. A longitudinal length of the nanowire is defined into a channel region of a first group III-N material, a source region electrically coupled with a first end of the channel region, and a drain region electrically coupled with a second end of the channel region. A second group III-N material on the first group III-N material serves as a charge inducing layer, and/or barrier layer on surfaces of nanowire. A gate insulator and/or gate conductor coaxially wraps completely around the nanowire within the channel region. Drain and source contacts may similarly coaxially wrap completely around the drain and source regions.
    Type: Application
    Filed: December 19, 2011
    Publication date: October 24, 2013
    Inventors: Han Wui Then, Robert Chau, Benjamin Chu-Kung, Gilbert Dewey, Jack Kavalieros, Matthew Metz, Niloy Mukherjee, Ravi Pillarisetty, Marko Radosavljevic
  • Publication number: 20130270512
    Abstract: Architectures and techniques for co-integration of heterogeneous materials, such as group III-V semiconductor materials and group IV semiconductors (e.g., Ge) on a same substrate (e.g. silicon). In embodiments, multi-layer heterogeneous semiconductor material stacks having alternating nanowire and sacrificial layers are employed to release nanowires and permit formation of a coaxial gate structure that completely surrounds a channel region of the nanowire transistor. In embodiments, individual PMOS and NMOS channel semiconductor materials are co-integrated with a starting substrate having a blanket layers of alternating Ge/III-V layers. In embodiments, vertical integration of a plurality of stacked nanowires within an individual PMOS and individual NMOS device enable significant drive current for a given layout area.
    Type: Application
    Filed: December 19, 2011
    Publication date: October 17, 2013
    Inventors: Marko Radosavljevic, Ravi Pillarisetty, Gilbert Dewey, Niloy Mukherjee, Jack Kavalieros, Willy Rachmady, Van Le, Benjamin Chu-Kung, Matthew Metz, Robert Chau
  • Publication number: 20130240838
    Abstract: Embodiments of the present disclosure describe structures and techniques to increase carrier injection velocity for integrated circuit devices. An integrated circuit device includes a semiconductor substrate, a first barrier film coupled with the semiconductor substrate, a quantum well channel coupled to the first barrier film, the quantum well channel comprising a first material having a first bandgap energy, and a source structure coupled to launch mobile charge carriers into the quantum well channel, the source structure comprising a second material having a second bandgap energy, wherein the second bandgap energy is greater than the first bandgap energy. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: April 29, 2013
    Publication date: September 19, 2013
    Inventors: Marko Radosavljevic, Benjamin Chu-Kung, Gilbert Dewey, Niloy Mukherjee
  • Patent number: 8525151
    Abstract: Embodiments of an apparatus and methods of providing a quantum well device for improved parallel conduction are generally described herein. Other embodiments may be described and claimed.
    Type: Grant
    Filed: July 10, 2012
    Date of Patent: September 3, 2013
    Assignee: Intel Corporation
    Inventors: Ravi Pillarisetty, Mantu Hudait, Been-Yih Jin, Benjamin Chu-Kung, Robert Chau
  • Patent number: 8525162
    Abstract: A method is provided. The method includes forming a plurality of nanowires on a top surface of a substrate and forming an oxide layer adjacent to a bottom surface of each of the plurality of nanowires, wherein the oxide layer is to isolate each of the plurality of nanowires from the substrate.
    Type: Grant
    Filed: November 8, 2011
    Date of Patent: September 3, 2013
    Assignee: Intel Corporation
    Inventors: Benjamin Chu-Kung, Uday Shah, Ravi Pillarisetty, Been-Yih Jin, Marko Radosavljevic, Willy Rachmady
  • Publication number: 20130146845
    Abstract: Techniques are disclosed for providing a low resistance self-aligned contacts to devices formed in a semiconductor heterostructure. The techniques can be used, for example, for forming contacts to the gate, source and drain regions of a quantum well transistor fabricated in III-V and SiGe/Ge material systems. Unlike conventional contact process flows which result in a relatively large space between the source/drain contacts to gate, the resulting source and drain contacts provided by the techniques described herein are self-aligned, in that each contact is aligned to the gate electrode and isolated therefrom via spacer material.
    Type: Application
    Filed: February 4, 2013
    Publication date: June 13, 2013
    Inventors: Ravi Pillarisetty, Benjamin Chu-Kung, Mantu K. Hudait, Marko Radiosavljevic, Jack T. Kavalieros, Willy Rachmady, Niloy Mukherjee, Robert S. Chau
  • Patent number: 8440998
    Abstract: Embodiments of the present disclosure describe structures and techniques to increase carrier injection velocity for integrated circuit devices. An integrated circuit device includes a semiconductor substrate, a first barrier film coupled with the semiconductor substrate, a quantum well channel coupled to the first barrier film, the quantum well channel comprising a first material having a first bandgap energy, and a source structure coupled to launch mobile charge carriers into the quantum well channel, the source structure comprising a second material having a second bandgap energy, wherein the second bandgap energy is greater than the first bandgap energy. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: December 21, 2009
    Date of Patent: May 14, 2013
    Assignee: Intel Corporation
    Inventors: Marko Radosavljevic, Benjamin Chu-Kung, Gilbert Dewey, Niloy Mukherjee
  • Publication number: 20130062594
    Abstract: A method is provided. The method includes forming a plurality of nanowires on a top surface of a substrate and forming an oxide layer adjacent to a bottom surface of each of the plurality of nanowires, wherein the oxide layer is to isolate each of the plurality of nanowires from the substrate.
    Type: Application
    Filed: November 8, 2011
    Publication date: March 14, 2013
    Inventors: Benjamin Chu-Kung, Uday Shah, Ravi Pillarisetty, Been-Yih Jin, Marko Radosavljevic, Willy Rachmady