Abstract: Semiconductor devices (e.g., gate-all-around (GAA) devices), process tools for manufacturing GAA devices and methods of manufacturing GAA devices, and inner spacer liners and inner spacers for GAA devices, are described. The methods comprise performing a chemical vapor deposition (CVD) process to form an amorphous silicon liner and an inner spacer within a superlattice structure formed on a top surface of a semiconductor substrate. The superlattice structure has a plurality of semiconductor material layers (e.g., silicon germanium (SiGe)) and a corresponding plurality of channel layers (e.g., silicon (Si)). The amorphous silicon liner is conformally formed along the GAA device, including along the recessed semiconductor material layers and the corresponding plurality of channel layers, and the inner spacer is formed directly on the amorphous silicon liner. One or more operations of the methods described herein are performed in situ in an integrated processing tool system.

Abstract: Semiconductor devices and methods of manufacturing the same are described. The method includes forming distinct and separate bottom dielectric isolation layers underneath the source/drain and underneath the gate of a gate all around device. Selectively remove of the bottom dielectric isolation layer underneath the source/drain results in better backside power rail (BPR) via alignment to the source/drain epi and reduces reliability and gate-shorting problems.

Abstract: Semiconductor devices (e.g., GAA device structures) and processing methods and cluster tools for forming GAA device structures are described. The cluster tools for forming GAA device structures comprise a first etch chamber, a second etch chamber, and a third etch chamber. Each of the first etch chamber and the second etch chamber independently comprises a single-wafer chamber or an immersion chamber. One or more of the first etch chamber or the second etch chamber may be a wet etch chamber. In some embodiments, at least one of the first etch chamber, the second etch chamber, and the third etch chamber is a dry etch chamber. The cluster tool described herein advantageously reduces the number of cleaning processes, the total time between cleaning and processing operations, variations in time between processing and variation in sidewall loss compared to conventional cluster tools.

Abstract: Embodiments of the present disclosure generally relate to metal gate devices. In one or more embodiments, a method for preparing a device with an airgap is provided and includes depositing a silicon-containing layer on inner surfaces of trenches formed in a metal-gate layer disposed on a substrate, depositing a carbon-containing layer on the silicon-containing layer in the trenches, the carbon-containing layer is deposited to fill at least a lower half of the trenches from the bottom, and leaving a temporary gap within each trench at the top. The method also includes depositing a low-k dielectric layer on the carbon-containing layer and the silicon-containing layer to fill the temporary gap, and exposing at least the carbon-containing layer to a treatment process to remove the carbon-containing layer and form the airgap between the silicon-containing layer and the low-k dielectric layer.

Abstract: Methods and structure for gate-all-around (GAA) semiconductor device that can support multiple threshold voltages. The semiconductor device can include a first channel. The first channel can overlaid by a first dielectric layer. The first dielectric layer can be overlaid by a second dielectric layer. The semiconductor device can include a second channel. The second channel can be overlaid by a third dielectric layer. The first dielectric layer can be a doped dielectric layer. The the third dielectric layer can be overlaid by a fourth dielectric layer. The semiconductor device can include a work-function metal layer overlaying the second dielectric layer and the fourth dielectric layer.

Abstract: Approaches herein provide devices and methods for forming optimized gate-all-around transistors. One method may include forming a plurality of nanosheets each comprising a plurality of alternating first layers and second layers, and etching the plurality of nanosheets to laterally recess the second layers relative to the first layers. The method may further include forming an inner spacer over the recessed second layers by forming a spacer material along an exposed portion of each of the plurality of nanosheets, etching the spacer material to remove the spacer material from the first layers of each of the plurality of nanosheets, and performing a sidewall treatment to the plurality of nanosheets after the spacer material is removed from the first layers of each of the plurality of nanosheets.

Abstract: Semiconductor devices and methods of manufacturing the same are described. The method includes forming a bottom dielectric isolation (BDI) layer on a substrate and depositing a template material in the source/drain trench. The template material is crystallized. Epitaxially growth of the source and drain regions then proceeds, which growth advantageously occurring on the bottom and sidewalls of the source and drain regions.

Abstract: Described are semiconductor devices, e.g., GAA, FinFET, CFET, having a bilayer dielectric wall. Methods of forming a semiconductor device form a bilayer dielectric wall during the formation of the shallow trench isolation (STI). The first or liner dielectric layer of the bilayer dielectric wall is designed to allow the second or core dielectric layer to withstand downstream etching and to be removed prior to formation of the source/drain epitaxial regions. In some embodiments, the core dielectric layer is removed to form an airgap, mitigating the performance penalty associated with the bilayer dielectric wall.

Abstract: Semiconductor devices and methods of manufacturing the same are described. The method includes forming distinct and separate bottom dielectric isolation layers underneath the source/drain and underneath the gate of a gate all around device. Selectively remove of the bottom dielectric isolation layer underneath the source/drain results in better backside power rail (BPR) via alignment to the source/drain epi and reduces reliability and gate-shorting problems.

Abstract: Semiconductor devices and methods of manufacturing the same are described. A silicon wafer is provided and an etch stop bilayer is formed on the silicon wafer. The insertion of an etch stop bilayer in the starting wafer will serve as an etch stop for deep trench formation on the wafer frontside and for wafer backside planarization. With this approach variations in the sacrificial material depth in a GAA device and substrate thickness may offer benefits in lithography overlay control.

Abstract: A finFET device includes a doped source and/or drain extension that is disposed between a gate spacer of the finFET and a bulk semiconductor portion of the semiconductor substrate on which the n-doped or p-doped source or drain extension is disposed. The doped source or drain extension is formed by a selective epitaxial growth (SEG) process in a cavity formed proximate the gate spacer. After formation of the cavity, advanced processing controls (APC) (i.e., integrated metrology) is used to determine the distance of recess, without exposing the substrate to an oxidizing environment. The isotropic etch process, the metrology, and selective epitaxial growth may be performed in the same platform.

Abstract: Approaches herein provide devices and methods for forming optimized gate-all-around transistors. One method may include forming a plurality of nanosheets each comprising a plurality of alternating first layers and second layers, and etching the plurality of nanosheets to laterally recess the second layers relative to the first layers. The method may further include forming an inner spacer over the recessed second layers by forming a spacer material along an exposed portion of each of the plurality of nanosheets, etching the spacer material to remove the spacer material from the first layers of each of the plurality of nanosheets, and performing a sidewall treatment to the plurality of nanosheets after the spacer material is removed from the first layers of each of the plurality of nanosheets.

Abstract: A method of forming a portion of a gate-all-around field-effect transistor (GAA FET) includes performing an isotropic etch process to partially etch a substrate from source/drain (S/D) recesses extending into a front inter-layer dielectric (ILD) formed on the substrate, performing a substrate nitridation process to form nitride layers on inner surfaces of the S/D recesses, and performing a substrate removal process to selectively etch the substrate while protecting underlying extension regions within the S/D recesses by the nitride layers and form ILD recesses.

Abstract: A method of forming backside contacts to source/drain (S/D) regions of a semiconductor structure includes removing a substrate selectively to shallow trench isolations (STIs) and the extension regions to form first recesses between the STIs, filling the first recesses with first dielectric material, forming second recesses aligned to the S/D regions through the first dielectric material, and forming backside contacts to the extension regions within the second recesses.

Abstract: Described are semiconductor devices, e.g., PMOS and/or NMOS, with improved stress in the channel region. The semiconductor devices include a substrate, a source region, a drain region, a channel extending between the source region and the drain region, and a diffusion break patterned through the device. The self-aligned diffusion break opening is gap filled a stressed dielectric material using a densified seam-free silicon-containing material gap fill process.

Abstract: Embodiments described herein generally relate to methods of forming hardmask and bottom dielectric isolation layers in vertical trench structures. A method of forming a gate-all-around field-effect transistor includes depositing a conformal oxide layer on a channel surface and a bottom surface of vertical structures of a substrate, the vertical structures including an NMOS portion having NMOS vertical structures defining NMOS contact trenches and a PMOS portion having PMOS structures defining PMOS contact trenches having a PMOS source/drain layer deposited therein. The method further includes selectively etching the conformal oxide layer at the bottom surface of the vertical structures, inhibiting the conformal oxide layer, selectively depositing a nitride layer at the bottom surface of the vertical structures, etching the conformal oxide layer to expose the channel surface of the vertical structures, and depositing an NMOS source/drain layer on the bottom surface of the NMOS contact trenches.

Abstract: A method of forming a semiconductor device, the method including forming a superlattice structure on a substrate, the superlattice structure including a plurality of first layers and a corresponding plurality of second layers, the first layers and the second layers being alternatingly arranged in a plurality of stacked pairs; forming one or more gate and gate spacers in a gate region on the substrate; forming a plurality of nanosheets from the superlattice structure; filling the corresponding plurality of voids with a plurality of dummy dielectric interlayers; etching the plurality of nanosheets between the one or more gate and gate spacers to form one or more source regions and one or more drain regions; forming an inner spacer on the plurality of dummy dielectric interlayers; and depositing a source material in the one or more source regions and a drain material in the one or more drain regions.

Abstract: Horizontal gate-all-around devices and methods of manufacturing are described. The hGAA devices include a fully-depleted silicon-on-insulator (FD-SOI) under the channel layers in the same footprint as the hGAA. The buried dielectric isolation layer of the FD-SOI includes one or more of silicon oxide (SiOx), silicon nitride (SiN), silicon carbide (SiC), and a high-k material, and the buried dielectric isolation layer has a thickness in a range of from 0 nm to 10 nm.

Abstract: Horizontal gate-all-around devices and methods of manufacturing same are described. The hGAA devices comprise a doped semiconductor material between source regions and drain regions of the device. The method includes doping semiconductor material layers between source regions and drain regions of an electronic device.

Abstract: A method of forming a portion of a gate-all-around field-effect transistor (GAA FET) includes forming placeholders, each interfacing with an extension region electrically isolated from replacement-metal-gate (RMG) stacks by inner spacers, in recesses formed within portions of a substrate isolated by shallow trench isolations (STIs), the recesses extending into a front inter-layer dielectric (ILD) formed on the substrate, removing the placeholders selectively to the substrate and the STIs, forming a cavity at an exposed surface of the extension region within each of the recesses, forming a contact layer within the cavity, forming an interface on the contact layer, and a contact metallization process to form a metal contact within each of the recesses, selectively etching the substrate against the RMG stacks and form ILD recesses between adjacent metal contacts, forming a dielectric liner surrounding the metal contacts, and forming a back ILD in each of the ILD recesses.