Patents by Inventor Benjamin Colombeau

Benjamin Colombeau has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12363948
    Abstract: Horizontal gate-all-around devices and methods of manufacturing same are described. The hGAA devices comprise an oxide layer and a semiconductor material layer between source regions and drain regions of the device. The method includes growing a conformal epitaxial layer on a nanosheet channel layer, followed by radical plasma oxidation (RPO) to oxidize the conformal epitaxial layer. An alternative method includes growing a conformal epitaxial layer on a nanosheet channel layer, followed by a surface treatment, and then radical plasma oxidation (RPO) to oxidize the conformal epitaxial layer.
    Type: Grant
    Filed: October 11, 2021
    Date of Patent: July 15, 2025
    Assignee: Applied Materials, Inc.
    Inventors: Myungsun Kim, Andy Lo, Eric Davey, Michael Stolfi, Benjamin Colombeau
  • Publication number: 20250218870
    Abstract: Embodiments of the present disclosure relate to a method of forming a contact structure on a substrate. The method includes forming a high aspect ratio (HAR) feature within a substrate having a device formed thereon. The device includes a plurality of channels disposed through a polysilicon layer and extending in a first direction, and an isolation layer disposed on the substrate, the polysilicon layer separated from the isolation layer by a dielectric layer. The forming of the HAR feature is formed a first distance in a second direction from the plurality of channels and includes removing a portion of the isolation layer and the polysilicon layer. The method further includes etching the polysilicon layer to expose a top surface of the isolation layer that is opposite to a surface that is disposed on the surface of the substrate, and exposing a metal layer within the HAR feature.
    Type: Application
    Filed: January 2, 2025
    Publication date: July 3, 2025
    Inventors: Ashish PAL, Gregory COSTRINI, El Mehdi BAZIZI, Veeraraghavan S. BASKER, Benjamin COLOMBEAU, Balasubramanian PRANATHARTHIHARAN
  • Publication number: 20250212459
    Abstract: A system and method for fabricating a gate all-around (GAA) field effect transistor (FET) is disclosed. The method includes: forming a plurality of epitaxy layers on a substrate, wherein a formed epitaxy layer includes a plurality of doped channels, a plurality of metal channels, and a dummy gate; depositing a spacer in a source/drain cavity, wherein at least a portion of the spacer is deposited on a dummy gate of a formed epitaxy layer; partially etching the plurality of metal channels of to create a plurality of voids; depositing an inner spacer in each void of the plurality of voids; and depositing a stressed metal filler in the source/drain cavity.
    Type: Application
    Filed: December 20, 2023
    Publication date: June 26, 2025
    Applicant: Applied Materials, Inc.
    Inventors: Nicolas BREIL, Benjamin COLOMBEAU, Balasubramanian PRANATHARTHIHARAN, Pratik VYAS, Ashish PAL, El Mehdi BAZIZI
  • Publication number: 20250203942
    Abstract: Horizontal gate-all-around devices and methods of manufacturing same are described. The hGAA devices comprise an oxide layer and a semiconductor material layer between source regions and drain regions of the device. The method includes growing a conformal epitaxial layer on a nanosheet channel layer, followed by radical plasma oxidation (RPO) to oxidize the conformal epitaxial layer. An alternative method includes growing a conformal epitaxial layer on a nanosheet channel layer, followed by a surface treatment, and then radical plasma oxidation (RPO) to oxidize the conformal epitaxial layer.
    Type: Application
    Filed: February 26, 2025
    Publication date: June 19, 2025
    Applicant: Applied Materials, Inc.
    Inventors: Myungsun Kim, Andy Lo, Eric Davey, Michael Stolfi, Benjamin Colombeau
  • Patent number: 12327761
    Abstract: A method of forming a contact trench structure in a semiconductor device, the method includes performing a first selective deposition process to form a contact on sidewalls of a trench, each of the sidewalls of the trench comprising a first cross section of a first material and a second cross section of a second material, performing a second selective deposition process to form a metal silicide layer on the contact, performing a first metal fill process to form a contact plug within the trench, the first metal fill process including depositing a contact plug metal material within the trench, performing an etch process to form an opening within the trench, comprising partially etching the contact plug metal material within the trench, and performing a second metal fill process, the second metal fill process comprising depositing the contact plug metal material within the opening.
    Type: Grant
    Filed: April 25, 2022
    Date of Patent: June 10, 2025
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Nicolas Louis Breil, Byeong Chan Lee, Benjamin Colombeau
  • Publication number: 20250142957
    Abstract: Logic devices and methods of manufacturing logic devices are provided. The semiconductor logic device includes an n-channel gate-all-around (n-GAA) field-effect transistor on a substrate integrated with a p-channel gate-all-around (p-GAA) field-effect transistor on the substrate adjacent to the n-channel gate-all-around (p-GAA) field-effect transistor. The n-channel gate-all-around (n-GAA) field effect-transistor has a structure including a plurality of layers comprising silicon and a corresponding plurality of layers comprising at least 25% germanium alternatingly arranged in stacked pairs extending between a source region and a drain region, and the p-channel gate-all-around (p-GAA) field-effect transistor has a plurality of layers comprising in a range of from 5% to 15% germanium and a corresponding plurality of layers comprising at least 25% germanium alternatingly arranged in stacked pairs.
    Type: Application
    Filed: October 10, 2024
    Publication date: May 1, 2025
    Applicant: Applied Materials, Inc.
    Inventors: Sai Hooi Yeong, Steven C.H. Hung, Veeraraghavan S. Basker, Benjamin Colombeau, Balasubramanian Pranatharthiharan
  • Publication number: 20250112054
    Abstract: Exemplary methods of semiconductor processing may include providing an etchant precursor to a processing region of a semiconductor processing chamber. A structure may be disposed within the processing region. The structure may include a first silicon-containing material. The structure may include a second silicon-containing material, an oxygen-containing material, or both. The methods may include contacting the structure with the etchant precursor. The contacting with the etchant precursor may etch at least a portion of the second silicon-containing material or the oxygen-containing material from the structure. The methods may include providing a carbon-containing precursor to the processing region of the semiconductor processing chamber. The methods may include contacting the structure with the carbon-containing precursor. The contacting with the carbon-containing precursor may replenish carbon in the first silicon-containing material.
    Type: Application
    Filed: September 24, 2024
    Publication date: April 3, 2025
    Applicant: Applied Materials, Inc.
    Inventors: Yuriy Shusterman, Sean Reidy, Sai Hooi Yeong, Lisa Megan McGill, Benjamin Colombeau, Andre P. Labonte, Veeraraghavan S. Basker, Balasubramanian Pranatharthiharan
  • Publication number: 20250113577
    Abstract: Embodiments of the disclosure advantageously provide semiconductor devices, fin field effect transistors (FinFETs) in particular, and methods of manufacturing such devices having improved effective capacitance (Ceff). The FinFETs include a gate structure in which airgaps are provided by recessing a high-k material layer disposed between the gate structure and a spacer layer, thereby reducing the effective dielectric constant in the high-k dielectric layer and improving effective capacitance (Ceff) of the device.
    Type: Application
    Filed: September 23, 2024
    Publication date: April 3, 2025
    Applicant: Applied Materials, Inc.
    Inventors: Veeraraghavan S. Basker, Sai Hooi Yeong, Ashish Pal, El Mehdi Bazizi, Benjamin Colombeau, Balasubramanian Pranatharthiharan
  • Patent number: 12261047
    Abstract: A method of selectively and conformally doping semiconductor materials is disclosed. Some embodiments utilize a conformal dopant film deposited selectively on semiconductor materials by thermal decomposition. Some embodiments relate to doping non-line of sight surfaces. Some embodiments relate to methods for forming a highly doped crystalline semiconductor layer.
    Type: Grant
    Filed: August 5, 2022
    Date of Patent: March 25, 2025
    Assignee: Applied Materials, Inc.
    Inventors: Wolfgang Aderhold, Yi-Chiau Huang, Wei Liu, Benjamin Colombeau, Abhilash Mayur
  • Patent number: 12249511
    Abstract: A method of forming a semiconductor structure includes annealing a surface of a substrate in an ambient of hydrogen to smooth the surface, pre-cleaning the surface of the substrate, depositing a high-? dielectric layer on the pre-cleaned surface of the substrate, performing a re-oxidation process to thermally oxidize the surface of the substrate; performing a plasma nitridation process to insert nitrogen atoms in the deposited high-? dielectric layer, and performing a post-nitridation anneal process to passivate chemical bonds in the plasma nitridated high-? dielectric layer.
    Type: Grant
    Filed: March 4, 2021
    Date of Patent: March 11, 2025
    Assignee: Applied Materials, Inc.
    Inventors: Steven C. H. Hung, Lin Dong, Benjamin Colombeau, Johanes F. Swenberg, Linlin Wang
  • Patent number: 12243941
    Abstract: Horizontal gate-all-around devices and methods of manufacturing the same are described. The hGAA devices comprise an oxidize layer on a semiconductor material between source regions and drain regions of the device. The method includes radical plasma oxidation (RPO) of semiconductor material layers between source regions and drain regions of an electronic device.
    Type: Grant
    Filed: July 28, 2021
    Date of Patent: March 4, 2025
    Assignee: Applied Materials, Inc.
    Inventors: Myungsun Kim, Michael Stolfi, Benjamin Colombeau, Andy Lo
  • Publication number: 20250040170
    Abstract: A method of forming a portion of a gate-all-around field-effect transistor (GAA FET) includes forming placeholders, each interfacing with an extension region via a cap layer, in recesses formed in portions of a substrate isolated by shallow trench isolations (STIs), the recesses extending into an inter-layer dielectric (ILD) formed on the substrate, removing the placeholders selectively to the substrate, the cap layers, and the STIs, forming selective cap layers at bottoms of the recesses, performing a substrate removal process to isotropically etch the substrate within the recesses, performing a conformal deposition process to form a spacer on exposed surfaces of the substrate and the selective cap layers within the recesses, sculpting the spacer on sidewalls of the substrate and the STIs within the recesses, performing a cap layer removal process to remove the cap layers within the recesses, and forming metal contacts within the recesses.
    Type: Application
    Filed: June 10, 2024
    Publication date: January 30, 2025
    Inventors: Veeraraghavan S. BASKER, Gregory COSTRINI, Ashish PAL, Benjamin COLOMBEAU, Balasubramanian PRANATHARTHIHARAN
  • Patent number: 12183798
    Abstract: A method of forming a gate stack structure includes forming a dipole metal layer on a high-? gate dielectric layer on a semiconductor structure formed on a substrate, annealing the dipole metal layer, and removing the dipole metal layer. The dipole metal layer comprises dopants in the high-? gate dielectric layer.
    Type: Grant
    Filed: November 17, 2021
    Date of Patent: December 31, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Steven C. H. Hung, Benjamin Colombeau, Myungsun Kim, Srinivas Gandikota, Yixiong Yang, Jacqueline Samantha Wrench, Yong Yang
  • Publication number: 20240332388
    Abstract: One or more embodiments of the disclosure are directed to methods of forming semiconductor devices, e.g., gate-all-around (GAA) transistors that are used in FEOL and/or BEOL processes. The processes described herein may be integrated and performed in any suitable cluster tool. Some embodiments of the disclosure are directed to cavity shaping processes. Further embodiments of the disclosure are directed to logic transistors with wrap-around backside source/drain contact.
    Type: Application
    Filed: March 19, 2024
    Publication date: October 3, 2024
    Applicant: Applied Materials, Inc.
    Inventors: Byeong Chan Lee, Benjamin Colombeau, Nicolas Breil, Ashish Pal, El Mehdi Bazizi, Veeraraghavan S. Basker, Balasubramanian Pranatharthiharan, Pratik B. Vyas, Gregory Costrini
  • Publication number: 20240321584
    Abstract: Semiconductor devices, such as gate-all-around (GAA) devices, and methods of forming semiconductor devices are described. Selective oxidation processes that are useful in front-end of line (FEOL) and back-end of line (BEOL) applications and processes are also described. In FEOL processes, for example, selective oxidation protects silicon germanium (SiGe) layers during etching silicon (Si) channel recess when there is no dielectric inner spacer present. In BEOL processes, for example, selective oxidation protects growth of silicon germanium (SiGe) layers on the sidewall of a superlattice structure during bottom-up epitaxial growth.
    Type: Application
    Filed: March 13, 2024
    Publication date: September 26, 2024
    Applicant: Applied Materials, Inc.
    Inventors: Byeong Chan Lee, Benjamin Colombeau, Edy Cardona, Christopher S. Olsen, Shawn Thomas
  • Publication number: 20240290884
    Abstract: The present technology includes semiconductor devices with improved stress in a channel region. The semiconductor devices include a substrate, a source region, a drain region, a channel region that includes at least one channel located between the source and the drain, a first gate region, and a second gate region. The first gate region includes a self-aligned single diffusion break, and the second gate region includes a first gate enclosing the channel between the source region and the drain region. The self-aligned single diffusion break also contains a stressed dielectric material having a stress of about 500 MPa or greater.
    Type: Application
    Filed: February 14, 2024
    Publication date: August 29, 2024
    Applicant: Applied Materials, Inc.
    Inventors: El Mehdi Bazizi, Sai Hooi Yeong, Benjamin Colombeau, Balasubramanian Pranatharthiharan, Hui Zhao, Ashish Pal
  • Publication number: 20240290883
    Abstract: The present technology includes semiconductor devices with improved stress in a channel region. The semiconductor device includes a substrate, a source region, a drain region, a channel region that includes at least one channel located between the source and the drain, a first gate region, and a second gate region. The first gate region includes a self-aligned single diffusion break, and the second gate region includes a first gate enclosing the channel between the source region and the drain region. The self-aligned single diffusion break also contains a dielectric liner and a stressed metal fill, where the stressed metal fill exhibits a stress of about 350 MPa or greater.
    Type: Application
    Filed: February 14, 2024
    Publication date: August 29, 2024
    Applicant: Applied Materials, Inc.
    Inventors: Sai Hooi Yeong, Hui Zhao, Ashish Pal, El Mehdi Bazizi, Benjamin Colombeau, Balasubramanian Pranatharthiharan, Lequn Liu
  • Publication number: 20240290885
    Abstract: The present technology includes semiconductor devices with improved stress in a channel region. The semiconductor device includes a substrate, a source region, a drain region, a channel region that includes at least one channel located between the source and the drain. Devices include a first gate region having a first self-aligned single diffusion break in a n-MOS region, and a second gate region includes having a self-aligned single diffusion break in a p-MOS region. The second self-aligned single diffusion break also contains a liner and a compressive stressed material, where the stressed metal fill exhibits a compressive stress of about 350 MPa or greater.
    Type: Application
    Filed: February 14, 2024
    Publication date: August 29, 2024
    Applicant: Applied Materials, Inc.
    Inventors: Sai Hooi Yeong, Benjamin Colombeau, Balasubramanian Pranatharthiharan, El Mehdi Bazizi, Hui Zhao, Ashish Pal
  • Patent number: 12062708
    Abstract: Horizontal gate-all-around devices and methods of manufacturing same are described. The hGAA devices comprise a trimmed semiconductor material between source regions and drain regions of the device. The method includes selectively isotropically etching semiconductor material layers between source regions and drain regions of an electronic device.
    Type: Grant
    Filed: October 18, 2022
    Date of Patent: August 13, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Michael Stolfi, Myungsun Kim, Benjamin Colombeau, Sanjay Natarajan
  • Publication number: 20240234531
    Abstract: Semiconductor devices (e.g., gate-all-around (GAA) devices), process tools for manufacturing GAA devices and methods of manufacturing GAA devices, and inner spacer liners and inner spacers for GAA devices, are described. The methods comprise performing a chemical vapor deposition (CVD) process to form an amorphous silicon liner and an inner spacer within a superlattice structure formed on a top surface of a semiconductor substrate. The superlattice structure has a plurality of semiconductor material layers (e.g., silicon germanium (SiGe)) and a corresponding plurality of channel layers (e.g., silicon (Si)). The amorphous silicon liner is conformally formed along the GAA device, including along the recessed semiconductor material layers and the corresponding plurality of channel layers, and the inner spacer is formed directly on the amorphous silicon liner. One or more operations of the methods described herein are performed in situ in an integrated processing tool system.
    Type: Application
    Filed: December 13, 2023
    Publication date: July 11, 2024
    Applicant: Applied Materials, Inc.
    Inventors: Sai Hooi Yeong, Liu Jiang, Susmit Singha Roy, Abhijit Basu Mallick, Benjamin Colombeau, El Mehdi Bazizi, Balasubramanian Pranatharthiharan