Patents by Inventor Benjamin Colombeau
Benjamin Colombeau has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240136229Abstract: A method of forming a multi-layer semiconductor device on a substrate includes forming a superlattice of a plurality of alternating first layers composed of a first material and second layers formed of a second material, removing the second layers of the superlattice, etching the first material layers to form trimmed first layers therefrom, wherein the quantity of material removed from different ones of the first layers are different amounts, forming a capping layer over the first layers, measuring at least one of the distance between the capping layers formed on the different ones of the first layers, the thicknesses of the different ones of the capping layers formed on different ones of the trimmed first layers, and the different thicknesses of the combined thickness of different ones of the trimmed first layers and the capping layer formed thereover, and based on differences in the measurements, calculating a new thickness of the etched first layers.Type: ApplicationFiled: September 6, 2023Publication date: April 25, 2024Inventors: Jody FRONHEISER, Sai Hooi YEONG, Benjamin COLOMBEAU, Balasubramanian PRANATHARTHIHARAN, Lequn LIU
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Publication number: 20240120193Abstract: Exemplary methods of semiconductor processing may include etching a portion of a silicon-containing material from a substrate disposed within a processing region of a semiconductor processing chamber. The silicon-containing material may extend into one or more recesses defined by alternating layers of material deposited on the substrate. The methods may include providing a carbon-containing precursor to the processing region of the semiconductor processing chamber. The methods may include contacting a remaining silicon-containing material with the carbon-containing precursor. The contacting with the carbon-containing precursor may replenish carbon in the silicon-containing material. The methods may include providing a cleaning agent to the processing region of the semiconductor processing chamber. The methods may include contacting the substrate with the cleaning agent. The contacting with the cleaning precursor may remove surface oxide from the substrate.Type: ApplicationFiled: October 5, 2022Publication date: April 11, 2024Applicant: Applied Materials, Inc.Inventors: Shankar Venkataraman, Zeqing Shen, Susmit Singha Roy, Abhijit Basu Mallick, Lakmal C. Kalutarage, Jongbeom Seo, Sai Hooi Yeong, Benjamin Colombeau, Balasubramanian Pranatharthiharan
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Patent number: 11923441Abstract: Described is a method of manufacturing a gate-all-around electronic device. The method includes forming a thermal oxide layer though an enhanced in situ steam generation process in combination with atomic layer deposition of a low-? layer. The thin thermal oxide layer passivates the interface between the silicon layer and the dielectric layer of the GAA. A passivation process after the deposition of the low-? layer reduces the bulk trap and enhances the breakdown performance of the GAA transistor.Type: GrantFiled: August 16, 2022Date of Patent: March 5, 2024Assignee: Applied Materials, Inc.Inventors: Steven C. H. Hung, Benjamin Colombeau, Andy Lo, Byeong Chan Lee, Johanes F. Swenberg, Theresa Kramer Guarini, Malcolm J. Bevan
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Publication number: 20240038553Abstract: Semiconductor devices (e.g., GAA device structures) and processing methods and cluster tools for forming GAA device structures are described. The cluster tools for forming GAA device structures comprise a first etch chamber, a second etch chamber, and a third etch chamber. Each of the first etch chamber and the second etch chamber independently comprises a single-wafer chamber or an immersion chamber. One or more of the first etch chamber or the second etch chamber may be a wet etch chamber. In some embodiments, at least one of the first etch chamber, the second etch chamber, and the third etch chamber is a dry etch chamber. The cluster tool described herein advantageously reduces the number of cleaning processes, the total time between cleaning and processing operations, variations in time between processing and variation in sidewall loss compared to conventional cluster tools.Type: ApplicationFiled: July 25, 2023Publication date: February 1, 2024Applicant: Applied Materials, Inc.Inventors: Benjamin Colombeau, Balasubramanian Pranatharthiharan, Lequn Liu, Brian K. Kirkpatrick
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Publication number: 20240014214Abstract: Horizontal gate-all-around devices and methods of manufacturing same are described. The hGAA devices comprise a semiconductor material between source regions and drain regions of the device. The method includes formation of a cladding material on a first material followed by a dry oxidation process resulting rearrangement of the cladding material and first material.Type: ApplicationFiled: July 10, 2023Publication date: January 11, 2024Applicant: Applied Materials, Inc.Inventors: Sai Hooi Yeong, Jody A. Fronheiser, Benjamin Colombeau, Balasubramanian Pranatharthiharan, El Mehdi Bazizi, Ashish Pal
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Publication number: 20230377997Abstract: A method of forming a contact layer in a semiconductor structure includes performing a pre-clean process on exposed surfaces of a plurality of first semiconductor regions and a plurality of second semiconductor regions formed on a substrate, wherein the exposed surfaces of the plurality of first and second semiconductor regions are each disposed within openings formed in a dielectric layer disposed over the substrate, performing a first selective epitaxial deposition process to form a first contact layer on the exposed surfaces of the first semiconductor regions and a second contact layer on the exposed surface of the second semiconductor regions, performing a patterning process to form a patterned stack, wherein the patterned stack comprises a patterned layer that comprises openings formed over the first contact layer disposed within each opening in the dielectric layer and a portion of the patterned layer that is disposed over each second contact layer disposed within each opening in the dielectric layer, aType: ApplicationFiled: March 20, 2023Publication date: November 23, 2023Inventors: Nicolas Louis BREIL, Balasubramanian PRANATHARTHIHARAN, Benjamin COLOMBEAU, Anchuan WANG
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Publication number: 20230299199Abstract: Examples of the present technology include processing methods to incorporate stress in a channel region of a semiconductor transistor. The methods may include depositing a stressed material on an adjacent layer, where the adjacent layer is disposed between the stressed material and semiconductor material having an incorporated dopant. The adjacent layer may be characterized by an increased stress level after the deposition of the stressed material. The method may further include heating the stressed material and the adjacent layer, and removing the stressed material from the adjacent layer. The adjacent layer retains at least a portion of the increased stress after the removal of the stressed material. Examples of the present technology also include semiconductor structures having a conductive layer with first stress, and an intermediate layer with second stress in contact with the conductive layer. The second tensile stress may be at least ten times the first tensile stress.Type: ApplicationFiled: May 26, 2023Publication date: September 21, 2023Applicant: Applied Materials, Inc.Inventors: Ashish Pal, Mehdi Saremi, El Mehdi Bazizi, Benjamin Colombeau
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Publication number: 20230260909Abstract: Semiconductor devices and methods of manufacturing the same are described. The method includes forming a diffusion break opening on the backside and filling with a diffusion break material to serve as a planarization stop. In some embodiments, a single diffusion break opening is formed. In other embodiments, a mixed diffusion break opening is formed.Type: ApplicationFiled: February 7, 2023Publication date: August 17, 2023Applicant: Applied Materials, Inc.Inventors: Andrew Yeoh, Benjamin Colombeau, Balasubramanian Pranatharthiharan, El Mehdi Bazizi, Ashish Pal
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Publication number: 20230260908Abstract: Semiconductor devices and methods of manufacturing the same are described. The method includes forming distinct and separate bottom dielectric isolation layers underneath the source/drain and underneath the gate of a gate all around device. Selectively remove of the bottom dielectric isolation layer underneath the source/drain results in better backside power rail (BPR) via alignment to the source/drain epi and reduces reliability and gate-shorting problems.Type: ApplicationFiled: February 7, 2023Publication date: August 17, 2023Applicant: Applied Materials, Inc.Inventors: Andrew Yeoh, Benjamin Colombeau, Balasubramanian Pranatharthiharan, Ashish Pal, El Mehdi Bazizi
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Patent number: 11699755Abstract: Examples of the present technology include processing methods to incorporate stress in a channel region of a semiconductor transistor. The methods may include depositing a stressed material on an adjacent layer, where the adjacent layer is disposed between the stressed material and semiconductor material having an incorporated dopant. The adjacent layer may be characterized by an increased stress level after the deposition of the stressed material. The method may further include heating the stressed material and the adjacent layer, and removing the stressed material from the adjacent layer. The adjacent layer retains at least a portion of the increased stress after the removal of the stressed material. Examples of the present technology also include semiconductor structures having a conductive layer with first stress, and an intermediate layer with second stress in contact with the conductive layer. The second tensile stress may be at least ten times the first tensile stress.Type: GrantFiled: August 24, 2020Date of Patent: July 11, 2023Assignee: Applied Materials, Inc.Inventors: Ashish Pal, Mehdi Saremi, El Mehdi Bazizi, Benjamin Colombeau
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Publication number: 20230178419Abstract: Generally, examples described herein relate to methods and processing systems for forming isolation structures (e.g., shallow trench isolations (STIs)) between fins on a substrate. In an example, fins are formed on a substrate. A liner layer is conformally formed on and between the fins. Forming the liner layer includes conformally depositing a pre-liner layer on and between the fins, and densifying, using a plasma treatment, the pre-liner layer to form the liner layer. A dielectric material is formed on the liner layer.Type: ApplicationFiled: January 31, 2023Publication date: June 8, 2023Applicant: Applied Materials, Inc.Inventors: Benjamin COLOMBEAU, Theresa Kramer GUARINI, Malcolm BEVAN, Rui CHENG
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Publication number: 20230178628Abstract: Approaches herein provide devices and methods for forming optimized gate-all-around transistors. One method may include forming a plurality of nanosheets each comprising a plurality of alternating first layers and second layers, and etching the plurality of nanosheets to laterally recess the second layers relative to the first layers. The method may further include forming an inner spacer over the recessed second layers by forming a spacer material along an exposed portion of each of the plurality of nanosheets, etching the spacer material to remove the spacer material from the first layers of each of the plurality of nanosheets, and performing a sidewall treatment to the plurality of nanosheets after the spacer material is removed from the first layers of each of the plurality of nanosheets.Type: ApplicationFiled: October 17, 2022Publication date: June 8, 2023Applicant: Applied Materials, Inc.Inventors: Benjamin Colombeau, Balasubramanian Pranatharthiharan, Lequn Liu
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Publication number: 20230170400Abstract: Semiconductor devices and methods of manufacturing the same are described. The method includes front side processing to form a source/drain cavity and filling the cavity with a sacrificial layer. The sacrificial layer is then removed during processing of the backside to form a backside power rail via that is filled with a metal fill.Type: ApplicationFiled: November 28, 2022Publication date: June 1, 2023Applicant: Applied Materials, Inc.Inventors: Ashish Pal, Benjamin Colombeau, El Mehdi Bazizi, Balasubramanian Pranatharthiharan
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Publication number: 20230067331Abstract: Semiconductor devices and methods of manufacturing the same are described. The method includes forming a bottom dielectric isolation (BDI) layer on a substrate and depositing a template material in the source/drain trench. The template material is etched and then crystallized. Epitaxially growth of the source and drain regions then proceeds, with growth advantageously occurring on the bottom and sidewalls of the source and drain regions.Type: ApplicationFiled: August 26, 2022Publication date: March 2, 2023Applicant: Applied Materials, Inc.Inventors: Ashish Pal, El Mehdi Bazizi, Benjamin Colombeau
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Publication number: 20230040606Abstract: Semiconductor devices and methods of manufacturing the same are described. The method includes forming a bottom dielectric isolation (BDI) layer on a substrate and depositing a template material in the source/drain trench. The template material is crystallized. Epitaxially growth of the source and drain regions then proceeds, which growth advantageously occurring on the bottom and sidewalls of the source and drain regions.Type: ApplicationFiled: August 2, 2022Publication date: February 9, 2023Applicant: Applied Materials, Inc.Inventors: Benjamin Colombeau, Saurabh Chopra, Myungsun Kim, Balasubramanian Pranatharthiharan
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Publication number: 20230039074Abstract: Horizontal gate-all-around devices and methods of manufacturing same are described. The hGAA devices comprise a trimmed semiconductor material between source regions and drain regions of the device. The method includes selectively isotropically etching semiconductor material layers between source regions and drain regions of an electronic device.Type: ApplicationFiled: October 18, 2022Publication date: February 9, 2023Applicant: Applied Materials, Inc.Inventors: Michael Stolfi, Myungsun Kim, Benjamin Colombeau, Sanjay Natarajan
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Publication number: 20230014586Abstract: Horizontal gate-all-around devices and methods of manufacturing same are described. The hGAA devices comprise a doped semiconductor material between source regions and drain regions of the device. The method includes doping semiconductor material layers between source regions and drain regions of an electronic device.Type: ApplicationFiled: September 29, 2022Publication date: January 19, 2023Applicant: Applied Materials, Inc.Inventors: Benjamin Colombeau, Hans-Joachim Gossmann
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Publication number: 20220399457Abstract: Described is a method of manufacturing a gate-all-around electronic device. The method includes forming a thermal oxide layer though an enhanced in situ steam generation process in combination with atomic layer deposition of a low-? layer. The thin thermal oxide layer passivates the interface between the silicon layer and the dielectric layer of the GAA. A passivation process after the deposition of the low-? layer reduces the bulk trap and enhances the breakdown performance of the GAA transistor.Type: ApplicationFiled: August 16, 2022Publication date: December 15, 2022Applicant: Applied Materials, Inc.Inventors: Steven C.H. Hung, Benjamin Colombeau, Andy Lo, Byeong Chan Lee, Johanes F. Swenberg, Theresa Kramer Guarini, Malcolm J. Bevan
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Publication number: 20220384258Abstract: A method of forming a contact trench structure in a semiconductor device, the method includes performing a first selective deposition process to form a contact on sidewalls of a trench, each of the sidewalls of the trench comprising a first cross section of a first material and a second cross section of a second material, performing a second selective deposition process to form a metal silicide layer on the contact, performing a first metal fill process to form a contact plug within the trench, the first metal fill process including depositing a contact plug metal material within the trench, performing an etch process to form an opening within the trench, comprising partially etching the contact plug metal material within the trench, and performing a second metal fill process, the second metal fill process comprising depositing the contact plug metal material within the opening.Type: ApplicationFiled: April 25, 2022Publication date: December 1, 2022Inventors: Nicolas Louis BREIL, Byeong Chan LEE, Benjamin COLOMBEAU
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Publication number: 20220375753Abstract: A method of selectively and conformally doping semiconductor materials is disclosed. Some embodiments utilize a conformal dopant film deposited selectively on semiconductor materials by thermal decomposition. Some embodiments relate to doping non-line of sight surfaces. Some embodiments relate to methods for forming a highly doped crystalline semiconductor layer.Type: ApplicationFiled: August 5, 2022Publication date: November 24, 2022Applicant: Applied Materials, Inc.Inventors: Wolfgang Aderhold, Yi-Chiau Huang, Wei Liu, Benjamin Colombeau, Abhilash Mayur