Abstract: Examples of the present technology include processing methods to incorporate stress in a channel region of a semiconductor transistor. The methods may include depositing a stressed material on an adjacent layer, where the adjacent layer is disposed between the stressed material and semiconductor material having an incorporated dopant. The adjacent layer may be characterized by an increased stress level after the deposition of the stressed material. The method may further include heating the stressed material and the adjacent layer, and removing the stressed material from the adjacent layer. The adjacent layer retains at least a portion of the increased stress after the removal of the stressed material. Examples of the present technology also include semiconductor structures having a conductive layer with first stress, and an intermediate layer with second stress in contact with the conductive layer. The second tensile stress may be at least ten times the first tensile stress.

Abstract: Generally, examples described herein relate to methods and processing systems for forming isolation structures (e.g., shallow trench isolations (STIs)) between fins on a substrate. In an example, fins are formed on a substrate. A liner layer is conformally formed on and between the fins. Forming the liner layer includes conformally depositing a pre-liner layer on and between the fins, and densifying, using a plasma treatment, the pre-liner layer to form the liner layer. A dielectric material is formed on the liner layer.

Abstract: Approaches herein provide devices and methods for forming optimized gate-all-around transistors. One method may include forming a plurality of nanosheets each comprising a plurality of alternating first layers and second layers, and etching the plurality of nanosheets to laterally recess the second layers relative to the first layers. The method may further include forming an inner spacer over the recessed second layers by forming a spacer material along an exposed portion of each of the plurality of nanosheets, etching the spacer material to remove the spacer material from the first layers of each of the plurality of nanosheets, and performing a sidewall treatment to the plurality of nanosheets after the spacer material is removed from the first layers of each of the plurality of nanosheets.

Abstract: Semiconductor devices and methods of manufacturing the same are described. The method includes front side processing to form a source/drain cavity and filling the cavity with a sacrificial layer. The sacrificial layer is then removed during processing of the backside to form a backside power rail via that is filled with a metal fill.

Abstract: Semiconductor devices and methods of manufacturing the same are described. The method includes forming a bottom dielectric isolation (BDI) layer on a substrate and depositing a template material in the source/drain trench. The template material is etched and then crystallized. Epitaxially growth of the source and drain regions then proceeds, with growth advantageously occurring on the bottom and sidewalls of the source and drain regions.

Abstract: Horizontal gate-all-around devices and methods of manufacturing same are described. The hGAA devices comprise a trimmed semiconductor material between source regions and drain regions of the device. The method includes selectively isotropically etching semiconductor material layers between source regions and drain regions of an electronic device.

Abstract: Semiconductor devices and methods of manufacturing the same are described. The method includes forming a bottom dielectric isolation (BDI) layer on a substrate and depositing a template material in the source/drain trench. The template material is crystallized. Epitaxially growth of the source and drain regions then proceeds, which growth advantageously occurring on the bottom and sidewalls of the source and drain regions.

Abstract: Horizontal gate-all-around devices and methods of manufacturing same are described. The hGAA devices comprise a doped semiconductor material between source regions and drain regions of the device. The method includes doping semiconductor material layers between source regions and drain regions of an electronic device.

Abstract: Described is a method of manufacturing a gate-all-around electronic device. The method includes forming a thermal oxide layer though an enhanced in situ steam generation process in combination with atomic layer deposition of a low-? layer. The thin thermal oxide layer passivates the interface between the silicon layer and the dielectric layer of the GAA. A passivation process after the deposition of the low-? layer reduces the bulk trap and enhances the breakdown performance of the GAA transistor.

Abstract: A method of forming a contact trench structure in a semiconductor device, the method includes performing a first selective deposition process to form a contact on sidewalls of a trench, each of the sidewalls of the trench comprising a first cross section of a first material and a second cross section of a second material, performing a second selective deposition process to form a metal silicide layer on the contact, performing a first metal fill process to form a contact plug within the trench, the first metal fill process including depositing a contact plug metal material within the trench, performing an etch process to form an opening within the trench, comprising partially etching the contact plug metal material within the trench, and performing a second metal fill process, the second metal fill process comprising depositing the contact plug metal material within the opening.

Abstract: A method of selectively and conformally doping semiconductor materials is disclosed. Some embodiments utilize a conformal dopant film deposited selectively on semiconductor materials by thermal decomposition. Some embodiments relate to doping non-line of sight surfaces. Some embodiments relate to methods for forming a highly doped crystalline semiconductor layer.

Abstract: Horizontal gate-all-around devices and methods of manufacturing same are described. The hGAA devices comprise a trimmed semiconductor material between source regions and drain regions of the device. The method includes selectively isotropically etching semiconductor material layers between source regions and drain regions of an electronic device.

Abstract: Horizontal gate-all-around devices and methods of manufacturing same are described. The hGAA devices comprise a doped semiconductor material between source regions and drain regions of the device. The method includes doping semiconductor material layers between source regions and drain regions of an electronic device.

Abstract: Electronic devices and methods of forming electronic devices with gate-all-around non-I/O devices and finlike structures for I/O devices are described. A plurality of dummy gates is etched to expose a fin comprising alternating layers of a first material and a second material. The second material layers are removed to create openings and the first material layers remaining are epitaxially grown to form a finlike structure.

Abstract: Processing methods may be performed to produce semiconductor structures. The methods may include forming a silicon layer over a semiconductor substrate. The forming may include forming a silicon layer incorporating a dopant. The methods may include oxidizing a portion of the silicon layer while maintaining a portion of the silicon layer in contact with the semiconductor substrate. The oxidizing may drive a portion of the dopant through the silicon layer and into the semiconductor substrate.

Abstract: Described is a method of manufacturing a gate-all-around electronic device. The method includes forming a thermal oxide layer though an enhanced in situ steam generation process in combination with atomic layer deposition of a low-? layer. The thin thermal oxide layer passivates the interface between the silicon layer and the dielectric layer of the GAA. A passivation process after the deposition of the low-? layer reduces the bulk trap and enhances the breakdown performance of the GAA transistor.

Abstract: A method of selectively and conformally doping semiconductor materials is disclosed. Some embodiments utilize a conformal dopant film deposited selectively on semiconductor materials by thermal decomposition. Some embodiments relate to doping non-line of sight surfaces. Some embodiments relate to methods for forming a highly doped crystalline semiconductor layer.

Abstract: Horizontal gate-all-around devices and methods of manufacturing are described. The hGAA devices comprise a fully-depleted silicon-on-insulator (FD-SOI) under the channel layers in the same footprint as the hGAA. The buried dielectric insulating layer of the FD-SOI comprises one or more of silicon oxide (SiOx), silicon nitride (SiN), silicon carbide (SiC), and a high-k material, and the buried dielectric insulating layer has a thickness in a range of from 0 nm to 10 nm.

Abstract: A method of forming a gate stack structure includes forming a dipole metal layer on a high-? gate dielectric layer on a semiconductor structure formed on a substrate, annealing the dipole metal layer, and removing the dipole metal layer. The dipole metal layer comprises dopants in the high-? gate dielectric layer.

Abstract: Electronic devices and methods of forming electronic devices with gate-all-around non-I/O devices and finlike structures for I/O devices are described. A plurality of dummy gates is etched to expose a fin comprising alternating layers of a first material and a second material. The second material layers are removed to create openings and the first material layers remaining are epitaxially grown to form a finlike structure.