Patents by Inventor Benjamin Colombeau

Benjamin Colombeau has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9865735
    Abstract: Embodiments described herein generally relate to methods and device structures for horizontal gate all around (hGAA) isolation and fin field effect transistor (FinFET) isolation. A superlattice structure comprising different materials arranged in an alternatingly stacked formation may be formed on a substrate. In one embodiment, at least one of the layers of the superlattice structure may be oxidized to form a buried oxide layer adjacent the substrate.
    Type: Grant
    Filed: May 11, 2016
    Date of Patent: January 9, 2018
    Assignee: Applied Materials, Inc.
    Inventors: Shiyu Sun, Naomi Yoshida, Theresa Kramer Guarini, Sung Won Jun, Vanessa Pena, Errol Antonio C. Sanchez, Benjamin Colombeau, Michael Chudzik, Bingxi Wood, Nam Sung Kim
  • Patent number: 9853129
    Abstract: A finFET device includes an n-doped source and/or drain extension that is disposed between a gate spacer of the finFET and a bulk semiconductor portion of the semiconductor substrate on which the n-doped source or drain extension is disposed. The n-doped source or drain extension is formed by a selective epitaxial growth (SEG) process in a cavity formed proximate the gate spacer.
    Type: Grant
    Filed: August 19, 2016
    Date of Patent: December 26, 2017
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Matthias Bauer, Hans-Joachim Ludwig Gossmann, Benjamin Colombeau
  • Publication number: 20170330960
    Abstract: A finFET device includes an n-doped source and/or drain extension that is disposed between a gate spacer of the finFET and a bulk semiconductor portion of the semiconductor substrate on which the n-doped source or drain extension is disposed. The n-doped source or drain extension is formed by a selective epitaxial growth (SEG) process in a cavity formed proximate the gate spacer.
    Type: Application
    Filed: August 19, 2016
    Publication date: November 16, 2017
    Inventors: Matthias BAUER, Hans-Joachim Ludwig GOSSMANN, Benjamin COLOMBEAU
  • Patent number: 9748364
    Abstract: A method for forming a three dimensional device. The method may include directing ions to an end surface of an extension region of a fin structure, the fin structure extending perpendicularly from a substrate plane and having a fin axis parallel to the substrate plane, wherein the ions have trajectories extending in a plane perpendicular to the substrate plane and parallel to the fin axis, wherein a portion of the fin structure is covered by a gate structure defining a channel region, and wherein the end surface is not covered by the gate structure.
    Type: Grant
    Filed: June 19, 2015
    Date of Patent: August 29, 2017
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Shiyu Sun, Naomi Yoshida, Benjamin Colombeau, Hans-Joachim L. Gossmann
  • Patent number: 9576819
    Abstract: A method of doping a compound semiconductor substrate includes: setting a first substrate temperature for the compound semiconductor substrate in a first temperature range; implanting a dopant species into the compound semiconductor substrate at a first ion dose at the first substrate temperature; and annealing the compound semiconductor substrate after the implanting the ions. In conjunction with the annealing, the first ion dose is effective to generate a first dopant activation in the first temperature range higher than a second dopant activation resulting from implantation of the first ion dose at a second substrate temperature below the first temperature range, and is higher than a third dopant activation resulting from implantation of the first ion dose at a third substrate temperature above the first temperature range.
    Type: Grant
    Filed: June 17, 2015
    Date of Patent: February 21, 2017
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Christopher R. Hatem, Benjamin Colombeau, Kevin Jones, Aaron Lind
  • Publication number: 20170018624
    Abstract: Embodiments described herein generally relate to methods and apparatus for horizontal gate all around (hGAA) isolation. A superlattice structure comprising different materials arranged in an alternatingly stacked formation may be formed on a substrate. The different materials may be silicon containing materials and one or more III/V materials. In one embodiment, at least one of the layers of the superlattice structure may be oxidized to form a buried oxide layer adjacent the substrate.
    Type: Application
    Filed: September 28, 2016
    Publication date: January 19, 2017
    Inventors: Shiyu SUN, Naomi YOSHIDA, Theresa Kramer GUARINI, Sung Won JUN, Benjamin COLOMBEAU, Michael CHUDZIK
  • Publication number: 20160336405
    Abstract: Embodiments described herein generally relate to methods and device structures for horizontal gate all around (hGAA) isolation and fin field effect transistor (FinFET) isolation. A superlattice structure comprising different materials arranged in an alternatingly stacked formation may be formed on a substrate. In one embodiment, at least one of the layers of the superlattice structure may be oxidized to form a buried oxide layer adjacent the substrate.
    Type: Application
    Filed: May 11, 2016
    Publication date: November 17, 2016
    Inventors: Shiyu SUN, Naomi YOSHIDA, Theresa Kramer GUARINI, Sung Won JUN, Vanessa PENA, Errol Antonio C. SANCHEZ, Benjamin COLOMBEAU, Michael CHUDZIK, Bingxi WOOD, Nam Sung KIM
  • Publication number: 20160315176
    Abstract: A method for forming a three dimensional device. The method may include directing ions to an end surface of an extension region of a fin structure, the fin structure extending perpendicularly from a substrate plane and having a fin axis parallel to the substrate plane, wherein the ions have trajectories extending in a plane perpendicular to the substrate plane and parallel to the fin axis, wherein a portion of the fin structure is covered by a gate structure defining a channel region, and wherein the end surface is not covered by the gate structure.
    Type: Application
    Filed: June 19, 2015
    Publication date: October 27, 2016
    Inventors: Shiyu Sun, Naomi Yoshida, Benjamin Colombeau, Hans-Joachim L. Gossmann
  • Publication number: 20160315177
    Abstract: A method of forming an asymmetrical three dimensional semiconductor device. The method may include providing a fin structure extending perpendicularly from a substrate plane and having a fin axis parallel to the substrate plane, wherein a portion of the fin structure is covered by a gate structure defining a channel region, and wherein the fin structure comprises a first end surface not covered by the gate structure and second end surface not covered by the gate structure. The method may further include directing ions in a fin treatment to the fin structure, wherein the fin treatment comprises a first treatment of the first end surface and a second treatment of the second end surface different from the first treatment.
    Type: Application
    Filed: September 18, 2015
    Publication date: October 27, 2016
    Inventors: Shiyu Sun, Naomi Yoshida, Benjamin Colombeau, Hans-Joachim L. Gossmann
  • Patent number: 9460920
    Abstract: Embodiments described herein generally relate to methods and apparatus for horizontal gate all around (hGAA) isolation. A superlattice structure comprising different materials arranged in an alternatingly stacked formation may be formed on a substrate. The different materials may be silicon containing materials and one or more III/V materials. In one embodiment, at least one of the layers of the superlattice structure may be oxidized to form a buried oxide layer adjacent the substrate.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: October 4, 2016
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Shiyu Sun, Naomi Yoshida, Theresa Kramer Guarini, Sung Won Jun, Benjamin Colombeau, Michael Chudzik
  • Patent number: 9455196
    Abstract: A method of processing a workpiece to create a doped fin structure is disclosed. A portion of the workpiece is subjected to a pre-amorphizing implant to create an amorphized region. This amorphized region is then implanted with dopant species, at an implant energy and dose so that the dopant species are contained within the amorphized region. The doped amorphized region is then subjected to a laser melt anneal which crystallizes the amorphized region. The dopant profile is box-like, and the dopant is confined to the previously amorphized region.
    Type: Grant
    Filed: November 6, 2015
    Date of Patent: September 27, 2016
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Nilay A. Pradhan, Benjamin Colombeau, Hans-Joachim L. Gossmann
  • Patent number: 9396902
    Abstract: In one embodiment, a method for generating an ion beam having gallium ions includes providing at least a portion of a gallium compound target in a plasma chamber, the gallium compound target comprising gallium and at least one additional element. The method also includes initiating a plasma in the plasma chamber using at least one gaseous species and providing a source of gaseous etchant species to react with the gallium compound target to form a volatile gallium species.
    Type: Grant
    Filed: May 22, 2012
    Date of Patent: July 19, 2016
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Costel Biloiu, Craig R. Chaney, Neil J. Bassom, Benjamin Colombeau, Dennis P. Rodier
  • Publication number: 20160133523
    Abstract: A method of processing a workpiece to create a doped fin structure is disclosed. A portion of the workpiece is subjected to a pre-amorphizing implant to create an amorphized region. This amorphized region is then implanted with dopant species, at an implant energy and dose so that the dopant species are contained within the amorphized region. The doped amorphized region is then subjected to a laser melt anneal which crystallizes the amorphized region. The dopant profile is box-like, and the dopant is confined to the previously amorphized region.
    Type: Application
    Filed: November 6, 2015
    Publication date: May 12, 2016
    Inventors: Nilay A. Pradhan, Benjamin Colombeau, Hans-Joachim L. Gossmann
  • Patent number: 9337314
    Abstract: A method to selectively process a three dimensional device, comprising providing a substrate having a first surface that extends horizontally, the substrate comprising a structure containing a second surface that extends vertically from the first surface; providing a film on the substrate, the film comprising carbon species; and etching a selected portion of the film by exposing the selected portion of the film to an etchant containing hydrogen species, where the etchant excludes oxygen species and fluorine species.
    Type: Grant
    Filed: December 11, 2013
    Date of Patent: May 10, 2016
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Nilay A. Pradhan, Benjamin Colombeau, Naushad K. Variam, Mandar B. Pandit, Christopher Dennis Bencher, Adam Brand
  • Publication number: 20150364325
    Abstract: A method of doping a compound semiconductor substrate includes: setting a first substrate temperature for the compound semiconductor substrate in a first temperature range; implanting a dopant species into the compound semiconductor substrate at a first ion dose at the first substrate temperature; and annealing the compound semiconductor substrate after the implanting the ions. In conjunction with the annealing, the first ion dose is effective to generate a first dopant activation in the first temperature range higher than a second dopant activation resulting from implantation of the first ion dose at a second substrate temperature below the first temperature range, and is higher than a third dopant activation resulting from implantation of the first ion dose at a third substrate temperature above the first temperature range.
    Type: Application
    Filed: June 17, 2015
    Publication date: December 17, 2015
    Inventors: Christopher R. Hatem, Benjamin Colombeau, Kevin Jones, Aaron Lind
  • Patent number: 8999800
    Abstract: In one embodiment a method of forming low contact resistance in a substrate includes forming a silicide layer on the substrate, the silicide layer and substrate defining an interface therebetween in a source/drain region, and performing a hot implant of a dopant species into the silicide layer while the substrate is at a substrate temperature greater than 150° C., where the hot implant is effective to generate an activated dopant layer containing the dopant species, and the activated dopant layer extends from the interface into the source/drain region.
    Type: Grant
    Filed: June 19, 2013
    Date of Patent: April 7, 2015
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Fareen Adeni Khaja, Benjamin Colombeau
  • Patent number: 8860142
    Abstract: A method (and semiconductor device) of fabricating a semiconductor device utilizes a thermal proximity correction (TPC) technique to reduce the impact of thermal variations during anneal. Prior to actual fabrication, a location of interest (e.g., a transistor) within an integrated circuit design is determined and an effective thermal area around the location is defined. Thermal properties of structures intended to be fabricated within this area are used to calculate an estimated temperature that would be achieved at the location of interest from a given anneal process. If the estimated temperature is below or above a predetermined target temperature (or range), TPC is performed. Various TPC techniques may be performed, such as the addition of dummy cells and/or changing dimensions of the structure to be fabricated at the location of interest (resulting in an modified thermally corrected design, to suppress local variations in device performance caused by thermal variations during anneal.
    Type: Grant
    Filed: October 10, 2012
    Date of Patent: October 14, 2014
    Assignee: Globalfoundries Singapore Pte. Ltd.
    Inventors: Debora Chyiu Hyia Poon, Alex K H See, Francis Benistant, Benjamin Colombeau, Yun Ling Tan, Mei Sheng Zhou, Liang Choo Hsia
  • Publication number: 20140162442
    Abstract: In one embodiment a method of forming low contact resistance in a substrate includes forming a silicide layer on the substrate, the silicide layer and substrate defining an interface therebetween in a source/drain region, and performing a hot implant of a dopant species into the silicide layer while the substrate is at a substrate temperature greater than 150° C., where the hot implant is effective to generate an activated dopant layer containing the dopant species, and the activated dopant layer extends from the interface into the source/drain region.
    Type: Application
    Filed: June 19, 2013
    Publication date: June 12, 2014
    Inventors: Fareen Adeni Khaja, Benjamin Colombeau
  • Publication number: 20140162414
    Abstract: A method to selectively process a three dimensional device, comprising providing a substrate having a first surface that extends horizontally, the substrate comprising a structure containing a second surface that extends vertically from the first surface; providing a film on the substrate, the film comprising carbon species; and etching a selected portion of the film by exposing the selected portion of the film to an etchant containing hydrogen species, where the etchant excludes oxygen species and fluorine species.
    Type: Application
    Filed: December 11, 2013
    Publication date: June 12, 2014
    Applicant: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Nilay A. Pradhan, Benjamin Colombeau, Naushad K. Variam, Mandar B. Pandit, Christopher Dennis Bencher, Adam Brand
  • Patent number: 8722431
    Abstract: A method of forming a FinFET device. The method may include providing a substrate having a single crystalline region, heating the substrate to a substrate temperature effective for dynamically removing implant damage during ion implantation, implanting ions into the substrate while the substrate is maintained at the substrate temperature, and patterning the single crystalline region so as to form a single crystalline fin.
    Type: Grant
    Filed: March 22, 2012
    Date of Patent: May 13, 2014
    Inventors: Nilay Anil Pradhan, Stanislav S. Todorov, Kurt Decker-Lucke, Klaus Petry, Benjamin Colombeau, Baonian Guo