Patents by Inventor Benjamin Colombeau

Benjamin Colombeau has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130313971
    Abstract: In one embodiment, a method for generating an ion beam having gallium ions includes providing at least a portion of a gallium compound target in a plasma chamber, the gallium compound target comprising gallium and at least one additional element. The method also includes initiating a plasma in the plasma chamber using at least one gaseous species and providing a source of gaseous etchant species to react with the gallium compound target to form a volatile gallium species.
    Type: Application
    Filed: May 22, 2012
    Publication date: November 28, 2013
    Applicant: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
    Inventors: Costel Biloiu, Craig R. Chaney, Neil J. Bassom, Benjamin Colombeau, Dennis P. Rodier
  • Publication number: 20130252349
    Abstract: A method of forming a FinFET device. The method may include providing a substrate having a single crystalline region, heating the substrate to a substrate temperature effective for dynamically removing implant damage during ion implantation, implanting ions into the substrate while the substrate is maintained at the substrate temperature, and patterning the single crystalline region so as to form a single crystalline fin.
    Type: Application
    Filed: March 22, 2012
    Publication date: September 26, 2013
    Applicant: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Nilay Anil Pradhan, Stanislav S. Todorov, Kurt Decker-Lucke, Klaus Petry, Benjamin Colombeau, Baonian Guo
  • Patent number: 8354321
    Abstract: A transistor which includes halo regions disposed in a substrate adjacent to opposing sides of the gate. The halo regions have upper and lower regions. The upper region is a crystalline region with excess vacancies and the lower region is an amorphous region. Source/drain diffusion regions are disposed in the halo regions. The source/drain diffusion regions overlap the upper and lower halo regions. This architecture offers the minimal extension resistance as well as minimum lateral diffusion for better CMOS device scaling.
    Type: Grant
    Filed: October 19, 2011
    Date of Patent: January 15, 2013
    Assignees: GLOBALFOUNDRIES Singapore Pte. Ltd., National University of Singapore
    Inventors: Benjamin Colombeau, Sai Hooi Yeong, Francis Benistant, Bangun Indajang, Lap Chan
  • Patent number: 8293544
    Abstract: A method (and semiconductor device) of fabricating a semiconductor device utilizes a thermal proximity correction (TPC) technique to reduce the impact of thermal variations during anneal. Prior to actual fabrication, a location of interest (e.g., a transistor) within an integrated circuit design is determined and an effective thermal area around the location is defined. Thermal properties of structures intended to be fabricated within this area are used to calculate an estimated temperature that would be achieved at the location of interest from a given anneal process. If the estimated temperature is below or above a predetermined target temperature (or range), TPC is performed. Various TPC techniques may be performed, such as the addition of dummy cells and/or changing dimensions of the structure to be fabricated at the location of interest (resulting in an modified thermally corrected design, to suppress local variations in device performance caused by thermal variations during anneal.
    Type: Grant
    Filed: July 28, 2008
    Date of Patent: October 23, 2012
    Assignee: GlobalFoundries Singapore Pte. Ltd.
    Inventors: Debora Chyiu Hyia Poon, Alex Kh See, Francis Benistant, Benjamin Colombeau, Yun Ling Tan, Mei Sheng Zhou, Liang Choo Hsia
  • Publication number: 20120034745
    Abstract: A transistor which includes halo regions disposed in a substrate adjacent to opposing sides of the gate. The halo regions have upper and lower regions. The upper region is a crystalline region with excess vacancies and the lower region is an amorphous region. Source/drain diffusion regions are disposed in the halo regions. The source/drain diffusion regions overlap the upper and lower halo regions. This architecture offers the minimal extension resistance as well as minimum lateral diffusion for better CMOS device scaling.
    Type: Application
    Filed: October 19, 2011
    Publication date: February 9, 2012
    Applicant: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Benjamin COLOMBEAU, Sai Hooi YEONG, Francis BENISTANT, Bangun INDAJANG, Lap CHAN
  • Patent number: 8101528
    Abstract: A method of processing to a substrate while minimizing cost and manufacturing time is disclosed. The implantation of the source and drain regions of a semiconductor device are performed at low temperatures, such as below 273° K. This low temperature implant reduces the structural damage caused by the impacting ions. Subsequently, the implanted substrate is activated using faster forms of annealing. By performing the implant at low temperatures, the damage to the substrate is reduced, thereby allowing a fast anneal to be used to activate the dopants, while eliminating the majority of the defects and damage. Fast annealing is less expensive than conventional furnace annealing, and can achieve higher throughput at lower costs.
    Type: Grant
    Filed: August 4, 2010
    Date of Patent: January 24, 2012
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Christopher R. Hatem, Benjamin Colombeau
  • Patent number: 8101487
    Abstract: A method for fabricating a semiconductor device is presented. The method includes providing a substrate and forming a gate stack over the substrate. A first laser processing to form vacancy rich regions within the substrate on opposing sides of the gate stack is performed. The vacancy rich regions have a first depth from a surface of the substrate. A first implant causing end of range defect regions to be formed on opposing sides of the gate stack at a second depth from the surface of the substrate is also carried out, wherein the first depth is proximate to the second depth.
    Type: Grant
    Filed: May 15, 2009
    Date of Patent: January 24, 2012
    Assignees: Nanyang Technological University, National University of Singapore, GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Dexter Xueming Tan, Benjamin Colombeau, Clark Kuang Kian Ong, Sai Hooi Yeong, Chee Mang Ng, Kin Leong Pey
  • Patent number: 8053340
    Abstract: A transistor which includes halo regions disposed in a substrate adjacent to opposing sides of the gate. The halo regions have upper and lower regions. The upper region is a crystalline region with excess vacancies and the lower region is an amorphous region. Source/drain diffusion regions are disposed in the halo regions. The source/drain diffusion regions overlap the upper and lower halo regions. This architecture offers the minimal extension resistance as well as minimum lateral diffusion for better CMOS device scaling.
    Type: Grant
    Filed: September 27, 2007
    Date of Patent: November 8, 2011
    Assignees: National University of Singapore, Globalfoundries Singapore Pte. Ltd.
    Inventors: Benjamin Colombeau, Sai Hooi Yeong, Francis Benistant, Bangun Indajang, Lap Chan
  • Patent number: 8012843
    Abstract: An improved method of performing pocket or halo implants is disclosed. The amount of damage and defects created by the halo implant degrades the performance of the semiconductor device, by increasing leakage current, decreasing the noise margin and increasing the minimum gate voltage. The halo or packet implant is performed at cold temperature, which decreases the damage caused to the crystalline structure and improves the amorphization of the crystal. The use of cold temperature also allows the use of lighter elements for the halo implant, such as boron or phosphorus.
    Type: Grant
    Filed: August 5, 2010
    Date of Patent: September 6, 2011
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Christopher R. Hatem, Benjamin Colombeau, Thirumal Thanigaivelan, Kyu-Ha Shim, Dennis Rodier
  • Publication number: 20110034014
    Abstract: A method of applying a silicide to a substrate while minimizing adverse effects, such as lateral diffusion of metal or “piping” is disclosed. The implantation of the source and drain regions of a semiconductor device are performed at cold temperatures, such as below 0° C. This cold implant reduces the structural damage caused by the impacting ions. Subsequently, a silicide layer is applied, and due to the reduced structural damage, metal diffusion and piping into the substrate is lessened. In some embodiments, an amorphization implant is performed after the implantation of dopants, but prior to the application of the silicide. By performing this pre-silicide implant at cold temperatures, similar results can be obtained.
    Type: Application
    Filed: August 4, 2010
    Publication date: February 10, 2011
    Applicant: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
    Inventors: Christopher R. Hatem, Benjamin Colombeau, Thirumal Thanigaivelan, Kyu-Ha Shim, Jay T. Scheuer
  • Publication number: 20110034013
    Abstract: A method of processing to a substrate while minimizing cost and manufacturing time is disclosed. The implantation of the source and drain regions of a semiconductor device are performed at low temperatures, such as below 273° K. This low temperature implant reduces the structural damage caused by the impacting ions. Subsequently, the implanted substrate is activated using faster forms of annealing. By performing the implant at low temperatures, the damage to the substrate is reduced, thereby allowing a fast anneal to be used to activate the dopants, while eliminating the majority of the defects and damage. Fast annealing is less expensive than conventional furnace annealing, and can achieve higher throughput at lower costs.
    Type: Application
    Filed: August 4, 2010
    Publication date: February 10, 2011
    Applicant: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
    Inventors: Christopher R. Hatem, Benjamin Colombeau
  • Publication number: 20110033998
    Abstract: An improved method of performing pocket or halo implants is disclosed. The amount of damage and defects created by the halo implant degrades the performance of the semiconductor device, by increasing leakage current, decreasing the noise margin and increasing the minimum gate voltage. The halo or packet implant is performed at cold temperature, which decreases the damage caused to the crystalline structure and improves the amorphization of the crystal. The use of cold temperature also allows the use of lighter elements for the halo implant, such as boron or phosphorus.
    Type: Application
    Filed: August 5, 2010
    Publication date: February 10, 2011
    Applicant: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
    Inventors: Christopher R. Hatem, Benjamin Colombeau, Thirumal Thanigaivelan, Kyu-Ha Shim, Dennis Rodier
  • Publication number: 20100019329
    Abstract: A method (and semiconductor device) of fabricating a semiconductor device utilizes a thermal proximity correction (TPC) technique to reduce the impact of thermal variations during anneal. Prior to actual fabrication, a location of interest (e.g., a transistor) within an integrated circuit design is determined and an effective thermal area around the location is defined. Thermal properties of structures intended to be fabricated within this area are used to calculate an estimated temperature that would be achieved at the location of interest from a given anneal process. If the estimated temperature is below or above a predetermined target temperature (or range), TPC is performed. Various TPC techniques may be performed, such as the addition of dummy cells and/or changing dimensions of the structure to be fabricated at the location of interest (resulting in an modified thermally corrected design, to suppress local variations in device performance caused by thermal variations during anneal.
    Type: Application
    Filed: July 28, 2008
    Publication date: January 28, 2010
    Inventors: Debora Chyiu Hyia Poon, Alex KH See, Francis Benistant, Benjamin Colombeau, Yun Ling Tan, Mei Sheng Zhou, Liang Choo Hsia
  • Publication number: 20090286373
    Abstract: A method for fabricating a semiconductor device is presented. The method includes providing a substrate and forming a gate stack over the substrate. A first laser processing to form vacancy rich regions within the substrate on opposing sides of the gate stack is performed. The vacancy rich regions have a first depth from a surface of the substrate. A first implant causing end of range defect regions to be formed on opposing sides of the gate stack at a second depth from the surface of the substrate is also carried out, wherein the first depth is proximate to the second depth.
    Type: Application
    Filed: May 15, 2009
    Publication date: November 19, 2009
    Applicants: CHARTERED SEMICONDUCTOR MANUFACTURING, LTD., NANYANG TECHNOLOGICAL UNIVERSITY, NATIONAL UNIVERSITY OF SINGAPORE
    Inventors: Dexter Xueming TAN, Benjamin COLOMBEAU, Clark Kuang Kian ONG, Sai Hooi YEONG, Chee Mang NG, Kin Leong PEY
  • Publication number: 20090087971
    Abstract: A transistor which includes halo regions disposed in a substrate adjacent to opposing sides of the gate. The halo regions have upper and lower regions. The upper region is a crystalline region with excess vacancies and the lower region is an amorphous region. Source/drain diffusion regions are disposed in the halo regions. The source/drain diffusion regions overlap the upper and lower halo regions. This architecture offers the minimal extension resistance as well as minimum lateral diffusion for better CMOS device scaling.
    Type: Application
    Filed: September 27, 2007
    Publication date: April 2, 2009
    Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.
    Inventors: Benjamin COLOMBEAU, Sai Hooi YEONG, Francis BENISTANT, Bangun INDAJANG, Lap CHAN