Abstract: A method for fabricating semiconductor wafers comprises creating a semiconductor wafer having a plurality of wide copper wires and a plurality of narrow copper wires embedded in a dielectric insulator. The width of each wide copper wire is greater than a cutoff value and each narrow copper is less than the cutoff value. An optical pass through layer is deposited over a top surface of the wafer and a photo-resist layer is deposited over the optical pass through layer. The wafer is exposed to a light source to selectively remove photo-resist, forming a self-aligned pattern where photo-resist only remains in areas above wide copper wires. The self-aligned pattern is transferred to the optical pass through layer and the remaining photo-resist is removed. The wafer is chemically etched to remove the narrow copper wires, defining narrow gaps in the dielectric insulator. The wafer is metallized with non-copper metal, forming narrow non-copper metal wires.

Abstract: A method of forming an interconnect to an electrical device is provided. The structure produced by the method may include a plurality of metal lines in a region of a substrate positioned in an array of metal lines all having parallel lengths; and a plurality of air gaps between the metal lines in a same level as the metal lines, wherein an air gap is present between each set of adjacent metal lines. A plurality of interconnects may be present in electrical communication with said plurality of metal lines, wherein an exclusion zone for said plurality of interconnects is not present in said array of metal lines.

Abstract: An electrical device includes a plurality of metal lines in a region of a substrate positioned in an array of metal lines all having parallel lengths, and a plurality of air gaps between the metal lines in a same level as the metal lines, wherein an air gap is present between each set of adjacent metal lines. A plurality of interconnects may be present in electrical communication with said plurality of metal lines, wherein an exclusion zone for said plurality of interconnects is not present in said array of metal lines.

Abstract: A method for manufacturing a semiconductor device includes forming a plurality of trenches in a dielectric layer, wherein the plurality of trenches each comprise a rounded surface, depositing a liner layer on the rounded surface of each of plurality of trenches, and depositing a conductive layer on the liner layer in each of the plurality of trenches, wherein the conductive layer and the liner layer form a plurality of interconnects, and each of the plurality of interconnects has a cylindrical shape.

Abstract: A semiconductor device and method for forming the semiconductor device are described. The method includes recessing a device pad to below a top surface of an interconnect layer and depositing a cap in the recess over the device pad. A topography assist layer is formed over each of at least one alignment mark using a selective deposition process that deposits material on conductive material of the at least one alignment mark selective to the metal nitride of the device pad such that a top surface of the topography assist feature is higher than a top surface of the cap. Device layers are deposited conformally over the interconnect layer such that the topography assist layer causes a topographical feature in a top surface of the deposited device layers, the topographical feature being vertically aligned with the topography assist layer. The device pad is aligned according to the topographical feature.

Abstract: A method of forming a self-aligned pattern of vias in a semiconductor device comprises etching a pattern of lines that contain notches that are narrower than other parts of the line. Thereafter, vias are created where the notches are located. The locations of the vias are such that the effect of blown-out areas is minimized. Thereafter, the lines are etched and the vias and line areas are filled. The layers are planarized such that the metal fill is level with a surrounding ultra-low-k dielectric. Additional metal layers, lines, and vias can be created. Other embodiments are also described herein.

Abstract: Extreme ultraviolet (EUV) lithographic patterning methods are provided which implement a surface-hardened EUV resist mask to pattern features in multiple layers. A layer of EUV resist material is formed on a substrate. An EUV resist mask is formed by exposing and developing the layer of EUV resist material. A surface-hardened EUV resist mask is formed by applying a surface treatment to an upper surface of the EUV resist mask to form an etch-resistant layer that is embedded in the upper surface of the EUV resist mask. At least one layer of the substrate is patterned using the surface-hardened EUV resist mask. The surface treatment can be implemented using a neutral atom beam (NAB) process which is configured to implant a chemical or metallic species into the upper surface of the EUV resist mask to form the etch-resistant layer.

Abstract: Methods and systems of navigating within a virtual environment are described. In an example, a processor may generate a portal that includes a set of portal boundaries. The processor may display the portal within a first scene of the virtual environment being displayed on a device. The processor may display a second scene of the virtual environment within the portal boundaries. The processor may receive sensor data indicating a movement of a motion controller. The processor may reposition the portal and the second scene in the first scene based on the sensor data, wherein the first scene remains stationary on the device during the reposition of the portal and the second scene. The processor may translate a location of the portal within the first scene to move the portal towards a user of the device until the second scene replaces the first scene being displayed on the device.

Abstract: A semiconductor device and method for forming the semiconductor device are described. The method includes recessing a device pad to below a top surface of an interconnect layer and depositing a cap in the recess over the device pad. A topography assist layer is formed over each of at least one alignment mark using a selective deposition process that deposits material on conductive material of the at least one alignment mark selective to the metal nitride of the device pad such that a top surface of the topography assist feature is higher than a top surface of the cap. Device layers are deposited conformally over the interconnect layer such that the topography assist layer causes a topographical feature in a top surface of the deposited device layers, the topographical feature being vertically aligned with the topography assist layer. The device pad is aligned according to the topographical feature.

Abstract: A station for compliance testing of unmanned vehicles comprises a dedicated area for acceptance of an unmanned vehicle. The dedicated area is configured for permitting the unmanned vehicle to be in a first inspection position. The station further comprises a transmitter. The transmitter is directed towards the dedicated area. The transmitter is configured to instruct the unmanned vehicle to perform a behavior. The station further comprises a sensor. The sensor is directed towards the dedicated area. The sensor is configured to detect a non-compliance of the unmanned vehicle. The detected non-compliance is in response to the instructed performed behavior of the unmanned vehicle.

Abstract: An unmanned vehicle is identified. One or more specifications of the unmanned vehicle are retrieved in response to the identification. A first characteristic of the unmanned vehicle is observed. The observed first characteristic is compared to the retrieved specifications. A compliance standard of the unmanned vehicle is determined. The determination is based on the comparison.

Abstract: A system for a touch screen interface that includes a coating including a plurality of a touch activated microchips; and a projector for projecting a light image onto the coating that is applied to a touch screen substrate. The system also includes an image calibrator that calibrates touch activated microchips in the coating to features of the light image projected onto the coating. The system further includes a receiver for receiving signal from the touch activated microchips when said feature of the light image is activated.

Abstract: A system for a touch screen interface that includes a coating including a plurality of a touch activated microchips; and a projector for projecting a light image onto the coating that is applied to a touch screen substrate. The system also includes an image calibrator that calibrates touch activated microchips in the coating to features of the light image projected onto the coating. The system further includes a receiver for receiving signal from the touch activated microchips when said feature of the light image is activated.

Abstract: A method of forming via openings that includes forming sidewall spacers on a plurality of mandrels that are overlying a hardmask layer that is present on an interlevel dielectric layer. Etching the hardmask layer using a portion of the sidewall spacers and the plurality of mandrels to form a first pillar of hardmask material. The interlevel dielectric layer is etched using the first pillar of hardmask material as a mask to define a first via opening. The plurality of mandrels are removed. The hardmask layer is etched using the spacers to define a second pillar of hardmask material. The interlevel dielectric layer is etched using the second pillar of hardmask material to provide a second via opening.

Abstract: A method for forming a conductor includes forming trenches in an insulator layer. An alloy layer is deposited in the trenches. The alloy layer includes a conductor material and a barrier material. The alloy layer is annealed to form a barrier layer on the insulator layer and to purify the alloy layer into a conductor layer, such that the barrier material in the alloy layer is driven to an interface between the alloy layer and the insulator layer.

Abstract: Methods for orientation and placement of computing devices are presented. Aspects include applying, using a viscous material application device, a layer of a viscous material to a surface of an object, the layer of the viscous material having a plurality of computing devices disposed therein. The layer of the viscous material is allowed to dry during a drying period, wherein each of the plurality of computing devices comprises a first material applied to a first side of each of the plurality of computing devices, the first material having a first characteristic. And each of the plurality of computing devices comprises a second material applied to a second side of each of the plurality of computing devices, the second material having a second characteristic. And each of the plurality of computing devices is configured to perform, during the drying period, a self-orientation operation.

Abstract: A method of forming via openings that includes forming sidewall spacers on a plurality of mandrels that are overlying a hardmask layer that is present on an interlevel dielectric layer. Etching the hardmask layer using a portion of the sidewall spacers and the plurality of mandrels to form a first pillar of hardmask material. The interlevel dielectric layer is etched using the first pillar of hardmask material as a mask to define a first via opening. The plurality of mandrels are removed. The hardmask layer is etched using the spacers to define a second pillar of hardmask material. The interlevel dielectric layer is etched using the second pillar of hardmask material to provide a second via opening.

Abstract: A field emission transistor includes a gate, a fold over emitter, and fold over collector. The emitter and the collector are separated from the gate by a void and are separated from a gate contact by gate contact dielectric. The void may be a vacuum, ambient air, or a gas. Respective ends of the emitter and the collector are separated by a gap. Electrons are drawn across gap from the emitter to the collector by an electrostatic field created when a voltage is applied to the gate. The emitter and collector include a first conductive portion substantially parallel with gate and a second conductive portion substantially perpendicular with gate. The second conductive portion may be formed by bending a segment of the first conductive portion. The second conductive portion is folded inward from the first conductive portion towards the gate. Respective second conductive portions are generally aligned.

Abstract: An interconnect for a semiconductor device includes an insulator layer having a trench. A barrier layer is formed on a surface of the insulator layer in the trench. An elemental cobalt conductor is formed on the barrier layer.

Abstract: Techniques for leveraging the capabilities of wearable mobile technology to collect data and to provide real-time feedback to an orator about his/her performance and/or audience interaction are provided. In one aspect, a method for providing real-time feedback to a speaker making a presentation to an audience includes the steps of: collecting real-time data from the speaker during the presentation, wherein the data is collected via a mobile device worn by the speaker; analyzing the real-time data collected from the speaker to determine whether corrective action is needed to improve performance; and generating a real-time alert to the speaker suggesting the corrective action if the real-time data indicates that corrective action is needed to improve performance, otherwise continuing to collect data from the speaker in real-time. Real-time data may also be collected from members of the audience and/or from other speakers (if present) via wearable mobile devices.