Abstract: A method of forming a metal-insulator-metal capacitor. A substrate is provided and then a first dielectric layer is formed over the substrate. The first dielectric layer is patterned to form a first opening for forming a desired lower electrode and a second opening for forming a desired conductive line. A first metallic layer conformal to the exposed surface of the first opening and completely filling the second opening is formed. A conformal capacitor dielectric layer is formed over the first metallic layer and then a second dielectric layer is formed over the capacitor dielectric layer. The second dielectric layer is patterned to form a third opening above the first opening and a fourth opening above the second opening. The third opening exposes a portion of the capacitor dielectric layer and the fourth opening exposes a portion of the first metallic layer. Finally, a second metallic layer that completely fills the third opening and the fourth opening is formed.

Abstract: A method of forming the lower electrode of a capacitor capable of withstanding the flushing force produced by a cleaning agent. A lower electrode having a rectangular profile when viewed from the top is provided. The lower electrode is bounded by a pair of ends and a pair of sides. The ends and the sides are linked together. The ends have a wedge shape. The sides have edges that cave in towards the center, thereby forming a recess region between the sides. A flushing operation is carried out using a cleaning solution. The cleaning solution flows from one end of the electrode to the other end along the sides.

Abstract: A method of forming the lower electrode of a capacitor capable of withstanding the flushing force produced by a cleaning agent. A lower electrode having a rectangular profile when viewed from the top is provided. The lower electrode is bounded by a pair of ends and a pair of sides. The ends and the sides are linked together. The ends have a wedge shape. The sides have edges that cave in towards the center, thereby forming a recess region between the sides. A flushing operation is carried out using a cleaning solution. The cleaning solution flows from one end of the electrode to the other end along the sides.

Abstract: A self-aligned photolithographic process for forming silicon-on-insulator devices. A substrate made from a transparent insulating material is provided. Conductive devices made from a non-transparent material, material layers made from transparent material and a photoresist layer are formed over the substrate. Transparent substrate areas having conductive devices thereon are non-transparent regions and transparent substrate areas having no conductive devices thereon are transparent regions. Using the substrate as a mask, a contact exposure of the photoresist material is conducted to form a patterned photoresist layer by shining light through the transparent substrate regions.

Abstract: An optical proximity correction algorithm using a computer aided design (CAD) system to eliminate the optical proximity effect when transferring the pattern of a photomask onto a wafer. The algorithm comprises, 1. providing an original layout to be formed on the semiconductor wafer, 2. analyzing the image condition of the original layout by the operation of a reverse Fourier transformation method on the original layout, and 3. creating a modified layout to be formed on the photomask according to the image condition.

Abstract: A multiphase phase shifting mask is described. The multiphase phase shifting mask comprises a transparent substrate; a lightly transparent material shifting an exposure light by about 180° in phase on the transparent substrate, a first group of transparent hole features shifting the exposure light by about 90° in phase on the transparent substrate, a second group of transparent hole features shifting the exposure light by about 270° in phase on the transparent substrate, and at least one transparent hole feature shifting the exposure light by about 0° in phase on the transparent substrate. The first and the second groups of transparent hole features are alternatively arranged with each other. The transparent hole feature shifting the exposure light by about 0° in phase is spaced apart from but substantially surrounded by the first and the second groups of transparent hole features.

Abstract: A method for forming different patterns using one phase shifting mask. The phase shifting mask has a bit line contact pattern and a node contact pattern thereon. The exposure pattern is changed by using different defocus conditions. In a first defocus situation, the bit line contact pattern and the node contact pattern of the PSM are simultaneously transferred to a photoresist layer. However, in a second defocus situation, only the bit line contact pattern is transferred to the photoresist layer. A phase shifting mask thus can be used in two different photolithography processes.

Abstract: This invention provides a method of forming a multi-layer photo mask on a photo mask substrate. A first transparent layer comprising at least one vertical side wall is formed on at least one predetermined area of the photo mask substrate. A first opaque spacer is formed around the vertical side wall of the first transparent layer, and the top side of the first spacer is approximately leveled off with the upper surface of the first transparent layer. An external transparent layer is formed on the photo mask substrate and outside the predetermined area, and the upper surface of the external transparent layer is leveled off with that of the first transparent layer. So the first transparent layer and the external transparent layer form a first photo mask layer. A second transparent layer comprising at least one vertical side wall is formed on at least one predetermined area of the first photo mask layer.

Abstract: A bi-focus exposure process for exposing a wafer through a mask is described. The mask comprises a plurality of first transparent hole features having a phase shift of about 0 degrees and a plurality of second transparent hole features having a phase shift of about 180 degrees, the first and the second hole features are alternatively located on a transparent substrate, and each of the hole features is substantially and adjacently surrounded by a lightly transparent material having a phase shift of about 90 degrees on the transparent substrate. The patterns of the first hole features are printed on the wafer by exposing the wafer through the mask at a first defocus smaller than 0 &mgr;m defocus. The patterns of the second hole features are printed on the wafer by exposing the wafer through the mask at a second defocus smaller than 0 &mgr;m defocus.

Abstract: A method of fabricating a via plug for self-aligned interconnects is provided. The method features initially forming a polysilicon buffer layer and a silicon oxide layer in sequence on an inter-polysilicon dielectric (IPD) layer, followed by forming a trench opening in the silicon oxide layer. The trench opening is then filled with a metal line. A patterned photoresist layer is formed on the silicon oxide layer to form a photoresist opening which exposes a part of the metal line. The exposed part of the metal line and a part of the polysilicon buffer layer are removed to expose a part of the IPD layer, followed by removing the photoresist layer and the silicon oxide layer. With the polysilicon buffer layer and the metal line serving as a mask, the exposed part of the IPD layer is removed to form a via opening. The via opening is then filled with a polysilicon layer which is formed on the polysilicon buffer layer and the metal line.

Abstract: The present invention provides a method of forming a node contact hole on a semiconductor wafer. The semiconductor wafer comprises a silicon substrate, a first dielectric layer positioned on the silicon substrate, two bit lines positioned on the first dielectric layer which form a first groove between the two bit lines and the surface of the first dielectric layer, and a second dielectric layer positioned on each of the two bit lines. A lithographic process is performed to form a photoresist layer on the second dielectric layer with at least one second groove extending down to the second dielectric layer wherein the second groove is positioned above the first groove and is perpendicular to the first groove. An etching process is performed along the second groove of the photoresist layer to remove the second dielectric layer and the first dielectric layer under the second groove down to the surface of the silicon substrate so as to approximately form the node contact hole.

Abstract: A low duty ratio mask has a plurality of masked layout patterns and a plurality of alternating scattering bars placed next to edges of each masked layout pattern. A phase shift of 180° exists between the alternating scattering bars and the corresponding masked layout pattern.

Abstract: The present invention relates to a method of forming a phase shift mask on a mask substrate. This method comprises sequentially forming a phase shifter layer and a shield layer on the mask substrate, forming a photo-resist layer on a predetermined region of the shield layer, wherein the periphery of the photo-resist layer comprises at least one vertical side-wall, and forming a deposition layer uniformly on the photo-resist layer and the shield layer surrounding the photo-resist layer. Next, silylanizing the deposition layer. Next, performing an anisotropic etching process to remove the deposition layer on top of the photo-resist layer and the shield layer surrounding the photo-resist layer, and to partially remove the deposition layer covered on the vertical side-wall of the photo-resist layer so as to form a spacer on the vertical side-wall of the photo-resist layer.

Abstract: This invention provides a method of forming a node contact with self-alignment on a semiconductor wafer. The wafer comprises a substrate, a dielectric layer, and a first and a second bit lines. A first side wall of the first bit line is adjacent to a second side wall of the second bit line and comprises a first region and two second regions adjacent to the first region. The distance between the first region and the second side wall is greater than a predetermined value and the distance between the two second regions and the second side wall is less than the predetermined value. A second insulating layer is formed on the dielectric layer and two bit lines to form a groove over the gap between the first region and the second side wall. A first anisotropic etching is performed to extend the bottom of the groove down to the dielectric layer.

Abstract: A fabrication method for a vertical MOS device is described, in which dopants are implanted in the active region to form, from the bulk to the surface of the wafer respectively, a first doped layer, a second doped layer and a third doped layer. A portion of the isolation structure above the first doped layer is then removed, exposing the sidewalls of the second doped layer and the surface of the third doped layer but still concealing the first doped layer in the substrate. A gate oxide layer is further formed on the sidewalls of the second doped layer and the surface of the third doped layer. Furthermore, a conductive layer is formed at the second doped layer, covering the isolation structure, wherein the second doped layer and the conductive layer are isolated by the gate oxide layer.

Abstract: A method for forming the cylindrical lower electrode of a capacitor includes the steps of providing a semiconductor substrate, and then forming an insulation layer over the substrate. Next, a contact opening is formed in the insulation layer, and then a conductive layer is formed, filling the contact opening and covering the insulation layer. Subsequently, a patterned photoresist layer is formed over the conductive layer. Thereafter, silylated photoresist spacers are formed on the sidewalls of the photoresist layer. Finally, using the spacers as a mask, the photoresist layer and a portion of the conductive layer are etched away to form the cylindrical-shaped lower electrode of a capacitor.

Abstract: A method of forming landing pads for a bit line and a node contact is provided. First, a first dielectric layer is formed on a substrate having a transistor structure thereon. The first dielectric layer is defined and etched in a self-aligned process to form a contact opening to the substrate. A second dielectric layer is formed on the first dielectric layer and is etched back to form a spacer on the opening sidewall. Then, a conductive layer is formed on the first dielectric layer and fills the opening. A bit line is formed by partially removing the conductive layer through a photo-resist mask provided on the conductive layer, wherein the conductive layer filling the opening is left to form a landing pad.

Abstract: An alignment and exposure process that use the same incident beam. A substrate having a photoresist formed on an upper surface of the substrate is provided. At least one alignment mark is located on a bottom surface of the substrate. A mask is located over the photoresist. An incident beam is projected onto a light splitter over the mask, wherein the incident beam is reflected onto the alignment mark to align the mask with the substrate. The first light is split into a transmission light and a reflection light. The transmission light passes through the light splitter and the mask to expose the photoresist and the reflection light is projected onto the alignment mark to dynamically align the mask with the substrate.

Abstract: A method of manufacturing a DRAM capacitor comprises the steps of providing a substrate having a word line, a source/drain region, a bit line and a first insulator layer. A hard mask layer and a second insulator layer are formed on the first insulator layer in sequence. Next, an opening is formed to expose a portion of the first insulator layer by patterning the second insulator layer and the hard mask layer. Thereafter, a spacer is formed on the side wall of the opening and a node contact hole is formed to expose a portion of the source/drain region in the first insulator layer. The second insulator layer is stripped to expose the hard mask layer and a conductive layer is formed over the hard mask layer and fills the node contact hole. A bottom electrode is formed by patterning the conductive layer and a dielectric layer and another conductive layer are formed over the bottom electrode in sequence.

Abstract: A semiconductor fabrication method is provided for forming an opening in a dielectric layer, which can help downsize the critical dimension of the resulting opening through the use of a photoresist layer with silylated sidewall spacers. By this method, the first step is to coat a base photoresist layer over the dielectric layer. Next, a photolithographic process is performed to remove a selected part of the base photoresist layer. Then, a conformational coating process is performed to coat a silylatable photoresist layer over the base photoresist layer to a controlled predefined thickness. Subsequently, a silylation process is performed on the silylatable photoresist layer so as to form a silylated photoresist layer over all the exposed surfaces of the base photoresist layer. After this, a first etching process is performed on the silylated photoresist layer, with the remaining portions of the silylated photoresist layer serving as silylated sidewall spacers on the base photoresist layer.