Abstract: An installation for forming a double-sided photomask includes a first and a second particle sources and a first and a second focusing assemblies positioned on each side of a mechanical stage. The mechanical stage is used for holding a masking plate that requires pattern inscription. The particles generated by the first and the second particle sources are channeled to the first and second focusing assemblies, respectively. Within each focusing assembly, the particle beam is focused to a desired resolution for inscribing a pattern onto each face of the masking plate, thereby forming a double-sided photomask. The installation further includes a controlling unit coupled to the particle sources, the focusing assemblies and the mechanical stage for controlling system operation. In addition, there is a photomask pattern generator coupled to the controlling unit for supplying pattern data to the controlling unit.

Abstract: A photolithography technique. A chip has latitudinal scribe lines and longitudinal scribe lines and also has a plurality of alignment marks. The latitudinal scribe lines and longitudinal scribe lines divide the chip into a plurality of dies. Some dies are effective dies. Alignment marks are located at each intersection of the latitudinal and longitudinal scribe lines. Each shot contains a plurality of dies. A mask having a plurality of mask alignment marks is provided. The mask alignment marks are used for alignment with alignment marks in the chip. The alignment marks of the chip are aligned with the mask alignment marks of the mask. At least three alignment marks close to the effective dies in the shots are selected for detection a focus and focal plane of each shot, so as to level the shot and perform an exposure step on each shot, shot by shot.

Abstract: A method for fabricating a photomask includes forming an anti-reflection layer on a transparent substrate. A transparent layer is formed on the anti-reflection layer. Patterning the transparent layer forms a transparent bar layer so that a portion of the ant-reflection layer is exposed. An opaque layer is formed over the substrate. A polishing process is performed to polish the opaque layer and the transparent bar layer so that a top portion of the transparent bar layer is polished and exposed. An etching back process is performed to remove a portion of the opaque layer so that the anti-reflection layer is exposed and the remains of the opaque layer forms a spacer with uniform thickness on each side of the transparent bar layer. The transparent bar layer is removed by etching so as to form the photomask.

Abstract: A double-alternating phase-shifting mask (PSM) is provided for use in photolithography for pattern definition of contact holes in semiconductor fabrication, which can eliminate the side-lobe effect that would otherwise cause ghost lines in the resulted pattern definition. The double-alternating PSM comprises a quartz substrate and a masked area formed on said quartz substrate with the unmasked areas being defined as contact hole patterns. The masked area includes a first shifter layer formed over said quartz substrate and a second shifter layers formed over said quartz substrate at those positions each substantially in the geometric center of each group of neighboring contact hole patterns.

Abstract: A half-tone phase shifting mask (HTPSM) with a back surface blind border alignment mark includes a shifter layer with a desired pattern on one surface of a transparent substrate, and a light shielding layer with a mark opening on another surface of the transparent substrate. In this case, the light ray passing through the mark opening is partially shielded by the shifter layer so that there is no light amplitude subtraction within the mark opening.

Abstract: A method of fabricating a dual damascene structure is provided comprising forming a photoresist layer on a dielectric layer. A mask including a region that light completely passes over, a region that light partially passes over and a dense region is used for exposure. A development step is carried out to remove the photoresist layer under the region that light completely passes over, to partially remove the photoresist layer under the region that light partially passes over and to leave the photoresist layer under the dense region. The photoresist layer remaining from the forgoing step and the dielectric layer are partially removed to form a via and a trench in the dielectric layer. The via and the trench are filled with metal to form a dual damascene structure.

Abstract: A double photomask includes two complementary pattern layers respectively formed on each surface of a transparent substrate. A full pattern is a combined pattern of these two complementary pattern layers. These two complementary pattern layers are formed separately on the different surfaces. The double-sided photomask also includes a shifter layer for a phase shifting mask.

Abstract: A fabrication process for a multi-layer photomask. A transparent substrate is provided. An anti-reflecting layer is formed on the substrate. First blinding blocks are formed on the anti-reflecting layer by defining a first blinding layer. A transparent layer is formed along the profile of the structure surface described above. Second blinding blocks are formed on the transparent layer between the first blinding blocks by defining a second blinding layer, wherein a part of the transparent layer on the first blocks is exposed.

Abstract: A phase-shifting mask (PSM) is provided for use in a photolithographic process in semiconductor fabrications. The phase-shifting mask includes a quartz plate and a plurality of mask pieces located at predefined locations over said quartz plate. Each of said mask pieces includes a semi-transparent masking layer formed on said quartz plate and a semi-transparent phase-shifting layer formed on the periphery of said semi-transparent masking layer. The phase-shifting mask has the benefits of facilitating auto generation of the mask patterns thereon through computer graphic means and increasing the resolution and contrast of the pattern definition in the photolithographic process.

Abstract: A method for fabricating an alternating phase shifting mask includes a transparent substrate, a number of oblique layers formed on the transparent substrate, and a number of embedded phase shift layers inside the transparent substrate. Then, a photolithography process is applied to form a photoresist layer on the transparent substrate corresponding to a desired pattern and, therefore, exposing a portion of the transparent substrate. Then, an ion implantation process utilizing the photoresist layer as a mask is applied to form the embedded phase shift layers and the photoresist layer is removed after ion implantation. The embedded phase shift layers are formed in alternating positions in the transparent portion between the oblique layers.

Abstract: A method for fabricating crown-shaped a capacitor is provided. The method is comprised of the following steps. First, a dielectric layer is formed on a substrate having a pre-formed field effect transistor, then a contact hole which exposes one of the source/drain regions of the field effect transistor is defined and formed. Then a first conductive layer is formed in the contact hole and on the dielectric layer, a crown-shaped photoresist layer is formed by employing a mask comprising a transmission layer, a partial transmission layer, and a non-transmission layer. Next, the pattern on the photoresist layer is transferred onto the first conductive layer to form a crown-shaped conductive layer. Then, a dielectric film is formed on the top of the crown-shaped conductive layer, and a second conductive layer on the top of the dielectric film.

Abstract: A phase-shifting mask (PSM) structure and a method for fabricating the same are provided. The PSM structure includes a quartz substrate and a shifter layer formed over said quartz substrate, each shifter layer being formed with a first thickness of specific value to serve as the blinding portion of the PSM and a second thickness of specific value to serve as the phase-shifting portion of the PSM. The shifter layer of two different thicknesses can be used to replace the conventional chromium layer to provide the desired blinding and phase shifting effects of the PSM.

Abstract: A method for forming a DRAM capacitor that uses a sacrificial layer to form a gear-teeth mold for producing a storage electrode having a highly increased surface area. The mold in a sacrificial layer is formed by first depositing alternating layers of two different insulating materials on a dielectric layer, and then patterning the sacrificial layer to form an opening using a conventional method. Next, a wet etching operation is performed using an etchant having a high etching selectivity between the two insulating layers. Hence, sunken slots are formed in the insulating layers that have a higher etching rate than its adjacent insulating layers, thus obtaining a gear teeth cross-sectional profile. Finally, the mold in the sacrificial layer is used for forming the storage electrode.

Abstract: A method for forming dual damascene metallic structure that utilizes the formation of a protective photoresist layer at the bottom of a vertical window to prevent damages to a device region in the substrate when subsequent etching operation is carried out to form a horizontal trench pattern. The protective photoresist layer at the bottom of the vertical window is formed by irradiating the photoresist layer with a dose of radiation having energy level insufficient to chemically dissociate the photoactive molecules of the photoresist layer near the bottom of the vertical window.

Abstract: A two-step metal salicide semiconductor process, suitable for a semiconductor substrate on which gates, sources (drains), spacers, and field oxides are formed. A first metal layer is formed on the gates. A first high-temperature process is executed to form a first metal salicide layer on the gates. A second metal layer is formed on the first metal salicide layer, sources (drains), spacers, and field oxides. A second high-temperature process is executed to form a thicker second metal salicide layer on the gates and a third metal salicide layer on the sources (drains). A wet etching is then performed. A dielectric layer is formded over the semiconductor substrate wherein the horizontal line of the dielectric layer is above the second metal salicide layer. Polishing is then performed. Finally, shallow contact windows and deep contact windows are then formed for the gates and sources (drains), respectively.

Abstract: A metal salicide-CMP-metal salicide semiconductor process, suitable for a semiconductor substrate on which gates, sources (drains), spacers, and field oxides are formed. A first metal layer is formed on gates, sources (drains), spacers, and field oxides. A first high-temperature process is executed to form a first metal salicide layer on gates and sources (drains). A first wet etching is then performed. A first dielectric layer is formed over the semiconductor substrate wherein the horizontal line of the first dielectric layer is above the first metal salicide layer located on gates. A first chemical mechanical polishing (CMP) is then executed until the first metal salicide layer on gates is reached. A second metal layer is formed on the first dielectric layer and on the first metal salicide layer that is located on gates. A second high-temperature process is executed in order to form a thicker second metal salicide layer on the gates. A second wet etching is then performed.

Abstract: A method for manufacturing a DRAM capacitor whose lower electrode has a greater surface area, and is thereby able to increase the capacitance of the capacitor. The method comprises the steps of providing a substrate with a target conductive region and then depositing a first dielectric layer, an etching stop layer and a second dielectric layer sequentially over the target conductive region and the substrate. Next, a deep opening leading to the target conductive region is etched through the various layers, and a first conductive material is deposited to fill the deep opening completely. Thereafter, the second dielectric layer is patterned and etched to form a shallow opening exposing a portion of the first conductive layer and the etching stop layer. Then, a second conductive material is deposited into the exposed first conductive layer and etching stop layer.

Abstract: A method for opening contacts of different depths in a semiconductor wafer after salicide processing. A sacrificial layer is formed over the wafer wherein the wafer further includes a first silicide layer and a second silicide layer formed thereon. The sacrificial layer is selectively removed such that only a portion of the sacrificial layer remains on the first silicide layer. An interlayer dielectric layer is formed over the wafer. The interlayer dielectric layer is planed. Contact windows are patterned. Contacts are opened to reveal the first silicide layer and the second silicide layer as contacts wherein the position where the first silicide layer is formed is higher than that where the second silicide layer is formed. Further, the thickness Y of the sacrificial layer is determined according to the following relation: Y=.DELTA.X.times.R.sub.SAC /(R.sub.ILD -R.sub.SAC), wherein .DELTA.X is the height difference between the first silicide layer and the second silicide layer, and R.sub.SAC and R.sub.

Abstract: A critical dimension (CD) vernier apparatus, appropriate for scanning electron microscope (SEM) measurements, formed with additional encoding patterns. A central strip pattern is disposed along a specific direction. A first plurality of strip patterns is disposed in parallel along the specific direction and at a first side adjacent to the central strip pattern. A second plurality of strip patterns is disposed in parallel along the specific direction and at a second side adjacent to the central strip pattern. A plurality of recognition patterns is selectively added to the strip patterns whereby the central strip pattern, the recognition patterns, and the strip patterns at the first side and the second side form a specific figure to serve as a critical dimension vernier pattern. In addition, a novel critical dimension vernier, which is appropriate for measuring the compliance of contact hole dimensions to process parameters at a specific resolution is provided.