Patents by Inventor Benoit Froment
Benoit Froment has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240040781Abstract: The present description concerns a ROM including at least one first rewritable memory cell. In an embodiment, a method of manufacturing a read-only memory (ROM) comprising a plurality of memory cells is proposed. Each of the plurality of memory cells includes a rewritable first transistor and a rewritable second transistor. An insulated gate of the rewritable first transistor is connected to an insulated gate of the rewritable second transistor. The method includes successively depositing, on a semiconductor structure, a first insulating layer and a first gate layer, wherein the first insulating layer is arranged between the semiconductor structure and the first gate layer, wherein the rewritable second transistor further includes a well-formed between an associated first insulating layer and the semiconductor structure, and wherein the rewritable first insulating layer is in direct contact with the semiconductor structure; and successively depositing a second insulating layer and a second gate layer.Type: ApplicationFiled: October 11, 2023Publication date: February 1, 2024Inventors: Abderrezak Marzaki, Mathieu Lisart, Benoit Froment
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Patent number: 11818883Abstract: The present description concerns a ROM including at least one first rewritable memory cell.Type: GrantFiled: December 1, 2021Date of Patent: November 14, 2023Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics (Rousset) SASInventors: Abderrezak Marzaki, Mathieu Lisart, Benoit Froment
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Publication number: 20220199632Abstract: The present description concerns a ROM including at least one first rewritable memory cell.Type: ApplicationFiled: December 1, 2021Publication date: June 23, 2022Inventors: Abderrezak Marzaki, Mathieu Lisart, Benoit Froment
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Publication number: 20220131005Abstract: An integrated circuit includes a semiconductor substrate having a first type of conductivity and a semiconductor component. The semiconductor component includes: a buried semiconductor region having a second type of conductivity opposite to the first type of conductivity; a first gate region and a second gate region each extending in depth from a front face of the semiconductor substrate to the buried semiconductor region; a third gate region extending in depth from the front face of the semiconductor substrate and being electrically connected to the buried semiconductor region; and an active area delimited by the first gate region, the second gate region and the buried semiconductor region.Type: ApplicationFiled: October 19, 2021Publication date: April 28, 2022Applicant: STMicroelectronics (Crolles 2) SASInventors: Benoit FROMENT, Thomas CABOUT
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Publication number: 20220045020Abstract: A method for fabricating a semiconductor chip includes forming a plurality of conducting pads at a front face of a substrate, thinning a rear face of the substrate, etching openings under each conducting pad from the rear face, depositing a layer of a dielectric on walls and a bottom of the openings, forming a conducting material in the openings, and forming a conducting strip on the rear face. The conducting strip is electrically connected to the conducting material of each of the openings. The etching is stopped when the respective conducting pad is reached.Type: ApplicationFiled: October 21, 2021Publication date: February 10, 2022Inventors: Sebastien Petitdidier, Nicolas Hotellier, Raul Andres Bianchi, Alexis Farcy, Benoit Froment
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Publication number: 20210399094Abstract: An electronic component is formed on and in a semiconductor substrate. The component includes source and drain regions and a gate region between the source and drain regions. Two dielectric lateral spacing regions are provided on the semiconductor substrate against sides of the gate region. An electrical connection, formed by a silicide on a surface of at least one of said dielectric lateral spacing region, is configured to electrically connect the gate region to at least one of the source region and the drain region.Type: ApplicationFiled: June 21, 2021Publication date: December 23, 2021Applicant: STMicroelectronics (Crolles 2) SASInventor: Benoit FROMENT
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Publication number: 20210377058Abstract: An integrated physical unclonable function device includes at least one reference capacitor and a number of comparison capacitors. A capacitance determination circuit operates to determine a capacitance of the at least one reference capacitor and a capacitance of each comparison capacitor. The determined capacitances of the comparison capacitors are then compared to the determined capacitance of the reference capacitor by a comparison circuit. A digital word is then generated with bit values indicative of a result of the comparisons made by the comparison circuit.Type: ApplicationFiled: May 25, 2021Publication date: December 2, 2021Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics (Rousset) SASInventors: Benoit Froment, Jean-Marc Voisin
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Patent number: 11183468Abstract: A semiconductor chip includes at least two insulated vias passing through the chip from the front face to the rear face in which, on the side of the rear face, the vias are connected to one and the same conducting strip and, on the side of the front face, each via is separated from a conducting pad by a layer of a dielectric.Type: GrantFiled: June 30, 2017Date of Patent: November 23, 2021Assignee: STMICROELECTRONICS (CROLLES 2) SASInventors: Sebastien Petitdidier, Nicolas Hotellier, Raul Andres Bianchi, Alexis Farcy, Benoît Froment
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Patent number: 10833027Abstract: An integrated device for physically unclonable functions is based on a set of MOS transistors exhibiting a random distribution of threshold voltages which are obtained by lateral implantations of dopants exhibiting non-predictable characteristics, resulting from implantations through a polysilicon layer. A certain number of these transistors form a group of gauge transistors which makes it possible to define a mean gate source voltage making it possible to bias the gates of certain others of these transistors (which are used to define the various bits of the unique code generated by the function). All these transistors consequently exhibit a random distribution of drain-source currents and a comparison of each drain-source current of a transistor associated with a bit of the digital code with a reference current corresponding to the average of this distribution makes it possible to define the logical value 0 or 1 of this bit.Type: GrantFiled: October 16, 2017Date of Patent: November 10, 2020Assignees: STMICROELECTRONICS (CROLLES 2) SAS, STMICROELECTRONICS (ROUSSET) SASInventors: Mathieu Lisart, Raul Andres Bianchi, Benoit Froment
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Patent number: 10770357Abstract: An integrated circuit includes a semiconductor substrate with an electrically isolated semiconductor well. An upper trench isolation extends from a front face of the semiconductor well to a depth located a distance from the bottom of the well. Two additional isolating zones are electrically insulated from the semiconductor well and extending inside the semiconductor well in a first direction and vertically from the front face to the bottom of the semiconductor well. At least one hemmed resistive region is bounded by the two additional isolating zones, the upper trench isolation and the bottom of the semiconductor well. Electrical contacts are electrically coupled to the hemmed resistive region.Type: GrantFiled: June 3, 2019Date of Patent: September 8, 2020Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics (Rousset) SASInventors: Benoit Froment, Stephan Niel, Arnaud Regnier, Abderrezak Marzaki
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Patent number: 10754618Abstract: A random number generation device includes conductive lines including interruptions and a number of conductive vias. A via is located at each interruption. Each via randomly fills or does not fill the interruption. A circuit is capable of determining the electric continuity or lack of continuity of the conductive lines.Type: GrantFiled: July 16, 2018Date of Patent: August 25, 2020Assignees: STMicroelectronics (Rousset) SAS, STMicroelectronics (Crolles 2) SASInventors: Benoit Froment, Sebastien Petitdidier, Mathieu Lisart, Jean-Marc Voisin
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Patent number: 10497653Abstract: A decoupling capacitor includes: two capacitor cells sharing the same well; a first trench isolation passing through the well between the two cells without reaching the bottom of the well; and a contact with the well formed in each cell.Type: GrantFiled: October 19, 2017Date of Patent: December 3, 2019Assignees: STMICROELECTRONICS (CROLLES 2) SAS, STMICROELECTRONICS (ROUSSET) SASInventors: Mathieu Lisart, Benoit Froment
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Publication number: 20190287862Abstract: An integrated circuit includes a semiconductor substrate with an electrically isolated semiconductor well. An upper trench isolation extends from a front face of the semiconductor well to a depth located a distance from the bottom of the well. Two additional isolating zones are electrically insulated from the semiconductor well and extending inside the semiconductor well in a first direction and vertically from the front face to the bottom of the semiconductor well. At least one hemmed resistive region is bounded by the two additional isolating zones, the upper trench isolation and the bottom of the semiconductor well. Electrical contacts are electrically coupled to the hemmed resistive region.Type: ApplicationFiled: June 3, 2019Publication date: September 19, 2019Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics (Rousset) SASInventors: Benoit FROMENT, Stephan NIEL, Arnaud REGNIER, Abderrezak MARZAKI
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Patent number: 10354926Abstract: An integrated circuit includes a semiconductor substrate with an electrically isolated semiconductor well. An upper trench isolation extends from a front face of the semiconductor well to a depth located a distance from the bottom of the well. Two additional isolating zones are electrically insulated from the semiconductor well and extending inside the semiconductor well in a first direction and vertically from the front face to the bottom of the semiconductor well. At least one hemmed resistive region is bounded by the two additional isolating zones, the upper trench isolation and the bottom of the semiconductor well. Electrical contacts are electrically coupled to the hemmed resistive region.Type: GrantFiled: October 3, 2017Date of Patent: July 16, 2019Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics (Rousset) SASInventors: Benoît Froment, Stephan Niel, Arnaud Regnier, Abderrezak Marzaki
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Publication number: 20190034168Abstract: A random number generation device includes conductive lines including interruptions and a number of conductive vias. A via is located at each interruption. Each via randomly fills or does not fill the interruption. A circuit is capable of determining the electric continuity or lack of continuity of the conductive lines.Type: ApplicationFiled: July 16, 2018Publication date: January 31, 2019Inventors: Benoit Froment, Sebastien Petitdidier, Mathieu Lisart, Jean-Marc Voisin
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Publication number: 20180277496Abstract: An integrated device for physically unclonable functions is based on a set of MOS transistors exhibiting a random distribution of threshold voltages which are obtained by lateral implantations of dopants exhibiting non-predictable characteristics, resulting from implantations through a polysilicon layer. A certain number of these transistors form a group of gauge transistors which makes it possible to define a mean gate source voltage making it possible to bias the gates of certain others of these transistors (which are used to define the various bits of the unique code generated by the function). All these transistors consequently exhibit a random distribution of drain-source currents and a comparison of each drain-source current of a transistor associated with a bit of the digital code with a reference current corresponding to the average of this distribution makes it possible to define the logical value 0 or 1 of this bit.Type: ApplicationFiled: October 16, 2017Publication date: September 27, 2018Inventors: Mathieu Lisart, Raul Andres Bianchi, Benoit Froment
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Publication number: 20180247874Abstract: An integrated circuit includes a semiconductor substrate with an electrically isolated semiconductor well. An upper trench isolation extends from a front face of the semiconductor well to a depth located a distance from the bottom of the well. Two additional isolating zones are electrically insulated from the semiconductor well and extending inside the semiconductor well in a first direction and vertically from the front face to the bottom of the semiconductor well. At least one hemmed resistive region is bounded by the two additional isolating zones, the upper trench isolation and the bottom of the semiconductor well. Electrical contacts are electrically coupled to the hemmed resistive region.Type: ApplicationFiled: October 3, 2017Publication date: August 30, 2018Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics (Rousset) SASInventors: Benoît Froment, Stephan Niel, Arnaud Regnier, Abderrezak Marzaki
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Publication number: 20180233460Abstract: A decoupling capacitor includes: two capacitor cells sharing the same well; a first trench isolation passing through the well between the two cells without reaching the bottom of the well; and a contact with the well formed in each cell.Type: ApplicationFiled: October 19, 2017Publication date: August 16, 2018Inventors: Mathieu Lisart, Benoit Froment
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Publication number: 20180061781Abstract: A semiconductor chip includes at least two insulated vias passing through the chip from the front face to the rear face in which, on the side of the rear face, the vias are connected to one and the same conducting strip and, on the side of the front face, each via is separated from a conducting pad by a layer of a dielectric.Type: ApplicationFiled: June 30, 2017Publication date: March 1, 2018Inventors: Sebastien Petitdidier, Nicolas Hotellier, Raul Andres Bianchi, Alexis Farcy, Benoît Froment
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Patent number: 8975682Abstract: An integrated circuit (IC) includes at least one capacitor with metal electrodes. At least one of the electrodes (10 or 30) is formed from at least surface-silicided hemispherical grain silicon or silicon alloy. A fabrication process for obtaining such a capacitor with silicided metal electrodes is also provided.Type: GrantFiled: August 23, 2010Date of Patent: March 10, 2015Assignee: STMicroelectronics (Crolles 2) SASInventors: Aomar Halimaoui, Rebha El Farhane, Benoit Froment