Abstract: At least one layer of a dielectric material 3 is deposited on a copper track 1 covered with an encapsulation layer 2. A cavity 6 is etched in the layer of dielectric material at the location of the future vertical connection. At least one protective layer is deposited in said cavity to preclude diffusion of copper 7. The protective layer 7 at the bottom of the cavity 6 is subjected to an anisotropic etching treatment and also the encapsulation layer 2 is subjected to etching, whereafter the cavity is filled with copper. The copper particles pulverized during etching the encapsulation layer do not contaminate the dielectric material 3.

Abstract: A device includes a capacitive structure including an input node and n output nodes, r integrated capacitors connected in series between two adjacent nodes, an integrated capacitor connected between the input node and ground, an integrated capacitor connected between the nth output node and ground, and r capacitive branches connected in parallel between ground and each node of the capacitive structure including the first output node and the (n−1)th output node. Each branch may include r+1 series-connected integrated capacitors. Furthermore, the integrated capacitors of the capacitive structure are theoretically identical. The device may also include a charge source for charging each node of the capacitive structure. Additionally, a measurement circuit may measure the charge at each of the nodes of the structure, and a comparison circuit may compare each measured nodal charge value with a theoretical nodal charge value while taking into account a predetermined nodal tolerance.

Abstract: A device includes a capacitive structure including an input node and n output nodes, r integrated capacitors connected in series between two adjacent nodes, an integrated capacitor connected between the input node and ground, an integrated capacitor connected between the nth output node and ground, and r capacitive branches connected in parallel between ground and each node of the capacitive structure including the first output node and the (n−1)th output node. Each branch may include r+1 series-connected integrated capacitors. Furthermore, the integrated capacitors of the capacitive structure are theoretically identical. The device may also include a charge source for charging each node of the capacitive structure. Additionally, a measurement circuit may measure the charge at each of the nodes of the structure, and a comparison circuit may compare each measured nodal charge value with a theoretical nodal charge value while taking into account a predetermined nodal tolerance.

Abstract: A test structure includes a single current-measuring means for measuring current between a supply terminal and ground, and first and second branches for measuring capacitance between first and second metal lines. The first branch includes a first switch coupled between the current-measuring means and the first line, and a second switch coupled between the first line and ground. Similarly, the second branch includes a third switch coupled between the current-measuring means and the second line, and a fourth switch coupled between the second line and ground. A method for testing a circuit is also provided.