Abstract: A package substrate includes: a glass frame having a through hole and a chip embedding cavity; an electronic component arranged in the chip embedding cavity; a dielectric layer filled on an upper surface of the glass frame and in the chip embedding cavity; a metal pillar passing through the through hole; a circuit layer arranged on the upper surface and/or a lower surface of the glass frame and connected to the electronic component and the metal pillar; and a solder mask arranged on a surface of the circuit layer and having a pad which is connected to the circuit layer.

Abstract: A hybrid embedded packaging structure and a manufacturing method thereof are disclosed. The structure includes: a substrate with a first insulating layer, a conductive copper column, a chip-embedded cavity and a first circuit layer; a first electronic device arranged inside the chip-embedded cavity; a second electronic device arranged on a back surface of the first electronic device; a second insulating layer covering and filling the chip-embedded cavity and an upper layer of the substrate, exposing part of the first circuit layer and a back surface of part of the second electronic device or part of the first electronic device; a second circuit layer electrically connected with the conductive copper column and a terminal of the first electronic device; a conducting wire electrically connecting the first circuit layer with a terminal of the second electronic device; and a protection cover arranged on the top surface of the substrate.

Abstract: A cavity substrate may have a directional optoelectronic transmission channel. The cavity substrate includes a support frame, a first dielectric layer on a first surface of the support frame, and a second dielectric layer on a second surface of the support frame. The support frame, the first dielectric layer and the second dielectric layer constitute a closed cavity having an opening on one side in the length direction of the substrate, a first circuit layer is arranged on the inner surface of the first dielectric layer facing the cavity, an electrode connected with an optical communication device is arranged on the first circuit layer, the electrode is electrically conducted with the first circuit layer, a second circuit layer is arranged on the outer surfaces of the first dielectric layer and the second dielectric layer, and the first circuit layer and the second circuit layer are communicated through a via column.

Abstract: Disclosed are a method for manufacturing a support frame structure and a support frame structure. The method includes steps of: providing a metal plate including a support region and an opening region; forming an upper dielectric hole and a lower dielectric hole respectively at an upper surface and a lower surface of the support region by photolithography, with a metal spacer connected between the upper dielectric hole and the lower dielectric hole; forming an upper metal pillar on an upper surface of the metal plate, and laminating an upper dielectric layer which covers the upper metal pillar and the upper dielectric hole; etching the metal spacer, forming a lower metal pillar on the lower surface of the metal plate, and laminating a lower dielectric layer which covers the lower metal pillar and the lower dielectric hole.

Abstract: A cyclic cooling embedded packaging substrate and a manufacturing method thereof are disclosed. The packaging substrate includes a dielectric material body, a chip, a first metal face, a second metal face and a first trace. The dielectric material body is provided with a packaging cavity, the chip is packaged in the packaging cavity, the first metal face is embedded in the dielectric material body, covers and is connected to a heat dissipation face of the chip. The second metal face is embedded in the dielectric material body, connected to a surface of the first metal face, and is provided with a first cooling channel pattern for forming a cooling channel. The first trace is arranged on a surface of the dielectric material body or embedded therein, and is connected with a corresponding terminal on an active face of the chip through a first conductive structure.

Abstract: A package structure with a wettable side surface and a manufacturing method thereof, and a vertical package module are disclosed. The package structure includes a first dielectric layer, a chip and a circuit layer. The first dielectric layer is provided with a package cavity, side wall bonding pads are arranged on a side wall of the first dielectric layer and located outside the package cavity. The chip is packaged inside the package cavity, pins of the chip face first surface of the first dielectric layer. The circuit layer is arranged on the first surface of the first dielectric layer, and the circuit layer is directly or indirectly connected to the side wall bonding pads and the pins of the chip.

Abstract: A method for manufacturing a package substrate, includes: providing a glass frame having a through hole and a chip embedding cavity; fixing an electronic component in the chip embedding cavity; coating a dielectric layer to an upper surface of the glass frame, the through hole and the chip embedding cavity and curing the dielectric layer; photoetching the dielectric layer to form an opening window arranged above the through hole; depositing metal through the opening window and patterning the metal to form a metal pillar and a circuit layer, the metal pillar passing through the through hole, the circuit layer being arranged on the upper surface and/or a lower surface of the glass frame and being connected to the electronic component and the metal pillar; forming a solder mask on a surface of the circuit layer, patterning the solder mask to form a pad connected to the circuit layer.

Abstract: A multi-device graded embedding package substrate includes a first dielectric layer, a second dielectric layer, and a third dielectric layer. The first dielectric layer includes a first conductive copper pillar layer and a first device cavity. The second dielectric layer includes a first wiring layer located in a lower surface of the second dielectric layer, a second conductive copper pillar layer and a heat dissipation copper block layer provided on the first wiring layer. The third dielectric layer includes a second wiring layer, a third conductive copper pillar layer provided on the second wiring layer. A first device is attached to the bottom of the first device cavity, and a terminal of the first device is in conductive connection with the second wiring layer. A second device is attached to the bottom of a second device cavity penetrating through the first, second and third dielectric layers.

Abstract: A passive device packaging structure embedded in a glass medium according to an embodiment of the present disclosures includes a glass substrate and at least one capacitor embedded in the glass substrate. The capacitor includes an upper electrode, a dielectric layer, and a lower electrode. The glass substrate is provided on its upper surface with a cavity, the dielectric layer covers a surface of the cavity and has an area larger than that of the cavity. The upper electrode is provided on the dielectric layer. The dielectric layer and the lower electrode are connected by a metal via pillar passing through the glass substrate.

Abstract: Disclosed are a heat dissipation-electromagnetic shielding embedded packaging structure, a manufacturing method thereof, and a substrate. The heat dissipation-electromagnetic shielding embedded packaging structure includes: a dielectric layer including an upper surface and a lower surface, wherein at least one hollow cavity unit is disposed inside the dielectric layer; an insulating layer disposed in the hollow cavity unit, wherein the hollow cavity unit is partially filled with the insulating layer; an electronic element, wherein one end is embedded in the insulating layer, the other end is exposed in the hollow cavity unit, and the electronic element includes terminals; a through hole penetrating through the upper surface and the lower surface of the dielectric layer and communicating with the terminals; and a metal layer covering the six surfaces of the dielectric layer and the interior of the through hole to form a shielding layer and circuit layer respectively.

Abstract: A multilayer embedded packaging structure according to an embodiment includes a first dielectric layer and a second dielectric layer on the first dielectric layer. The first dielectric layer includes a first wiring layer. The second dielectric layer includes a first copper pillar layer and a device placement port frame penetrating through the second dielectric layer in a height direction, and a second wiring layer on the first copper pillar layer. A second copper pillar layer is on the second wiring layer. The first wiring layer and the second wiring layer are conductively connected via the first copper pillar layer. A first device is mounted to the bottom of the device placement port frame, a second device is mounted to the second dielectric layer, and a third device is mounted to an end of the second copper pillar layer.

Abstract: An embedded package structure having a shielding cavity according to an embodiment of the present disclosure includes a device embedded in an insulating layer, and a shielding cavity enclosing the device, wherein the shielding cavity is defined by a shielding wall embedded in the insulating layer and surrounding the device on four sides, and first and second wiring layers which cover first and second end faces of the shielding wall and are electrically connected with the shielding wall; wherein a signal line leading-out opening is to formed between the first end face of the shielding wall and the first wiring layer, and a signal line connected with a terminal of the device is led, from the signal line leading-out opening, out of the shielding cavity.

Abstract: A temporary carrier according to an embodiment of the present invention may include a core layer, a first Cu foil layer and a second Cu foil layer on surfaces of both sides of the core layer. Each of the first Cu foil layer and the second Cu foil layer may include double Cu foils which are physically attached together.

Abstract: A temporary carrier plate according to an embodiment of the present disclosure includes a first carrier core layer, a first copper foil layer on the first carrier core layer, a second carrier core layer on the first copper foil layer, and a second copper foil layer on the second carrier core layer, wherein the first copper foil layer includes physically press-fitted first outer-layer copper foil and first inner-layer copper foil, and the second copper foil layer includes physically press-fitted second outer-layer copper foil and second inner-layer copper foil.

Abstract: An inductor-integrating embedded support frame according to an embodiment of the present disclosure includes a core dielectric layer, a through-opening penetrating through the core dielectric layer, wherein the through-opening is used for embedding and installing a device, and an inductor, wherein the inductor includes a magnetic core embedded in the core dielectric layer and an inductance coil wound around the magnetic core, wherein at least one conductive copper pillar penetrating through the core dielectric layer is provided at the periphery of the through-opening and the inductor.

Abstract: A packaging structure with an antenna and a manufacturing method thereof are disclosed. The packaging structure includes a package, an antenna circuit, an interconnecting circuit, an outer-layer circuit, and a chip. The package is internally packaged with a first conducting through hole column and a second conducting through hole column. The antenna circuit is disposed on a first surface and a sidewall of the package. The interconnecting circuit is packaged in the package, and is connected to the antenna circuit by the first conducting through hole column. The outer-layer circuit is disposed on a second surface of the package, and is connected to the interconnecting circuit by the second conducting through hole column. The outer-layer circuit is further connected to a conductive pin. The chip is packaged in the package, and is connected to the interconnecting circuit or the outer-layer circuit.

Abstract: A temporary carrier according to an embodiment of the present invention may include a core layer, a first Cu foil layer and a second Cu foil layer on surfaces of both sides of the core layer. Each of the first Cu foil layer and the second Cu foil layer may include double Cu foils which are physically attached together.

Abstract: Disclosed is a substrate manufacturing method for realizing three-dimensional packaging, which includes: preparing a base plate, the base plate including a dielectric material layer, a first sidewall pad, a first through-hole pillar and a cavity, the cavity being filled with a first metal block; processing a first circuit layer and a second circuit layer, the first circuit layer including a first padding plate and a second metal block, and the second circuit layer including a second padding plate and a plurality of pin pads; processing and laminating interlayer through-hole pillars; processing a third circuit layer and a fourth circuit layer, the third circuit layer including a second sidewall pad and the fourth circuit layer including a routing circuit; and etching to expose the first sidewall pad, the second sidewall pad and the pin pads.

Abstract: Disclosed are a package structure of an integrated passive device and a manufacturing method thereof and a substrate. The method includes: providing an organic frame having a chip embedding cavity and a metal pillar, laminating at least one layer of first dielectric on an upper surface of the organic frame, and processing the first dielectric by photolithography to form an opening correspondingly above the chip embedding cavity; mounting an electronic component in the chip embedding cavity through the opening, the electronic component including an upper and lower electrodes; laminating and curing a second dielectric into the chip embedding cavity and on an upper surface of the first dielectric, thinning the first and second dielectrics to expose the upper and lower electrodes, upper and lower surfaces of the metal pillar; performing metal electroplating to form a circuit layer communicated with the upper and lower electrodes and the metal pillar.

Abstract: A cavity substrate may have a directional optoelectronic transmission channel. The cavity substrate includes a support frame, a first dielectric layer on a first surface of the support frame, and a second dielectric layer on a second surface of the support frame. The support frame, the first dielectric layer and the second dielectric layer constitute a closed cavity having an opening on one side in the length direction of the substrate, a first circuit layer is arranged on the inner surface of the first dielectric layer facing the cavity, an electrode connected with an optical communication device is arranged on the first circuit layer, the electrode is electrically conducted with the first circuit layer, a second circuit layer is arranged on the outer surfaces of the first dielectric layer and the second dielectric layer, and the first circuit layer and the second circuit layer are communicated through a via column.