Abstract: The present technology relates to an electronic device. A memory device according to the present technology may include a first plane, a second plane, a data input/output circuit, and an encoder. The data input/output circuit may output data read from the first and second planes. The encoder may compress second data read from the second plane while first data read from the first plane is being output. The data input/output circuit may output the compressed second data after outputting the first data.

Abstract: A memory system includes at least one memory die and a controller coupled to the at least one memory die via a data path. The at least one memory die includes plural memory planes and a register storing operation statuses and operation results regarding the respective memory planes. The controller transfers a first status check command to the at least one memory die and receives a first response including the operation statuses and the operation results regarding the respective memory planes.

Abstract: A memory device includes a first memory group including plural first non-volatile memory cells capable of storing multi-bit data, and a second memory group including plural second non-volatile memory cells capable of storing single-bit data. A program operation controller builds the multi-bit data based on data inputted from an external device, performs a logical operation regarding partial data among the multi-bit data to generate a parity, programs the parity in the second memory group after programming the partial data in the first memory group, perform a verification operation regarding the partial data after a sudden power-off (SPO) occurs, recovers the partial data based on the parity and a result of the verification operation, and programs recovered partial data in the first memory group.

Abstract: A memory device may include: a plurality of planes, each suitable for inputting/outputting data in units of pages, a latch suitable for performing a read operation on one or more planes of the plurality of planes in response to one or more read commands, receiving data from any one plane, among the plurality of planes, and storing the received data, and a logic controller suitable for comparing first plane information, corresponding to the data that is stored in the latch, to second plane information, corresponding to an output command that is received after the read command is received, in response to the output command, and suitable for selectively outputting the data of the latch.

Abstract: A memory controller controls an address such that a number of chips included in a memory device can increase. The memory controller includes a flash translation layer configured to translate a logical block address received from a host into a physical block address, wherein the flash translation layer determines an addressing unit of at least one of a plurality of addresses in the physical block address based on a request received from the host and a command controller configured to generate a command representing the addressing unit based on the request.

Abstract: A memory device includes a first memory group including plural first non-volatile memory cells capable of storing multi-bit data, and a second memory group including plural second non-volatile memory cells capable of storing single-bit data. A program operation controller builds the multi-bit data based on data inputted from an external device, performs a logical operation regarding partial data among the multi-bit data to generate a parity, programs the parity in the second memory group after programming the partial data in the first memory group, perform a verification operation regarding the partial data after a sudden power-off (SPO) occurs, recovers the partial data based on the parity and a result of the verification operation, and programs recovered partial data in the first memory group.

Abstract: A memory system includes at least one memory die and a controller coupled to the at least one memory die via a data path. The at least one memory die includes plural memory planes and a register storing operation statuses and operation results regarding the respective memory planes. The controller transfers a first status check command to the at least one memory die and receives a first response including the operation statuses and the operation results regarding the respective memory planes.

Abstract: A memory device includes: a plurality of memory cells grouped into a plurality of planes; page buffer groups corresponding to respective ones of the plurality of planes, the page buffer groups including a plurality of page buffer circuits, each of the plurality of page buffer circuits including cache latches which are configured to receive data to be stored in memory cells in the plurality of planes; and control logic for controlling the page buffer groups to simultaneously initialize cache latches corresponding to at least two planes, among the cache latches, in response to a multi-plane program command, wherein the multi-plane program command instructs a multi-plane program operation of simultaneously storing data in plural planes among the plurality of planes.

Abstract: A storage device includes a memory device and a memory controller. The memory device includes a first plane and a second plane, each including data blocks configured to store user data, one or more replacement blocks configured to replace one or more bad blocks, and system blocks configured to store system information. The memory controller is configured to replace, when a bad block is detected in the first plane after all the one or more replacement blocks in the first plane are used to replace previously detected bad blocks, the detected bad block with a target system block selected among the system blocks in the first plane.

Abstract: A memory controller may control a memory device including a first storage area and a second storage area. The memory controller may include: a memory operation controller and a block information manager. The memory operation controller may control the memory device to perform a block merge operation of programming data stored in a victim block among normal blocks of the first storage area to a target block among the normal blocks, and perform a data migration operation of copying data stored in blocks of the first storage area to blocks of the second storage area. The block information manager may store block map information indicating whether each of the blocks of the first storage area is a normal block or a merge block. The target block may be changed from a normal block to a merge block by the block merge operation.

Abstract: An electronic device, and more particularly, a storage device for mitigating periods where a peak current occurs from currents overlapping is provided. The storage device includes a memory device including a plurality of dies and a memory controller controlling the memory device. The memory device generates status information about an amount of current consumed by each of the plurality of dies during a busy period when all of the plurality of dies are in a busy state, and wherein the memory controller determines, based on the status information, whether peak currents for multiple dies of the plurality of dies are consumed in a common sub-period of a plurality of sub-periods which span the busy period, and when it is determined that peak currents for multiple dies are consumed in the common sub-period, the memory controller controls the memory device to suspend an operation on a die among the plurality of dies.

Abstract: A memory device includes: a plurality of memory cells grouped into a plurality of planes; page buffer groups corresponding to respective ones of the plurality of planes, the page buffer groups including a plurality of page buffer circuits, each of the plurality of page buffer circuits including cache latches which are configured to receive data to be stored in memory cells in the plurality of planes; and control logic for controlling the page buffer groups to simultaneously initialize cache latches corresponding to at least two planes, among the cache latches, in response to a multi-plane program command, wherein the multi-plane program command instructs a multi-plane program operation of simultaneously storing data in plural planes among the plurality of planes.

Abstract: A memory controller for controlling a memory device for storing data, the memory controller, the memory controller comprising: a request transmitter for providing a program suspend request for suspending a program operation, when the memory device receives a read request from a host while the memory device is performing the program operation and a command controller for generating and outputting a program suspend command, based on the program suspend request, and outputting a cache read command or normal read command, based on a number of commands corresponding to a request received from the host, which are queued in a command queue.

Abstract: A storage device includes a memory device and a memory controller. The memory device includes a first plane and a second plane, each including data blocks configured to store user data, one or more replacement blocks configured to replace one or more bad blocks, and system blocks configured to store system information. The memory controller is configured to replace, when a bad block is detected in the first plane after all the one or more replacement blocks in the first plane are used to replace previously detected bad blocks, the detected bad block with a target system block selected among the system blocks in the first plane.

Abstract: An electronic device, and more particularly, a storage device for mitigating periods where a peak current occurs from currents overlapping is provided. The storage device includes a memory device including a plurality of dies and a memory controller controlling the memory device. The memory device generates status information about an amount of current consumed by each of the plurality of dies during a busy period when all of the plurality of dies are in a busy state, and wherein the memory controller determines, based on the status information, whether peak currents for multiple dies of the plurality of dies are consumed in a common sub-period of a plurality of sub-periods which span the busy period, and when it is determined that peak currents for multiple dies are consumed in the common sub-period, the memory controller controls the memory device to suspend an operation on a die among the plurality of dies.

Abstract: A memory controller controls an address such that a number of chips included in a memory device can increase. The memory controller includes a flash translation layer configured to translate a logical block address received from a host into a physical block address, wherein the flash translation layer determines an addressing unit of at least one of a plurality of addresses in the physical block address based on a request received from the host and a command controller configured to generate a command representing the addressing unit based on the request.

Abstract: A semiconductor memory device according to the present disclosure includes: a memory cell array including a plurality of planes; a command processing unit configured to generate an internal command to be executed by at least one plane among the plurality of planes on the basis of external commands received from an external controller; a status register configured to store status information of the external commands by a tag included in the external command according to results of performing the internal command.

Abstract: There are provided a memory system and an operating method thereof. The memory system includes a semiconductor memory configured to perform a memory operation and perform a suspend operation of suspending a currently performed memory operation and a controller configured to control the memory operation. The controller controls the semiconductor memory to perform the suspend operation in a suspension-allowed period by determining a detailed operation period of the currently performed memory operation.

Abstract: There are provided a memory system and an operating method thereof. The memory system includes a semiconductor memory configured to perform a memory operation and perform a suspend operation of suspending a currently performed memory operation and a controller configured to control the memory operation. The controller controls the semiconductor memory to perform the suspend operation in a suspension-allowed period by determining a detailed operation period of the currently performed memory operation.

Abstract: There are provided a memory system and an operating method thereof. The memory system includes a semiconductor memory configured to perform a memory operation and perform a suspend operation of suspending a currently performed memory operation and a controller configured to control the memory operation. The controller controls the semiconductor memory to perform the suspend operation in a suspension-allowed period by determining a detailed operation period of the currently performed memory operation.